1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35
36 #include "radeon.h"
37 #include "r600d.h"
38
39 /* 1 second timeout */
40 #define UVD_IDLE_TIMEOUT_MS 1000
41
42 /* Firmware Names */
43 #define FIRMWARE_R600 "radeon/R600_uvd.bin"
44 #define FIRMWARE_RS780 "radeon/RS780_uvd.bin"
45 #define FIRMWARE_RV770 "radeon/RV770_uvd.bin"
46 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
47 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
48 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
49 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
50 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"
51
52 MODULE_FIRMWARE(FIRMWARE_R600);
53 MODULE_FIRMWARE(FIRMWARE_RS780);
54 MODULE_FIRMWARE(FIRMWARE_RV770);
55 MODULE_FIRMWARE(FIRMWARE_RV710);
56 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
57 MODULE_FIRMWARE(FIRMWARE_SUMO);
58 MODULE_FIRMWARE(FIRMWARE_TAHITI);
59 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
60
61 static void radeon_uvd_idle_work_handler(struct work_struct *work);
62
radeon_uvd_init(struct radeon_device * rdev)63 int radeon_uvd_init(struct radeon_device *rdev)
64 {
65 unsigned long bo_size;
66 const char *fw_name;
67 int i, r;
68
69 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
70
71 switch (rdev->family) {
72 case CHIP_RV610:
73 case CHIP_RV630:
74 case CHIP_RV670:
75 case CHIP_RV620:
76 case CHIP_RV635:
77 fw_name = FIRMWARE_R600;
78 break;
79
80 case CHIP_RS780:
81 case CHIP_RS880:
82 fw_name = FIRMWARE_RS780;
83 break;
84
85 case CHIP_RV770:
86 fw_name = FIRMWARE_RV770;
87 break;
88
89 case CHIP_RV710:
90 case CHIP_RV730:
91 case CHIP_RV740:
92 fw_name = FIRMWARE_RV710;
93 break;
94
95 case CHIP_CYPRESS:
96 case CHIP_HEMLOCK:
97 case CHIP_JUNIPER:
98 case CHIP_REDWOOD:
99 case CHIP_CEDAR:
100 fw_name = FIRMWARE_CYPRESS;
101 break;
102
103 case CHIP_SUMO:
104 case CHIP_SUMO2:
105 case CHIP_PALM:
106 case CHIP_CAYMAN:
107 case CHIP_BARTS:
108 case CHIP_TURKS:
109 case CHIP_CAICOS:
110 fw_name = FIRMWARE_SUMO;
111 break;
112
113 case CHIP_TAHITI:
114 case CHIP_VERDE:
115 case CHIP_PITCAIRN:
116 case CHIP_ARUBA:
117 case CHIP_OLAND:
118 fw_name = FIRMWARE_TAHITI;
119 break;
120
121 case CHIP_BONAIRE:
122 case CHIP_KABINI:
123 case CHIP_KAVERI:
124 case CHIP_HAWAII:
125 case CHIP_MULLINS:
126 fw_name = FIRMWARE_BONAIRE;
127 break;
128
129 default:
130 return -EINVAL;
131 }
132
133 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
134 if (r) {
135 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
136 fw_name);
137 return r;
138 }
139
140 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
141 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
142 RADEON_GPU_PAGE_SIZE;
143 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
144 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
145 NULL, &rdev->uvd.vcpu_bo);
146 if (r) {
147 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
148 return r;
149 }
150
151 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
152 if (r) {
153 radeon_bo_unref(&rdev->uvd.vcpu_bo);
154 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
155 return r;
156 }
157
158 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
159 &rdev->uvd.gpu_addr);
160 if (r) {
161 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
162 radeon_bo_unref(&rdev->uvd.vcpu_bo);
163 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
164 return r;
165 }
166
167 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
168 if (r) {
169 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
170 return r;
171 }
172
173 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
174
175 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
176 atomic_set(&rdev->uvd.handles[i], 0);
177 rdev->uvd.filp[i] = NULL;
178 rdev->uvd.img_size[i] = 0;
179 }
180
181 return 0;
182 }
183
radeon_uvd_fini(struct radeon_device * rdev)184 void radeon_uvd_fini(struct radeon_device *rdev)
185 {
186 int r;
187
188 if (rdev->uvd.vcpu_bo == NULL)
189 return;
190
191 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
192 if (!r) {
193 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
194 radeon_bo_unpin(rdev->uvd.vcpu_bo);
195 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
196 }
197
198 radeon_bo_unref(&rdev->uvd.vcpu_bo);
199
200 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
201
202 release_firmware(rdev->uvd_fw);
203 }
204
radeon_uvd_suspend(struct radeon_device * rdev)205 int radeon_uvd_suspend(struct radeon_device *rdev)
206 {
207 unsigned size;
208 void *ptr;
209 int i;
210
211 if (rdev->uvd.vcpu_bo == NULL)
212 return 0;
213
214 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
215 if (atomic_read(&rdev->uvd.handles[i]))
216 break;
217
218 if (i == RADEON_MAX_UVD_HANDLES)
219 return 0;
220
221 size = radeon_bo_size(rdev->uvd.vcpu_bo);
222 size -= rdev->uvd_fw->size;
223
224 ptr = rdev->uvd.cpu_addr;
225 ptr += rdev->uvd_fw->size;
226
227 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
228 memcpy(rdev->uvd.saved_bo, ptr, size);
229
230 return 0;
231 }
232
radeon_uvd_resume(struct radeon_device * rdev)233 int radeon_uvd_resume(struct radeon_device *rdev)
234 {
235 unsigned size;
236 void *ptr;
237
238 if (rdev->uvd.vcpu_bo == NULL)
239 return -EINVAL;
240
241 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
242
243 size = radeon_bo_size(rdev->uvd.vcpu_bo);
244 size -= rdev->uvd_fw->size;
245
246 ptr = rdev->uvd.cpu_addr;
247 ptr += rdev->uvd_fw->size;
248
249 if (rdev->uvd.saved_bo != NULL) {
250 memcpy(ptr, rdev->uvd.saved_bo, size);
251 kfree(rdev->uvd.saved_bo);
252 rdev->uvd.saved_bo = NULL;
253 } else
254 memset(ptr, 0, size);
255
256 return 0;
257 }
258
radeon_uvd_force_into_uvd_segment(struct radeon_bo * rbo,uint32_t allowed_domains)259 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
260 uint32_t allowed_domains)
261 {
262 int i;
263
264 for (i = 0; i < rbo->placement.num_placement; ++i) {
265 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
266 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
267 }
268
269 /* If it must be in VRAM it must be in the first segment as well */
270 if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
271 return;
272
273 /* abort if we already have more than one placement */
274 if (rbo->placement.num_placement > 1)
275 return;
276
277 /* add another 256MB segment */
278 rbo->placements[1] = rbo->placements[0];
279 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
280 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
281 rbo->placement.num_placement++;
282 rbo->placement.num_busy_placement++;
283 }
284
radeon_uvd_free_handles(struct radeon_device * rdev,struct drm_file * filp)285 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
286 {
287 int i, r;
288 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
289 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
290 if (handle != 0 && rdev->uvd.filp[i] == filp) {
291 struct radeon_fence *fence;
292
293 radeon_uvd_note_usage(rdev);
294
295 r = radeon_uvd_get_destroy_msg(rdev,
296 R600_RING_TYPE_UVD_INDEX, handle, &fence);
297 if (r) {
298 DRM_ERROR("Error destroying UVD (%d)!\n", r);
299 continue;
300 }
301
302 radeon_fence_wait(fence, false);
303 radeon_fence_unref(&fence);
304
305 rdev->uvd.filp[i] = NULL;
306 atomic_set(&rdev->uvd.handles[i], 0);
307 }
308 }
309 }
310
radeon_uvd_cs_msg_decode(uint32_t * msg,unsigned buf_sizes[])311 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
312 {
313 unsigned stream_type = msg[4];
314 unsigned width = msg[6];
315 unsigned height = msg[7];
316 unsigned dpb_size = msg[9];
317 unsigned pitch = msg[28];
318
319 unsigned width_in_mb = width / 16;
320 unsigned height_in_mb = ALIGN(height / 16, 2);
321
322 unsigned image_size, tmp, min_dpb_size;
323
324 image_size = width * height;
325 image_size += image_size / 2;
326 image_size = ALIGN(image_size, 1024);
327
328 switch (stream_type) {
329 case 0: /* H264 */
330
331 /* reference picture buffer */
332 min_dpb_size = image_size * 17;
333
334 /* macroblock context buffer */
335 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
336
337 /* IT surface buffer */
338 min_dpb_size += width_in_mb * height_in_mb * 32;
339 break;
340
341 case 1: /* VC1 */
342
343 /* reference picture buffer */
344 min_dpb_size = image_size * 3;
345
346 /* CONTEXT_BUFFER */
347 min_dpb_size += width_in_mb * height_in_mb * 128;
348
349 /* IT surface buffer */
350 min_dpb_size += width_in_mb * 64;
351
352 /* DB surface buffer */
353 min_dpb_size += width_in_mb * 128;
354
355 /* BP */
356 tmp = max(width_in_mb, height_in_mb);
357 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
358 break;
359
360 case 3: /* MPEG2 */
361
362 /* reference picture buffer */
363 min_dpb_size = image_size * 3;
364 break;
365
366 case 4: /* MPEG4 */
367
368 /* reference picture buffer */
369 min_dpb_size = image_size * 3;
370
371 /* CM */
372 min_dpb_size += width_in_mb * height_in_mb * 64;
373
374 /* IT surface buffer */
375 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
376 break;
377
378 default:
379 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
380 return -EINVAL;
381 }
382
383 if (width > pitch) {
384 DRM_ERROR("Invalid UVD decoding target pitch!\n");
385 return -EINVAL;
386 }
387
388 if (dpb_size < min_dpb_size) {
389 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
390 dpb_size, min_dpb_size);
391 return -EINVAL;
392 }
393
394 buf_sizes[0x1] = dpb_size;
395 buf_sizes[0x2] = image_size;
396 return 0;
397 }
398
radeon_uvd_validate_codec(struct radeon_cs_parser * p,unsigned stream_type)399 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
400 unsigned stream_type)
401 {
402 switch (stream_type) {
403 case 0: /* H264 */
404 case 1: /* VC1 */
405 /* always supported */
406 return 0;
407
408 case 3: /* MPEG2 */
409 case 4: /* MPEG4 */
410 /* only since UVD 3 */
411 if (p->rdev->family >= CHIP_PALM)
412 return 0;
413
414 /* fall through */
415 default:
416 DRM_ERROR("UVD codec not supported by hardware %d!\n",
417 stream_type);
418 return -EINVAL;
419 }
420 }
421
radeon_uvd_cs_msg(struct radeon_cs_parser * p,struct radeon_bo * bo,unsigned offset,unsigned buf_sizes[])422 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
423 unsigned offset, unsigned buf_sizes[])
424 {
425 int32_t *msg, msg_type, handle;
426 unsigned img_size = 0;
427 struct fence *f;
428 void *ptr;
429
430 int i, r;
431
432 if (offset & 0x3F) {
433 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
434 return -EINVAL;
435 }
436
437 f = reservation_object_get_excl(bo->tbo.resv);
438 if (f) {
439 r = radeon_fence_wait((struct radeon_fence *)f, false);
440 if (r) {
441 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
442 return r;
443 }
444 }
445
446 r = radeon_bo_kmap(bo, &ptr);
447 if (r) {
448 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
449 return r;
450 }
451
452 msg = ptr + offset;
453
454 msg_type = msg[1];
455 handle = msg[2];
456
457 if (handle == 0) {
458 DRM_ERROR("Invalid UVD handle!\n");
459 return -EINVAL;
460 }
461
462 switch (msg_type) {
463 case 0:
464 /* it's a create msg, calc image size (width * height) */
465 img_size = msg[7] * msg[8];
466
467 r = radeon_uvd_validate_codec(p, msg[4]);
468 radeon_bo_kunmap(bo);
469 if (r)
470 return r;
471
472 /* try to alloc a new handle */
473 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
474 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
475 DRM_ERROR("Handle 0x%x already in use!\n", handle);
476 return -EINVAL;
477 }
478
479 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
480 p->rdev->uvd.filp[i] = p->filp;
481 p->rdev->uvd.img_size[i] = img_size;
482 return 0;
483 }
484 }
485
486 DRM_ERROR("No more free UVD handles!\n");
487 return -EINVAL;
488
489 case 1:
490 /* it's a decode msg, validate codec and calc buffer sizes */
491 r = radeon_uvd_validate_codec(p, msg[4]);
492 if (!r)
493 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
494 radeon_bo_kunmap(bo);
495 if (r)
496 return r;
497
498 /* validate the handle */
499 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
500 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
501 if (p->rdev->uvd.filp[i] != p->filp) {
502 DRM_ERROR("UVD handle collision detected!\n");
503 return -EINVAL;
504 }
505 return 0;
506 }
507 }
508
509 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
510 return -ENOENT;
511
512 case 2:
513 /* it's a destroy msg, free the handle */
514 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
515 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
516 radeon_bo_kunmap(bo);
517 return 0;
518
519 default:
520
521 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
522 return -EINVAL;
523 }
524
525 BUG();
526 return -EINVAL;
527 }
528
radeon_uvd_cs_reloc(struct radeon_cs_parser * p,int data0,int data1,unsigned buf_sizes[],bool * has_msg_cmd)529 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
530 int data0, int data1,
531 unsigned buf_sizes[], bool *has_msg_cmd)
532 {
533 struct radeon_cs_chunk *relocs_chunk;
534 struct radeon_cs_reloc *reloc;
535 unsigned idx, cmd, offset;
536 uint64_t start, end;
537 int r;
538
539 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
540 offset = radeon_get_ib_value(p, data0);
541 idx = radeon_get_ib_value(p, data1);
542 if (idx >= relocs_chunk->length_dw) {
543 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
544 idx, relocs_chunk->length_dw);
545 return -EINVAL;
546 }
547
548 reloc = p->relocs_ptr[(idx / 4)];
549 start = reloc->gpu_offset;
550 end = start + radeon_bo_size(reloc->robj);
551 start += offset;
552
553 p->ib.ptr[data0] = start & 0xFFFFFFFF;
554 p->ib.ptr[data1] = start >> 32;
555
556 cmd = radeon_get_ib_value(p, p->idx) >> 1;
557
558 if (cmd < 0x4) {
559 if (end <= start) {
560 DRM_ERROR("invalid reloc offset %X!\n", offset);
561 return -EINVAL;
562 }
563 if ((end - start) < buf_sizes[cmd]) {
564 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
565 (unsigned)(end - start), buf_sizes[cmd]);
566 return -EINVAL;
567 }
568
569 } else if (cmd != 0x100) {
570 DRM_ERROR("invalid UVD command %X!\n", cmd);
571 return -EINVAL;
572 }
573
574 if ((start >> 28) != ((end - 1) >> 28)) {
575 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
576 start, end);
577 return -EINVAL;
578 }
579
580 /* TODO: is this still necessary on NI+ ? */
581 if ((cmd == 0 || cmd == 0x3) &&
582 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
583 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
584 start, end);
585 return -EINVAL;
586 }
587
588 if (cmd == 0) {
589 if (*has_msg_cmd) {
590 DRM_ERROR("More than one message in a UVD-IB!\n");
591 return -EINVAL;
592 }
593 *has_msg_cmd = true;
594 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
595 if (r)
596 return r;
597 } else if (!*has_msg_cmd) {
598 DRM_ERROR("Message needed before other commands are send!\n");
599 return -EINVAL;
600 }
601
602 return 0;
603 }
604
radeon_uvd_cs_reg(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,int * data0,int * data1,unsigned buf_sizes[],bool * has_msg_cmd)605 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
606 struct radeon_cs_packet *pkt,
607 int *data0, int *data1,
608 unsigned buf_sizes[],
609 bool *has_msg_cmd)
610 {
611 int i, r;
612
613 p->idx++;
614 for (i = 0; i <= pkt->count; ++i) {
615 switch (pkt->reg + i*4) {
616 case UVD_GPCOM_VCPU_DATA0:
617 *data0 = p->idx;
618 break;
619 case UVD_GPCOM_VCPU_DATA1:
620 *data1 = p->idx;
621 break;
622 case UVD_GPCOM_VCPU_CMD:
623 r = radeon_uvd_cs_reloc(p, *data0, *data1,
624 buf_sizes, has_msg_cmd);
625 if (r)
626 return r;
627 break;
628 case UVD_ENGINE_CNTL:
629 break;
630 default:
631 DRM_ERROR("Invalid reg 0x%X!\n",
632 pkt->reg + i*4);
633 return -EINVAL;
634 }
635 p->idx++;
636 }
637 return 0;
638 }
639
radeon_uvd_cs_parse(struct radeon_cs_parser * p)640 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
641 {
642 struct radeon_cs_packet pkt;
643 int r, data0 = 0, data1 = 0;
644
645 /* does the IB has a msg command */
646 bool has_msg_cmd = false;
647
648 /* minimum buffer sizes */
649 unsigned buf_sizes[] = {
650 [0x00000000] = 2048,
651 [0x00000001] = 32 * 1024 * 1024,
652 [0x00000002] = 2048 * 1152 * 3,
653 [0x00000003] = 2048,
654 };
655
656 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
657 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
658 p->chunks[p->chunk_ib_idx].length_dw);
659 return -EINVAL;
660 }
661
662 if (p->chunk_relocs_idx == -1) {
663 DRM_ERROR("No relocation chunk !\n");
664 return -EINVAL;
665 }
666
667
668 do {
669 r = radeon_cs_packet_parse(p, &pkt, p->idx);
670 if (r)
671 return r;
672 switch (pkt.type) {
673 case RADEON_PACKET_TYPE0:
674 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
675 buf_sizes, &has_msg_cmd);
676 if (r)
677 return r;
678 break;
679 case RADEON_PACKET_TYPE2:
680 p->idx += pkt.count + 2;
681 break;
682 default:
683 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
684 return -EINVAL;
685 }
686 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
687
688 if (!has_msg_cmd) {
689 DRM_ERROR("UVD-IBs need a msg command!\n");
690 return -EINVAL;
691 }
692
693 return 0;
694 }
695
radeon_uvd_send_msg(struct radeon_device * rdev,int ring,uint64_t addr,struct radeon_fence ** fence)696 static int radeon_uvd_send_msg(struct radeon_device *rdev,
697 int ring, uint64_t addr,
698 struct radeon_fence **fence)
699 {
700 struct radeon_ib ib;
701 int i, r;
702
703 r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
704 if (r)
705 return r;
706
707 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
708 ib.ptr[1] = addr;
709 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
710 ib.ptr[3] = addr >> 32;
711 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
712 ib.ptr[5] = 0;
713 for (i = 6; i < 16; ++i)
714 ib.ptr[i] = PACKET2(0);
715 ib.length_dw = 16;
716
717 r = radeon_ib_schedule(rdev, &ib, NULL, false);
718
719 if (fence)
720 *fence = radeon_fence_ref(ib.fence);
721
722 radeon_ib_free(rdev, &ib);
723 return r;
724 }
725
726 /* multiple fence commands without any stream commands in between can
727 crash the vcpu so just try to emmit a dummy create/destroy msg to
728 avoid this */
radeon_uvd_get_create_msg(struct radeon_device * rdev,int ring,uint32_t handle,struct radeon_fence ** fence)729 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
730 uint32_t handle, struct radeon_fence **fence)
731 {
732 /* we use the last page of the vcpu bo for the UVD message */
733 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
734 RADEON_GPU_PAGE_SIZE;
735
736 uint32_t *msg = rdev->uvd.cpu_addr + offs;
737 uint64_t addr = rdev->uvd.gpu_addr + offs;
738
739 int r, i;
740
741 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
742 if (r)
743 return r;
744
745 /* stitch together an UVD create msg */
746 msg[0] = cpu_to_le32(0x00000de4);
747 msg[1] = cpu_to_le32(0x00000000);
748 msg[2] = cpu_to_le32(handle);
749 msg[3] = cpu_to_le32(0x00000000);
750 msg[4] = cpu_to_le32(0x00000000);
751 msg[5] = cpu_to_le32(0x00000000);
752 msg[6] = cpu_to_le32(0x00000000);
753 msg[7] = cpu_to_le32(0x00000780);
754 msg[8] = cpu_to_le32(0x00000440);
755 msg[9] = cpu_to_le32(0x00000000);
756 msg[10] = cpu_to_le32(0x01b37000);
757 for (i = 11; i < 1024; ++i)
758 msg[i] = cpu_to_le32(0x0);
759
760 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
761 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
762 return r;
763 }
764
radeon_uvd_get_destroy_msg(struct radeon_device * rdev,int ring,uint32_t handle,struct radeon_fence ** fence)765 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
766 uint32_t handle, struct radeon_fence **fence)
767 {
768 /* we use the last page of the vcpu bo for the UVD message */
769 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
770 RADEON_GPU_PAGE_SIZE;
771
772 uint32_t *msg = rdev->uvd.cpu_addr + offs;
773 uint64_t addr = rdev->uvd.gpu_addr + offs;
774
775 int r, i;
776
777 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
778 if (r)
779 return r;
780
781 /* stitch together an UVD destroy msg */
782 msg[0] = cpu_to_le32(0x00000de4);
783 msg[1] = cpu_to_le32(0x00000002);
784 msg[2] = cpu_to_le32(handle);
785 msg[3] = cpu_to_le32(0x00000000);
786 for (i = 4; i < 1024; ++i)
787 msg[i] = cpu_to_le32(0x0);
788
789 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
790 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
791 return r;
792 }
793
794 /**
795 * radeon_uvd_count_handles - count number of open streams
796 *
797 * @rdev: radeon_device pointer
798 * @sd: number of SD streams
799 * @hd: number of HD streams
800 *
801 * Count the number of open SD/HD streams as a hint for power mangement
802 */
radeon_uvd_count_handles(struct radeon_device * rdev,unsigned * sd,unsigned * hd)803 static void radeon_uvd_count_handles(struct radeon_device *rdev,
804 unsigned *sd, unsigned *hd)
805 {
806 unsigned i;
807
808 *sd = 0;
809 *hd = 0;
810
811 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
812 if (!atomic_read(&rdev->uvd.handles[i]))
813 continue;
814
815 if (rdev->uvd.img_size[i] >= 720*576)
816 ++(*hd);
817 else
818 ++(*sd);
819 }
820 }
821
radeon_uvd_idle_work_handler(struct work_struct * work)822 static void radeon_uvd_idle_work_handler(struct work_struct *work)
823 {
824 struct radeon_device *rdev =
825 container_of(work, struct radeon_device, uvd.idle_work.work);
826
827 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
828 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
829 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
830 &rdev->pm.dpm.hd);
831 radeon_dpm_enable_uvd(rdev, false);
832 } else {
833 radeon_set_uvd_clocks(rdev, 0, 0);
834 }
835 } else {
836 schedule_delayed_work(&rdev->uvd.idle_work,
837 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
838 }
839 }
840
radeon_uvd_note_usage(struct radeon_device * rdev)841 void radeon_uvd_note_usage(struct radeon_device *rdev)
842 {
843 bool streams_changed = false;
844 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
845 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
846 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
847
848 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
849 unsigned hd = 0, sd = 0;
850 radeon_uvd_count_handles(rdev, &sd, &hd);
851 if ((rdev->pm.dpm.sd != sd) ||
852 (rdev->pm.dpm.hd != hd)) {
853 rdev->pm.dpm.sd = sd;
854 rdev->pm.dpm.hd = hd;
855 /* disable this for now */
856 /*streams_changed = true;*/
857 }
858 }
859
860 if (set_clocks || streams_changed) {
861 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
862 radeon_dpm_enable_uvd(rdev, true);
863 } else {
864 radeon_set_uvd_clocks(rdev, 53300, 40000);
865 }
866 }
867 }
868
radeon_uvd_calc_upll_post_div(unsigned vco_freq,unsigned target_freq,unsigned pd_min,unsigned pd_even)869 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
870 unsigned target_freq,
871 unsigned pd_min,
872 unsigned pd_even)
873 {
874 unsigned post_div = vco_freq / target_freq;
875
876 /* adjust to post divider minimum value */
877 if (post_div < pd_min)
878 post_div = pd_min;
879
880 /* we alway need a frequency less than or equal the target */
881 if ((vco_freq / post_div) > target_freq)
882 post_div += 1;
883
884 /* post dividers above a certain value must be even */
885 if (post_div > pd_even && post_div % 2)
886 post_div += 1;
887
888 return post_div;
889 }
890
891 /**
892 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
893 *
894 * @rdev: radeon_device pointer
895 * @vclk: wanted VCLK
896 * @dclk: wanted DCLK
897 * @vco_min: minimum VCO frequency
898 * @vco_max: maximum VCO frequency
899 * @fb_factor: factor to multiply vco freq with
900 * @fb_mask: limit and bitmask for feedback divider
901 * @pd_min: post divider minimum
902 * @pd_max: post divider maximum
903 * @pd_even: post divider must be even above this value
904 * @optimal_fb_div: resulting feedback divider
905 * @optimal_vclk_div: resulting vclk post divider
906 * @optimal_dclk_div: resulting dclk post divider
907 *
908 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
909 * Returns zero on success -EINVAL on error.
910 */
radeon_uvd_calc_upll_dividers(struct radeon_device * rdev,unsigned vclk,unsigned dclk,unsigned vco_min,unsigned vco_max,unsigned fb_factor,unsigned fb_mask,unsigned pd_min,unsigned pd_max,unsigned pd_even,unsigned * optimal_fb_div,unsigned * optimal_vclk_div,unsigned * optimal_dclk_div)911 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
912 unsigned vclk, unsigned dclk,
913 unsigned vco_min, unsigned vco_max,
914 unsigned fb_factor, unsigned fb_mask,
915 unsigned pd_min, unsigned pd_max,
916 unsigned pd_even,
917 unsigned *optimal_fb_div,
918 unsigned *optimal_vclk_div,
919 unsigned *optimal_dclk_div)
920 {
921 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
922
923 /* start off with something large */
924 unsigned optimal_score = ~0;
925
926 /* loop through vco from low to high */
927 vco_min = max(max(vco_min, vclk), dclk);
928 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
929
930 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
931 unsigned vclk_div, dclk_div, score;
932
933 do_div(fb_div, ref_freq);
934
935 /* fb div out of range ? */
936 if (fb_div > fb_mask)
937 break; /* it can oly get worse */
938
939 fb_div &= fb_mask;
940
941 /* calc vclk divider with current vco freq */
942 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
943 pd_min, pd_even);
944 if (vclk_div > pd_max)
945 break; /* vco is too big, it has to stop */
946
947 /* calc dclk divider with current vco freq */
948 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
949 pd_min, pd_even);
950 if (vclk_div > pd_max)
951 break; /* vco is too big, it has to stop */
952
953 /* calc score with current vco freq */
954 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
955
956 /* determine if this vco setting is better than current optimal settings */
957 if (score < optimal_score) {
958 *optimal_fb_div = fb_div;
959 *optimal_vclk_div = vclk_div;
960 *optimal_dclk_div = dclk_div;
961 optimal_score = score;
962 if (optimal_score == 0)
963 break; /* it can't get better than this */
964 }
965 }
966
967 /* did we found a valid setup ? */
968 if (optimal_score == ~0)
969 return -EINVAL;
970
971 return 0;
972 }
973
radeon_uvd_send_upll_ctlreq(struct radeon_device * rdev,unsigned cg_upll_func_cntl)974 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
975 unsigned cg_upll_func_cntl)
976 {
977 unsigned i;
978
979 /* make sure UPLL_CTLREQ is deasserted */
980 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
981
982 mdelay(10);
983
984 /* assert UPLL_CTLREQ */
985 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
986
987 /* wait for CTLACK and CTLACK2 to get asserted */
988 for (i = 0; i < 100; ++i) {
989 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
990 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
991 break;
992 mdelay(10);
993 }
994
995 /* deassert UPLL_CTLREQ */
996 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
997
998 if (i == 100) {
999 DRM_ERROR("Timeout setting UVD clocks!\n");
1000 return -ETIMEDOUT;
1001 }
1002
1003 return 0;
1004 }
1005