1 /*
2 * arch/arm/plat-orion/time.c
3 *
4 * Marvell Orion SoC timer handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * Timer 0 is used as free-running clocksource, while timer 1 is
11 * used as clock_event_device.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/clockchips.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/sched_clock.h>
20 #include <plat/time.h>
21
22 /*
23 * MBus bridge block registers.
24 */
25 #define BRIDGE_CAUSE_OFF 0x0110
26 #define BRIDGE_MASK_OFF 0x0114
27 #define BRIDGE_INT_TIMER0 0x0002
28 #define BRIDGE_INT_TIMER1 0x0004
29
30
31 /*
32 * Timer block registers.
33 */
34 #define TIMER_CTRL_OFF 0x0000
35 #define TIMER0_EN 0x0001
36 #define TIMER0_RELOAD_EN 0x0002
37 #define TIMER1_EN 0x0004
38 #define TIMER1_RELOAD_EN 0x0008
39 #define TIMER0_RELOAD_OFF 0x0010
40 #define TIMER0_VAL_OFF 0x0014
41 #define TIMER1_RELOAD_OFF 0x0018
42 #define TIMER1_VAL_OFF 0x001c
43
44
45 /*
46 * SoC-specific data.
47 */
48 static void __iomem *bridge_base;
49 static u32 bridge_timer1_clr_mask;
50 static void __iomem *timer_base;
51
52
53 /*
54 * Number of timer ticks per jiffy.
55 */
56 static u32 ticks_per_jiffy;
57
58
59 /*
60 * Orion's sched_clock implementation. It has a resolution of
61 * at least 7.5ns (133MHz TCLK).
62 */
63
orion_read_sched_clock(void)64 static u64 notrace orion_read_sched_clock(void)
65 {
66 return ~readl(timer_base + TIMER0_VAL_OFF);
67 }
68
69 /*
70 * Clockevent handling.
71 */
72 static int
orion_clkevt_next_event(unsigned long delta,struct clock_event_device * dev)73 orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
74 {
75 unsigned long flags;
76 u32 u;
77
78 if (delta == 0)
79 return -ETIME;
80
81 local_irq_save(flags);
82
83 /*
84 * Clear and enable clockevent timer interrupt.
85 */
86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
87
88 u = readl(bridge_base + BRIDGE_MASK_OFF);
89 u |= BRIDGE_INT_TIMER1;
90 writel(u, bridge_base + BRIDGE_MASK_OFF);
91
92 /*
93 * Setup new clockevent timer value.
94 */
95 writel(delta, timer_base + TIMER1_VAL_OFF);
96
97 /*
98 * Enable the timer.
99 */
100 u = readl(timer_base + TIMER_CTRL_OFF);
101 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
102 writel(u, timer_base + TIMER_CTRL_OFF);
103
104 local_irq_restore(flags);
105
106 return 0;
107 }
108
109 static void
orion_clkevt_mode(enum clock_event_mode mode,struct clock_event_device * dev)110 orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
111 {
112 unsigned long flags;
113 u32 u;
114
115 local_irq_save(flags);
116 if (mode == CLOCK_EVT_MODE_PERIODIC) {
117 /*
118 * Setup timer to fire at 1/HZ intervals.
119 */
120 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
121 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
122
123 /*
124 * Enable timer interrupt.
125 */
126 u = readl(bridge_base + BRIDGE_MASK_OFF);
127 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
128
129 /*
130 * Enable timer.
131 */
132 u = readl(timer_base + TIMER_CTRL_OFF);
133 writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
134 timer_base + TIMER_CTRL_OFF);
135 } else {
136 /*
137 * Disable timer.
138 */
139 u = readl(timer_base + TIMER_CTRL_OFF);
140 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
141
142 /*
143 * Disable timer interrupt.
144 */
145 u = readl(bridge_base + BRIDGE_MASK_OFF);
146 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
147
148 /*
149 * ACK pending timer interrupt.
150 */
151 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
152
153 }
154 local_irq_restore(flags);
155 }
156
157 static struct clock_event_device orion_clkevt = {
158 .name = "orion_tick",
159 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
160 .rating = 300,
161 .set_next_event = orion_clkevt_next_event,
162 .set_mode = orion_clkevt_mode,
163 };
164
orion_timer_interrupt(int irq,void * dev_id)165 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
166 {
167 /*
168 * ACK timer interrupt and call event handler.
169 */
170 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
171 orion_clkevt.event_handler(&orion_clkevt);
172
173 return IRQ_HANDLED;
174 }
175
176 static struct irqaction orion_timer_irq = {
177 .name = "orion_tick",
178 .flags = IRQF_TIMER,
179 .handler = orion_timer_interrupt
180 };
181
182 void __init
orion_time_set_base(void __iomem * _timer_base)183 orion_time_set_base(void __iomem *_timer_base)
184 {
185 timer_base = _timer_base;
186 }
187
188 void __init
orion_time_init(void __iomem * _bridge_base,u32 _bridge_timer1_clr_mask,unsigned int irq,unsigned int tclk)189 orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
190 unsigned int irq, unsigned int tclk)
191 {
192 u32 u;
193
194 /*
195 * Set SoC-specific data.
196 */
197 bridge_base = _bridge_base;
198 bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
199
200 ticks_per_jiffy = (tclk + HZ/2) / HZ;
201
202 /*
203 * Set scale and timer for sched_clock.
204 */
205 sched_clock_register(orion_read_sched_clock, 32, tclk);
206
207 /*
208 * Setup free-running clocksource timer (interrupts
209 * disabled).
210 */
211 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
212 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
213 u = readl(bridge_base + BRIDGE_MASK_OFF);
214 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
215 u = readl(timer_base + TIMER_CTRL_OFF);
216 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
217 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
218 tclk, 300, 32, clocksource_mmio_readl_down);
219
220 /*
221 * Setup clockevent timer (interrupt-driven).
222 */
223 setup_irq(irq, &orion_timer_irq);
224 orion_clkevt.cpumask = cpumask_of(0);
225 clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
226 }
227