1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14960 bytes, from 2014-07-27 17:22:13)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-08-01 12:22:48)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 41068 bytes, from 2014-08-01 12:22:48)
18
19 Copyright (C) 2013-2014 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
21
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
29
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
33
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43
44 enum vgt_event_type {
45 VS_DEALLOC = 0,
46 PS_DEALLOC = 1,
47 VS_DONE_TS = 2,
48 PS_DONE_TS = 3,
49 CACHE_FLUSH_TS = 4,
50 CONTEXT_DONE = 5,
51 CACHE_FLUSH = 6,
52 HLSQ_FLUSH = 7,
53 VIZQUERY_START = 7,
54 VIZQUERY_END = 8,
55 SC_WAIT_WC = 9,
56 RST_PIX_CNT = 13,
57 RST_VTX_CNT = 14,
58 TILE_FLUSH = 15,
59 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
60 ZPASS_DONE = 21,
61 CACHE_FLUSH_AND_INV_EVENT = 22,
62 PERFCOUNTER_START = 23,
63 PERFCOUNTER_STOP = 24,
64 VS_FETCH_DONE = 27,
65 FACENESS_FLUSH = 28,
66 };
67
68 enum pc_di_primtype {
69 DI_PT_NONE = 0,
70 DI_PT_POINTLIST_A2XX = 1,
71 DI_PT_LINELIST = 2,
72 DI_PT_LINESTRIP = 3,
73 DI_PT_TRILIST = 4,
74 DI_PT_TRIFAN = 5,
75 DI_PT_TRISTRIP = 6,
76 DI_PT_LINELOOP = 7,
77 DI_PT_RECTLIST = 8,
78 DI_PT_POINTLIST_A3XX = 9,
79 DI_PT_QUADLIST = 13,
80 DI_PT_QUADSTRIP = 14,
81 DI_PT_POLYGON = 15,
82 DI_PT_2D_COPY_RECT_LIST_V0 = 16,
83 DI_PT_2D_COPY_RECT_LIST_V1 = 17,
84 DI_PT_2D_COPY_RECT_LIST_V2 = 18,
85 DI_PT_2D_COPY_RECT_LIST_V3 = 19,
86 DI_PT_2D_FILL_RECT_LIST = 20,
87 DI_PT_2D_LINE_STRIP = 21,
88 DI_PT_2D_TRI_STRIP = 22,
89 };
90
91 enum pc_di_src_sel {
92 DI_SRC_SEL_DMA = 0,
93 DI_SRC_SEL_IMMEDIATE = 1,
94 DI_SRC_SEL_AUTO_INDEX = 2,
95 DI_SRC_SEL_RESERVED = 3,
96 };
97
98 enum pc_di_index_size {
99 INDEX_SIZE_IGN = 0,
100 INDEX_SIZE_16_BIT = 0,
101 INDEX_SIZE_32_BIT = 1,
102 INDEX_SIZE_8_BIT = 2,
103 INDEX_SIZE_INVALID = 0,
104 };
105
106 enum pc_di_vis_cull_mode {
107 IGNORE_VISIBILITY = 0,
108 USE_VISIBILITY = 1,
109 };
110
111 enum adreno_pm4_packet_type {
112 CP_TYPE0_PKT = 0,
113 CP_TYPE1_PKT = 0x40000000,
114 CP_TYPE2_PKT = 0x80000000,
115 CP_TYPE3_PKT = 0xc0000000,
116 };
117
118 enum adreno_pm4_type3_packets {
119 CP_ME_INIT = 72,
120 CP_NOP = 16,
121 CP_INDIRECT_BUFFER = 63,
122 CP_INDIRECT_BUFFER_PFD = 55,
123 CP_WAIT_FOR_IDLE = 38,
124 CP_WAIT_REG_MEM = 60,
125 CP_WAIT_REG_EQ = 82,
126 CP_WAIT_REG_GTE = 83,
127 CP_WAIT_UNTIL_READ = 92,
128 CP_WAIT_IB_PFD_COMPLETE = 93,
129 CP_REG_RMW = 33,
130 CP_SET_BIN_DATA = 47,
131 CP_REG_TO_MEM = 62,
132 CP_MEM_WRITE = 61,
133 CP_MEM_WRITE_CNTR = 79,
134 CP_COND_EXEC = 68,
135 CP_COND_WRITE = 69,
136 CP_EVENT_WRITE = 70,
137 CP_EVENT_WRITE_SHD = 88,
138 CP_EVENT_WRITE_CFL = 89,
139 CP_EVENT_WRITE_ZPD = 91,
140 CP_RUN_OPENCL = 49,
141 CP_DRAW_INDX = 34,
142 CP_DRAW_INDX_2 = 54,
143 CP_DRAW_INDX_BIN = 52,
144 CP_DRAW_INDX_2_BIN = 53,
145 CP_VIZ_QUERY = 35,
146 CP_SET_STATE = 37,
147 CP_SET_CONSTANT = 45,
148 CP_IM_LOAD = 39,
149 CP_IM_LOAD_IMMEDIATE = 43,
150 CP_LOAD_CONSTANT_CONTEXT = 46,
151 CP_INVALIDATE_STATE = 59,
152 CP_SET_SHADER_BASES = 74,
153 CP_SET_BIN_MASK = 80,
154 CP_SET_BIN_SELECT = 81,
155 CP_CONTEXT_UPDATE = 94,
156 CP_INTERRUPT = 64,
157 CP_IM_STORE = 44,
158 CP_SET_DRAW_INIT_FLAGS = 75,
159 CP_SET_PROTECTED_MODE = 95,
160 CP_LOAD_STATE = 48,
161 CP_COND_INDIRECT_BUFFER_PFE = 58,
162 CP_COND_INDIRECT_BUFFER_PFD = 50,
163 CP_INDIRECT_BUFFER_PFE = 63,
164 CP_SET_BIN = 76,
165 CP_TEST_TWO_MEMS = 113,
166 CP_REG_WR_NO_CTXT = 120,
167 CP_RECORD_PFP_TIMESTAMP = 17,
168 CP_WAIT_FOR_ME = 19,
169 CP_SET_DRAW_STATE = 67,
170 CP_DRAW_INDX_OFFSET = 56,
171 CP_DRAW_INDIRECT = 40,
172 CP_DRAW_INDX_INDIRECT = 41,
173 CP_DRAW_AUTO = 36,
174 CP_UNKNOWN_1A = 26,
175 CP_WIDE_REG_WRITE = 116,
176 IN_IB_PREFETCH_END = 23,
177 IN_SUBBLK_PREFETCH = 31,
178 IN_INSTR_PREFETCH = 32,
179 IN_INSTR_MATCH = 71,
180 IN_CONST_PREFETCH = 73,
181 IN_INCR_UPDT_STATE = 85,
182 IN_INCR_UPDT_CONST = 86,
183 IN_INCR_UPDT_INSTR = 87,
184 };
185
186 enum adreno_state_block {
187 SB_VERT_TEX = 0,
188 SB_VERT_MIPADDR = 1,
189 SB_FRAG_TEX = 2,
190 SB_FRAG_MIPADDR = 3,
191 SB_VERT_SHADER = 4,
192 SB_FRAG_SHADER = 6,
193 };
194
195 enum adreno_state_type {
196 ST_SHADER = 0,
197 ST_CONSTANTS = 1,
198 };
199
200 enum adreno_state_src {
201 SS_DIRECT = 0,
202 SS_INDIRECT = 4,
203 };
204
205 #define REG_CP_LOAD_STATE_0 0x00000000
206 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
207 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
CP_LOAD_STATE_0_DST_OFF(uint32_t val)208 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
209 {
210 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
211 }
212 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
213 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)214 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
215 {
216 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
217 }
218 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
219 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)220 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
221 {
222 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
223 }
224 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000
225 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)226 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
227 {
228 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
229 }
230
231 #define REG_CP_LOAD_STATE_1 0x00000001
232 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
233 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)234 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
235 {
236 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
237 }
238 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
239 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)240 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
241 {
242 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
243 }
244
245 #define REG_CP_DRAW_INDX_0 0x00000000
246 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
247 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)248 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
249 {
250 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
251 }
252
253 #define REG_CP_DRAW_INDX_1 0x00000001
254 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
255 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)256 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
257 {
258 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
259 }
260 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
261 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)262 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
263 {
264 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
265 }
266 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
267 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)268 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
269 {
270 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
271 }
272 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
273 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)274 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
275 {
276 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
277 }
278 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
279 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
280 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
281 #define CP_DRAW_INDX_1_NUM_INDICES__MASK 0xffff0000
282 #define CP_DRAW_INDX_1_NUM_INDICES__SHIFT 16
CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)283 static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
284 {
285 return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
286 }
287
288 #define REG_CP_DRAW_INDX_2 0x00000002
289 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
290 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)291 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
292 {
293 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
294 }
295
296 #define REG_CP_DRAW_INDX_2 0x00000002
297 #define CP_DRAW_INDX_2_INDX_BASE__MASK 0xffffffff
298 #define CP_DRAW_INDX_2_INDX_BASE__SHIFT 0
CP_DRAW_INDX_2_INDX_BASE(uint32_t val)299 static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
300 {
301 return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
302 }
303
304 #define REG_CP_DRAW_INDX_2 0x00000002
305 #define CP_DRAW_INDX_2_INDX_SIZE__MASK 0xffffffff
306 #define CP_DRAW_INDX_2_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)307 static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
308 {
309 return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
310 }
311
312 #define REG_CP_DRAW_INDX_2_0 0x00000000
313 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
314 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)315 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
316 {
317 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
318 }
319
320 #define REG_CP_DRAW_INDX_2_1 0x00000001
321 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
322 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)323 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
324 {
325 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
326 }
327 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
328 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)329 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
330 {
331 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
332 }
333 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
334 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)335 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
336 {
337 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
338 }
339 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
340 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)341 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
342 {
343 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
344 }
345 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
346 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
347 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
348 #define CP_DRAW_INDX_2_1_NUM_INDICES__MASK 0xffff0000
349 #define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT 16
CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)350 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
351 {
352 return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
353 }
354
355 #define REG_CP_DRAW_INDX_2_2 0x00000002
356 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
357 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)358 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
359 {
360 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
361 }
362
363 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
364 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
365 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)366 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
367 {
368 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
369 }
370 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
371 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)372 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
373 {
374 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
375 }
376 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700
377 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)378 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
379 {
380 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
381 }
382 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800
383 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)384 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
385 {
386 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
387 }
388 #define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000
389 #define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000
390 #define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000
391 #define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK 0xffff0000
392 #define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT 16
CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)393 static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
394 {
395 return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
396 }
397
398 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
399
400 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
401 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
402 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)403 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
404 {
405 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
406 }
407
408 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
409 #define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK 0xffffffff
410 #define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT 0
CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)411 static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
412 {
413 return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
414 }
415
416 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
417 #define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK 0xffffffff
418 #define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)419 static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
420 {
421 return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
422 }
423
424 #define REG_CP_SET_DRAW_STATE_0 0x00000000
425 #define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff
426 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0
CP_SET_DRAW_STATE_0_COUNT(uint32_t val)427 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
428 {
429 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
430 }
431 #define CP_SET_DRAW_STATE_0_DIRTY 0x00010000
432 #define CP_SET_DRAW_STATE_0_DISABLE 0x00020000
433 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000
434 #define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000
435 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000
436 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24
CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)437 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
438 {
439 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
440 }
441
442 #define REG_CP_SET_DRAW_STATE_1 0x00000001
443 #define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff
444 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0
CP_SET_DRAW_STATE_1_ADDR(uint32_t val)445 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
446 {
447 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
448 }
449
450 #define REG_CP_SET_BIN_0 0x00000000
451
452 #define REG_CP_SET_BIN_1 0x00000001
453 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
454 #define CP_SET_BIN_1_X1__SHIFT 0
CP_SET_BIN_1_X1(uint32_t val)455 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
456 {
457 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
458 }
459 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
460 #define CP_SET_BIN_1_Y1__SHIFT 16
CP_SET_BIN_1_Y1(uint32_t val)461 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
462 {
463 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
464 }
465
466 #define REG_CP_SET_BIN_2 0x00000002
467 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
468 #define CP_SET_BIN_2_X2__SHIFT 0
CP_SET_BIN_2_X2(uint32_t val)469 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
470 {
471 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
472 }
473 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
474 #define CP_SET_BIN_2_Y2__SHIFT 16
CP_SET_BIN_2_Y2(uint32_t val)475 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
476 {
477 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
478 }
479
480 #define REG_CP_SET_BIN_DATA_0 0x00000000
481 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
482 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)483 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
484 {
485 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
486 }
487
488 #define REG_CP_SET_BIN_DATA_1 0x00000001
489 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
490 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)491 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
492 {
493 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
494 }
495
496
497 #endif /* ADRENO_PM4_XML */
498