1 #include <linux/delay.h>
2 #include <linux/pci.h>
3 #include <linux/module.h>
4 #include <linux/sched.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
8
9 #include "pci.h"
10
11 /*
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
14 */
15
16 DEFINE_RAW_SPINLOCK(pci_lock);
17
18 /*
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
21 * by pci_dev->ops.
22 */
23
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
27
28 #define PCI_OP_READ(size,type,len) \
29 int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
31 { \
32 int res; \
33 unsigned long flags; \
34 u32 data = 0; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
40 return res; \
41 }
42
43 #define PCI_OP_WRITE(size,type,len) \
44 int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
46 { \
47 int res; \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
53 return res; \
54 }
55
56 PCI_OP_READ(byte, u8, 1)
57 PCI_OP_READ(word, u16, 2)
58 PCI_OP_READ(dword, u32, 4)
59 PCI_OP_WRITE(byte, u8, 1)
60 PCI_OP_WRITE(word, u16, 2)
61 PCI_OP_WRITE(dword, u32, 4)
62
63 EXPORT_SYMBOL(pci_bus_read_config_byte);
64 EXPORT_SYMBOL(pci_bus_read_config_word);
65 EXPORT_SYMBOL(pci_bus_read_config_dword);
66 EXPORT_SYMBOL(pci_bus_write_config_byte);
67 EXPORT_SYMBOL(pci_bus_write_config_word);
68 EXPORT_SYMBOL(pci_bus_write_config_dword);
69
70 /**
71 * pci_bus_set_ops - Set raw operations of pci bus
72 * @bus: pci bus struct
73 * @ops: new raw operations
74 *
75 * Return previous raw operations
76 */
pci_bus_set_ops(struct pci_bus * bus,struct pci_ops * ops)77 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
78 {
79 struct pci_ops *old_ops;
80 unsigned long flags;
81
82 raw_spin_lock_irqsave(&pci_lock, flags);
83 old_ops = bus->ops;
84 bus->ops = ops;
85 raw_spin_unlock_irqrestore(&pci_lock, flags);
86 return old_ops;
87 }
88 EXPORT_SYMBOL(pci_bus_set_ops);
89
90 /**
91 * pci_read_vpd - Read one entry from Vital Product Data
92 * @dev: pci device struct
93 * @pos: offset in vpd space
94 * @count: number of bytes to read
95 * @buf: pointer to where to store result
96 *
97 */
pci_read_vpd(struct pci_dev * dev,loff_t pos,size_t count,void * buf)98 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
99 {
100 if (!dev->vpd || !dev->vpd->ops)
101 return -ENODEV;
102 return dev->vpd->ops->read(dev, pos, count, buf);
103 }
104 EXPORT_SYMBOL(pci_read_vpd);
105
106 /**
107 * pci_write_vpd - Write entry to Vital Product Data
108 * @dev: pci device struct
109 * @pos: offset in vpd space
110 * @count: number of bytes to write
111 * @buf: buffer containing write data
112 *
113 */
pci_write_vpd(struct pci_dev * dev,loff_t pos,size_t count,const void * buf)114 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
115 {
116 if (!dev->vpd || !dev->vpd->ops)
117 return -ENODEV;
118 return dev->vpd->ops->write(dev, pos, count, buf);
119 }
120 EXPORT_SYMBOL(pci_write_vpd);
121
122 /*
123 * The following routines are to prevent the user from accessing PCI config
124 * space when it's unsafe to do so. Some devices require this during BIST and
125 * we're required to prevent it during D-state transitions.
126 *
127 * We have a bit per device to indicate it's blocked and a global wait queue
128 * for callers to sleep on until devices are unblocked.
129 */
130 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
131
pci_wait_cfg(struct pci_dev * dev)132 static noinline void pci_wait_cfg(struct pci_dev *dev)
133 {
134 DECLARE_WAITQUEUE(wait, current);
135
136 __add_wait_queue(&pci_cfg_wait, &wait);
137 do {
138 set_current_state(TASK_UNINTERRUPTIBLE);
139 raw_spin_unlock_irq(&pci_lock);
140 schedule();
141 raw_spin_lock_irq(&pci_lock);
142 } while (dev->block_cfg_access);
143 __remove_wait_queue(&pci_cfg_wait, &wait);
144 }
145
146 /* Returns 0 on success, negative values indicate error. */
147 #define PCI_USER_READ_CONFIG(size,type) \
148 int pci_user_read_config_##size \
149 (struct pci_dev *dev, int pos, type *val) \
150 { \
151 int ret = PCIBIOS_SUCCESSFUL; \
152 u32 data = -1; \
153 if (PCI_##size##_BAD) \
154 return -EINVAL; \
155 raw_spin_lock_irq(&pci_lock); \
156 if (unlikely(dev->block_cfg_access)) \
157 pci_wait_cfg(dev); \
158 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
159 pos, sizeof(type), &data); \
160 raw_spin_unlock_irq(&pci_lock); \
161 *val = (type)data; \
162 return pcibios_err_to_errno(ret); \
163 } \
164 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
165
166 /* Returns 0 on success, negative values indicate error. */
167 #define PCI_USER_WRITE_CONFIG(size,type) \
168 int pci_user_write_config_##size \
169 (struct pci_dev *dev, int pos, type val) \
170 { \
171 int ret = PCIBIOS_SUCCESSFUL; \
172 if (PCI_##size##_BAD) \
173 return -EINVAL; \
174 raw_spin_lock_irq(&pci_lock); \
175 if (unlikely(dev->block_cfg_access)) \
176 pci_wait_cfg(dev); \
177 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
178 pos, sizeof(type), val); \
179 raw_spin_unlock_irq(&pci_lock); \
180 return pcibios_err_to_errno(ret); \
181 } \
182 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
183
184 PCI_USER_READ_CONFIG(byte, u8)
185 PCI_USER_READ_CONFIG(word, u16)
186 PCI_USER_READ_CONFIG(dword, u32)
187 PCI_USER_WRITE_CONFIG(byte, u8)
188 PCI_USER_WRITE_CONFIG(word, u16)
189 PCI_USER_WRITE_CONFIG(dword, u32)
190
191 /* VPD access through PCI 2.2+ VPD capability */
192
193 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
194
195 struct pci_vpd_pci22 {
196 struct pci_vpd base;
197 struct mutex lock;
198 u16 flag;
199 bool busy;
200 u8 cap;
201 };
202
203 /*
204 * Wait for last operation to complete.
205 * This code has to spin since there is no other notification from the PCI
206 * hardware. Since the VPD is often implemented by serial attachment to an
207 * EEPROM, it may take many milliseconds to complete.
208 *
209 * Returns 0 on success, negative values indicate error.
210 */
pci_vpd_pci22_wait(struct pci_dev * dev)211 static int pci_vpd_pci22_wait(struct pci_dev *dev)
212 {
213 struct pci_vpd_pci22 *vpd =
214 container_of(dev->vpd, struct pci_vpd_pci22, base);
215 unsigned long timeout = jiffies + HZ/20 + 2;
216 u16 status;
217 int ret;
218
219 if (!vpd->busy)
220 return 0;
221
222 for (;;) {
223 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
224 &status);
225 if (ret < 0)
226 return ret;
227
228 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
229 vpd->busy = false;
230 return 0;
231 }
232
233 if (time_after(jiffies, timeout)) {
234 dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
235 return -ETIMEDOUT;
236 }
237 if (fatal_signal_pending(current))
238 return -EINTR;
239 if (!cond_resched())
240 udelay(10);
241 }
242 }
243
pci_vpd_pci22_read(struct pci_dev * dev,loff_t pos,size_t count,void * arg)244 static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
245 void *arg)
246 {
247 struct pci_vpd_pci22 *vpd =
248 container_of(dev->vpd, struct pci_vpd_pci22, base);
249 int ret;
250 loff_t end = pos + count;
251 u8 *buf = arg;
252
253 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
254 return -EINVAL;
255
256 if (mutex_lock_killable(&vpd->lock))
257 return -EINTR;
258
259 ret = pci_vpd_pci22_wait(dev);
260 if (ret < 0)
261 goto out;
262
263 while (pos < end) {
264 u32 val;
265 unsigned int i, skip;
266
267 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
268 pos & ~3);
269 if (ret < 0)
270 break;
271 vpd->busy = true;
272 vpd->flag = PCI_VPD_ADDR_F;
273 ret = pci_vpd_pci22_wait(dev);
274 if (ret < 0)
275 break;
276
277 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
278 if (ret < 0)
279 break;
280
281 skip = pos & 3;
282 for (i = 0; i < sizeof(u32); i++) {
283 if (i >= skip) {
284 *buf++ = val;
285 if (++pos == end)
286 break;
287 }
288 val >>= 8;
289 }
290 }
291 out:
292 mutex_unlock(&vpd->lock);
293 return ret ? ret : count;
294 }
295
pci_vpd_pci22_write(struct pci_dev * dev,loff_t pos,size_t count,const void * arg)296 static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
297 const void *arg)
298 {
299 struct pci_vpd_pci22 *vpd =
300 container_of(dev->vpd, struct pci_vpd_pci22, base);
301 const u8 *buf = arg;
302 loff_t end = pos + count;
303 int ret = 0;
304
305 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
306 return -EINVAL;
307
308 if (mutex_lock_killable(&vpd->lock))
309 return -EINTR;
310
311 ret = pci_vpd_pci22_wait(dev);
312 if (ret < 0)
313 goto out;
314
315 while (pos < end) {
316 u32 val;
317
318 val = *buf++;
319 val |= *buf++ << 8;
320 val |= *buf++ << 16;
321 val |= *buf++ << 24;
322
323 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
324 if (ret < 0)
325 break;
326 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
327 pos | PCI_VPD_ADDR_F);
328 if (ret < 0)
329 break;
330
331 vpd->busy = true;
332 vpd->flag = 0;
333 ret = pci_vpd_pci22_wait(dev);
334 if (ret < 0)
335 break;
336
337 pos += sizeof(u32);
338 }
339 out:
340 mutex_unlock(&vpd->lock);
341 return ret ? ret : count;
342 }
343
pci_vpd_pci22_release(struct pci_dev * dev)344 static void pci_vpd_pci22_release(struct pci_dev *dev)
345 {
346 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
347 }
348
349 static const struct pci_vpd_ops pci_vpd_pci22_ops = {
350 .read = pci_vpd_pci22_read,
351 .write = pci_vpd_pci22_write,
352 .release = pci_vpd_pci22_release,
353 };
354
pci_vpd_f0_read(struct pci_dev * dev,loff_t pos,size_t count,void * arg)355 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
356 void *arg)
357 {
358 struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
359 ssize_t ret;
360
361 if (!tdev)
362 return -ENODEV;
363
364 ret = pci_read_vpd(tdev, pos, count, arg);
365 pci_dev_put(tdev);
366 return ret;
367 }
368
pci_vpd_f0_write(struct pci_dev * dev,loff_t pos,size_t count,const void * arg)369 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
370 const void *arg)
371 {
372 struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
373 ssize_t ret;
374
375 if (!tdev)
376 return -ENODEV;
377
378 ret = pci_write_vpd(tdev, pos, count, arg);
379 pci_dev_put(tdev);
380 return ret;
381 }
382
383 static const struct pci_vpd_ops pci_vpd_f0_ops = {
384 .read = pci_vpd_f0_read,
385 .write = pci_vpd_f0_write,
386 .release = pci_vpd_pci22_release,
387 };
388
pci_vpd_f0_dev_check(struct pci_dev * dev)389 static int pci_vpd_f0_dev_check(struct pci_dev *dev)
390 {
391 struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
392 int ret = 0;
393
394 if (!tdev)
395 return -ENODEV;
396 if (!tdev->vpd || !tdev->multifunction ||
397 dev->class != tdev->class || dev->vendor != tdev->vendor ||
398 dev->device != tdev->device)
399 ret = -ENODEV;
400
401 pci_dev_put(tdev);
402 return ret;
403 }
404
pci_vpd_pci22_init(struct pci_dev * dev)405 int pci_vpd_pci22_init(struct pci_dev *dev)
406 {
407 struct pci_vpd_pci22 *vpd;
408 u8 cap;
409
410 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
411 if (!cap)
412 return -ENODEV;
413 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
414 int ret = pci_vpd_f0_dev_check(dev);
415
416 if (ret)
417 return ret;
418 }
419 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
420 if (!vpd)
421 return -ENOMEM;
422
423 vpd->base.len = PCI_VPD_PCI22_SIZE;
424 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
425 vpd->base.ops = &pci_vpd_f0_ops;
426 else
427 vpd->base.ops = &pci_vpd_pci22_ops;
428 mutex_init(&vpd->lock);
429 vpd->cap = cap;
430 vpd->busy = false;
431 dev->vpd = &vpd->base;
432 return 0;
433 }
434
435 /**
436 * pci_cfg_access_lock - Lock PCI config reads/writes
437 * @dev: pci device struct
438 *
439 * When access is locked, any userspace reads or writes to config
440 * space and concurrent lock requests will sleep until access is
441 * allowed via pci_cfg_access_unlocked again.
442 */
pci_cfg_access_lock(struct pci_dev * dev)443 void pci_cfg_access_lock(struct pci_dev *dev)
444 {
445 might_sleep();
446
447 raw_spin_lock_irq(&pci_lock);
448 if (dev->block_cfg_access)
449 pci_wait_cfg(dev);
450 dev->block_cfg_access = 1;
451 raw_spin_unlock_irq(&pci_lock);
452 }
453 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
454
455 /**
456 * pci_cfg_access_trylock - try to lock PCI config reads/writes
457 * @dev: pci device struct
458 *
459 * Same as pci_cfg_access_lock, but will return 0 if access is
460 * already locked, 1 otherwise. This function can be used from
461 * atomic contexts.
462 */
pci_cfg_access_trylock(struct pci_dev * dev)463 bool pci_cfg_access_trylock(struct pci_dev *dev)
464 {
465 unsigned long flags;
466 bool locked = true;
467
468 raw_spin_lock_irqsave(&pci_lock, flags);
469 if (dev->block_cfg_access)
470 locked = false;
471 else
472 dev->block_cfg_access = 1;
473 raw_spin_unlock_irqrestore(&pci_lock, flags);
474
475 return locked;
476 }
477 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
478
479 /**
480 * pci_cfg_access_unlock - Unlock PCI config reads/writes
481 * @dev: pci device struct
482 *
483 * This function allows PCI config accesses to resume.
484 */
pci_cfg_access_unlock(struct pci_dev * dev)485 void pci_cfg_access_unlock(struct pci_dev *dev)
486 {
487 unsigned long flags;
488
489 raw_spin_lock_irqsave(&pci_lock, flags);
490
491 /* This indicates a problem in the caller, but we don't need
492 * to kill them, unlike a double-block above. */
493 WARN_ON(!dev->block_cfg_access);
494
495 dev->block_cfg_access = 0;
496 wake_up_all(&pci_cfg_wait);
497 raw_spin_unlock_irqrestore(&pci_lock, flags);
498 }
499 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
500
pcie_cap_version(const struct pci_dev * dev)501 static inline int pcie_cap_version(const struct pci_dev *dev)
502 {
503 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
504 }
505
pcie_cap_has_lnkctl(const struct pci_dev * dev)506 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
507 {
508 int type = pci_pcie_type(dev);
509
510 return type == PCI_EXP_TYPE_ENDPOINT ||
511 type == PCI_EXP_TYPE_LEG_END ||
512 type == PCI_EXP_TYPE_ROOT_PORT ||
513 type == PCI_EXP_TYPE_UPSTREAM ||
514 type == PCI_EXP_TYPE_DOWNSTREAM ||
515 type == PCI_EXP_TYPE_PCI_BRIDGE ||
516 type == PCI_EXP_TYPE_PCIE_BRIDGE;
517 }
518
pcie_cap_has_sltctl(const struct pci_dev * dev)519 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
520 {
521 int type = pci_pcie_type(dev);
522
523 return (type == PCI_EXP_TYPE_ROOT_PORT ||
524 type == PCI_EXP_TYPE_DOWNSTREAM) &&
525 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
526 }
527
pcie_cap_has_rtctl(const struct pci_dev * dev)528 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
529 {
530 int type = pci_pcie_type(dev);
531
532 return type == PCI_EXP_TYPE_ROOT_PORT ||
533 type == PCI_EXP_TYPE_RC_EC;
534 }
535
pcie_capability_reg_implemented(struct pci_dev * dev,int pos)536 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
537 {
538 if (!pci_is_pcie(dev))
539 return false;
540
541 switch (pos) {
542 case PCI_EXP_FLAGS:
543 return true;
544 case PCI_EXP_DEVCAP:
545 case PCI_EXP_DEVCTL:
546 case PCI_EXP_DEVSTA:
547 return true;
548 case PCI_EXP_LNKCAP:
549 case PCI_EXP_LNKCTL:
550 case PCI_EXP_LNKSTA:
551 return pcie_cap_has_lnkctl(dev);
552 case PCI_EXP_SLTCAP:
553 case PCI_EXP_SLTCTL:
554 case PCI_EXP_SLTSTA:
555 return pcie_cap_has_sltctl(dev);
556 case PCI_EXP_RTCTL:
557 case PCI_EXP_RTCAP:
558 case PCI_EXP_RTSTA:
559 return pcie_cap_has_rtctl(dev);
560 case PCI_EXP_DEVCAP2:
561 case PCI_EXP_DEVCTL2:
562 case PCI_EXP_LNKCAP2:
563 case PCI_EXP_LNKCTL2:
564 case PCI_EXP_LNKSTA2:
565 return pcie_cap_version(dev) > 1;
566 default:
567 return false;
568 }
569 }
570
571 /*
572 * Note that these accessor functions are only for the "PCI Express
573 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
574 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
575 */
pcie_capability_read_word(struct pci_dev * dev,int pos,u16 * val)576 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
577 {
578 int ret;
579
580 *val = 0;
581 if (pos & 1)
582 return -EINVAL;
583
584 if (pcie_capability_reg_implemented(dev, pos)) {
585 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
586 /*
587 * Reset *val to 0 if pci_read_config_word() fails, it may
588 * have been written as 0xFFFF if hardware error happens
589 * during pci_read_config_word().
590 */
591 if (ret)
592 *val = 0;
593 return ret;
594 }
595
596 /*
597 * For Functions that do not implement the Slot Capabilities,
598 * Slot Status, and Slot Control registers, these spaces must
599 * be hardwired to 0b, with the exception of the Presence Detect
600 * State bit in the Slot Status register of Downstream Ports,
601 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
602 */
603 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
604 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
605 *val = PCI_EXP_SLTSTA_PDS;
606 }
607
608 return 0;
609 }
610 EXPORT_SYMBOL(pcie_capability_read_word);
611
pcie_capability_read_dword(struct pci_dev * dev,int pos,u32 * val)612 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
613 {
614 int ret;
615
616 *val = 0;
617 if (pos & 3)
618 return -EINVAL;
619
620 if (pcie_capability_reg_implemented(dev, pos)) {
621 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
622 /*
623 * Reset *val to 0 if pci_read_config_dword() fails, it may
624 * have been written as 0xFFFFFFFF if hardware error happens
625 * during pci_read_config_dword().
626 */
627 if (ret)
628 *val = 0;
629 return ret;
630 }
631
632 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
633 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
634 *val = PCI_EXP_SLTSTA_PDS;
635 }
636
637 return 0;
638 }
639 EXPORT_SYMBOL(pcie_capability_read_dword);
640
pcie_capability_write_word(struct pci_dev * dev,int pos,u16 val)641 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
642 {
643 if (pos & 1)
644 return -EINVAL;
645
646 if (!pcie_capability_reg_implemented(dev, pos))
647 return 0;
648
649 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
650 }
651 EXPORT_SYMBOL(pcie_capability_write_word);
652
pcie_capability_write_dword(struct pci_dev * dev,int pos,u32 val)653 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
654 {
655 if (pos & 3)
656 return -EINVAL;
657
658 if (!pcie_capability_reg_implemented(dev, pos))
659 return 0;
660
661 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
662 }
663 EXPORT_SYMBOL(pcie_capability_write_dword);
664
pcie_capability_clear_and_set_word(struct pci_dev * dev,int pos,u16 clear,u16 set)665 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
666 u16 clear, u16 set)
667 {
668 int ret;
669 u16 val;
670
671 ret = pcie_capability_read_word(dev, pos, &val);
672 if (!ret) {
673 val &= ~clear;
674 val |= set;
675 ret = pcie_capability_write_word(dev, pos, val);
676 }
677
678 return ret;
679 }
680 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
681
pcie_capability_clear_and_set_dword(struct pci_dev * dev,int pos,u32 clear,u32 set)682 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
683 u32 clear, u32 set)
684 {
685 int ret;
686 u32 val;
687
688 ret = pcie_capability_read_dword(dev, pos, &val);
689 if (!ret) {
690 val &= ~clear;
691 val |= set;
692 ret = pcie_capability_write_dword(dev, pos, val);
693 }
694
695 return ret;
696 }
697 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
698