1 /*
2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/pci.h>
34 #include <linux/io.h>
35 #include <linux/delay.h>
36 #include <linux/vmalloc.h>
37 #include <linux/aer.h>
38 #include <linux/module.h>
39
40 #include "qib.h"
41
42 /*
43 * This file contains PCIe utility routines that are common to the
44 * various QLogic InfiniPath adapters
45 */
46
47 /*
48 * Code to adjust PCIe capabilities.
49 * To minimize the change footprint, we call it
50 * from qib_pcie_params, which every chip-specific
51 * file calls, even though this violates some
52 * expectations of harmlessness.
53 */
54 static void qib_tune_pcie_caps(struct qib_devdata *);
55 static void qib_tune_pcie_coalesce(struct qib_devdata *);
56
57 /*
58 * Do all the common PCIe setup and initialization.
59 * devdata is not yet allocated, and is not allocated until after this
60 * routine returns success. Therefore qib_dev_err() can't be used for error
61 * printing.
62 */
qib_pcie_init(struct pci_dev * pdev,const struct pci_device_id * ent)63 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
64 {
65 int ret;
66
67 ret = pci_enable_device(pdev);
68 if (ret) {
69 /*
70 * This can happen (in theory) iff:
71 * We did a chip reset, and then failed to reprogram the
72 * BAR, or the chip reset due to an internal error. We then
73 * unloaded the driver and reloaded it.
74 *
75 * Both reset cases set the BAR back to initial state. For
76 * the latter case, the AER sticky error bit at offset 0x718
77 * should be set, but the Linux kernel doesn't yet know
78 * about that, it appears. If the original BAR was retained
79 * in the kernel data structures, this may be OK.
80 */
81 qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
82 -ret);
83 goto done;
84 }
85
86 ret = pci_request_regions(pdev, QIB_DRV_NAME);
87 if (ret) {
88 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
89 goto bail;
90 }
91
92 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
93 if (ret) {
94 /*
95 * If the 64 bit setup fails, try 32 bit. Some systems
96 * do not setup 64 bit maps on systems with 2GB or less
97 * memory installed.
98 */
99 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
100 if (ret) {
101 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
102 goto bail;
103 }
104 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
105 } else
106 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
107 if (ret) {
108 qib_early_err(&pdev->dev,
109 "Unable to set DMA consistent mask: %d\n", ret);
110 goto bail;
111 }
112
113 pci_set_master(pdev);
114 ret = pci_enable_pcie_error_reporting(pdev);
115 if (ret) {
116 qib_early_err(&pdev->dev,
117 "Unable to enable pcie error reporting: %d\n",
118 ret);
119 ret = 0;
120 }
121 goto done;
122
123 bail:
124 pci_disable_device(pdev);
125 pci_release_regions(pdev);
126 done:
127 return ret;
128 }
129
130 /*
131 * Do remaining PCIe setup, once dd is allocated, and save away
132 * fields required to re-initialize after a chip reset, or for
133 * various other purposes
134 */
qib_pcie_ddinit(struct qib_devdata * dd,struct pci_dev * pdev,const struct pci_device_id * ent)135 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
136 const struct pci_device_id *ent)
137 {
138 unsigned long len;
139 resource_size_t addr;
140
141 dd->pcidev = pdev;
142 pci_set_drvdata(pdev, dd);
143
144 addr = pci_resource_start(pdev, 0);
145 len = pci_resource_len(pdev, 0);
146
147 #if defined(__powerpc__)
148 /* There isn't a generic way to specify writethrough mappings */
149 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU);
150 #else
151 dd->kregbase = ioremap_nocache(addr, len);
152 #endif
153
154 if (!dd->kregbase)
155 return -ENOMEM;
156
157 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
158 dd->physaddr = addr; /* used for io_remap, etc. */
159
160 /*
161 * Save BARs to rewrite after device reset. Save all 64 bits of
162 * BAR, just in case.
163 */
164 dd->pcibar0 = addr;
165 dd->pcibar1 = addr >> 32;
166 dd->deviceid = ent->device; /* save for later use */
167 dd->vendorid = ent->vendor;
168
169 return 0;
170 }
171
172 /*
173 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior
174 * to releasing the dd memory.
175 * void because none of the core pcie cleanup returns are void
176 */
qib_pcie_ddcleanup(struct qib_devdata * dd)177 void qib_pcie_ddcleanup(struct qib_devdata *dd)
178 {
179 u64 __iomem *base = (void __iomem *) dd->kregbase;
180
181 dd->kregbase = NULL;
182 iounmap(base);
183 if (dd->piobase)
184 iounmap(dd->piobase);
185 if (dd->userbase)
186 iounmap(dd->userbase);
187 if (dd->piovl15base)
188 iounmap(dd->piovl15base);
189
190 pci_disable_device(dd->pcidev);
191 pci_release_regions(dd->pcidev);
192
193 pci_set_drvdata(dd->pcidev, NULL);
194 }
195
qib_msix_setup(struct qib_devdata * dd,int pos,u32 * msixcnt,struct qib_msix_entry * qib_msix_entry)196 static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt,
197 struct qib_msix_entry *qib_msix_entry)
198 {
199 int ret;
200 int nvec = *msixcnt;
201 struct msix_entry *msix_entry;
202 int i;
203
204 ret = pci_msix_vec_count(dd->pcidev);
205 if (ret < 0)
206 goto do_intx;
207
208 nvec = min(nvec, ret);
209
210 /* We can't pass qib_msix_entry array to qib_msix_setup
211 * so use a dummy msix_entry array and copy the allocated
212 * irq back to the qib_msix_entry array. */
213 msix_entry = kmalloc(nvec * sizeof(*msix_entry), GFP_KERNEL);
214 if (!msix_entry)
215 goto do_intx;
216
217 for (i = 0; i < nvec; i++)
218 msix_entry[i] = qib_msix_entry[i].msix;
219
220 ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec);
221 if (ret < 0)
222 goto free_msix_entry;
223 else
224 nvec = ret;
225
226 for (i = 0; i < nvec; i++)
227 qib_msix_entry[i].msix = msix_entry[i];
228
229 kfree(msix_entry);
230 *msixcnt = nvec;
231 return;
232
233 free_msix_entry:
234 kfree(msix_entry);
235
236 do_intx:
237 qib_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, "
238 "falling back to INTx\n", nvec, ret);
239 *msixcnt = 0;
240 qib_enable_intx(dd->pcidev);
241 }
242
243 /**
244 * We save the msi lo and hi values, so we can restore them after
245 * chip reset (the kernel PCI infrastructure doesn't yet handle that
246 * correctly.
247 */
qib_msi_setup(struct qib_devdata * dd,int pos)248 static int qib_msi_setup(struct qib_devdata *dd, int pos)
249 {
250 struct pci_dev *pdev = dd->pcidev;
251 u16 control;
252 int ret;
253
254 ret = pci_enable_msi(pdev);
255 if (ret)
256 qib_dev_err(dd,
257 "pci_enable_msi failed: %d, interrupts may not work\n",
258 ret);
259 /* continue even if it fails, we may still be OK... */
260
261 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
262 &dd->msi_lo);
263 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
264 &dd->msi_hi);
265 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
266 /* now save the data (vector) info */
267 pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT)
268 ? 12 : 8),
269 &dd->msi_data);
270 return ret;
271 }
272
qib_pcie_params(struct qib_devdata * dd,u32 minw,u32 * nent,struct qib_msix_entry * entry)273 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
274 struct qib_msix_entry *entry)
275 {
276 u16 linkstat, speed;
277 int pos = 0, ret = 1;
278
279 if (!pci_is_pcie(dd->pcidev)) {
280 qib_dev_err(dd, "Can't find PCI Express capability!\n");
281 /* set up something... */
282 dd->lbus_width = 1;
283 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
284 goto bail;
285 }
286
287 pos = dd->pcidev->msix_cap;
288 if (nent && *nent && pos) {
289 qib_msix_setup(dd, pos, nent, entry);
290 ret = 0; /* did it, either MSIx or INTx */
291 } else {
292 pos = dd->pcidev->msi_cap;
293 if (pos)
294 ret = qib_msi_setup(dd, pos);
295 else
296 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
297 }
298 if (!pos)
299 qib_enable_intx(dd->pcidev);
300
301 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
302 /*
303 * speed is bits 0-3, linkwidth is bits 4-8
304 * no defines for them in headers
305 */
306 speed = linkstat & 0xf;
307 linkstat >>= 4;
308 linkstat &= 0x1f;
309 dd->lbus_width = linkstat;
310
311 switch (speed) {
312 case 1:
313 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
314 break;
315 case 2:
316 dd->lbus_speed = 5000; /* Gen1, 5GHz */
317 break;
318 default: /* not defined, assume gen1 */
319 dd->lbus_speed = 2500;
320 break;
321 }
322
323 /*
324 * Check against expected pcie width and complain if "wrong"
325 * on first initialization, not afterwards (i.e., reset).
326 */
327 if (minw && linkstat < minw)
328 qib_dev_err(dd,
329 "PCIe width %u (x%u HCA), performance reduced\n",
330 linkstat, minw);
331
332 qib_tune_pcie_caps(dd);
333
334 qib_tune_pcie_coalesce(dd);
335
336 bail:
337 /* fill in string, even on errors */
338 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
339 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
340 return ret;
341 }
342
343 /*
344 * Setup pcie interrupt stuff again after a reset. I'd like to just call
345 * pci_enable_msi() again for msi, but when I do that,
346 * the MSI enable bit doesn't get set in the command word, and
347 * we switch to to a different interrupt vector, which is confusing,
348 * so I instead just do it all inline. Perhaps somehow can tie this
349 * into the PCIe hotplug support at some point
350 */
qib_reinit_intr(struct qib_devdata * dd)351 int qib_reinit_intr(struct qib_devdata *dd)
352 {
353 int pos;
354 u16 control;
355 int ret = 0;
356
357 /* If we aren't using MSI, don't restore it */
358 if (!dd->msi_lo)
359 goto bail;
360
361 pos = dd->pcidev->msi_cap;
362 if (!pos) {
363 qib_dev_err(dd,
364 "Can't find MSI capability, can't restore MSI settings\n");
365 ret = 0;
366 /* nothing special for MSIx, just MSI */
367 goto bail;
368 }
369 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
370 dd->msi_lo);
371 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
372 dd->msi_hi);
373 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
374 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
375 control |= PCI_MSI_FLAGS_ENABLE;
376 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
377 control);
378 }
379 /* now rewrite the data (vector) info */
380 pci_write_config_word(dd->pcidev, pos +
381 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
382 dd->msi_data);
383 ret = 1;
384 bail:
385 if (!ret && (dd->flags & QIB_HAS_INTX)) {
386 qib_enable_intx(dd->pcidev);
387 ret = 1;
388 }
389
390 /* and now set the pci master bit again */
391 pci_set_master(dd->pcidev);
392
393 return ret;
394 }
395
396 /*
397 * Disable msi interrupt if enabled, and clear msi_lo.
398 * This is used primarily for the fallback to INTx, but
399 * is also used in reinit after reset, and during cleanup.
400 */
qib_nomsi(struct qib_devdata * dd)401 void qib_nomsi(struct qib_devdata *dd)
402 {
403 dd->msi_lo = 0;
404 pci_disable_msi(dd->pcidev);
405 }
406
407 /*
408 * Same as qib_nosmi, but for MSIx.
409 */
qib_nomsix(struct qib_devdata * dd)410 void qib_nomsix(struct qib_devdata *dd)
411 {
412 pci_disable_msix(dd->pcidev);
413 }
414
415 /*
416 * Similar to pci_intx(pdev, 1), except that we make sure
417 * msi(x) is off.
418 */
qib_enable_intx(struct pci_dev * pdev)419 void qib_enable_intx(struct pci_dev *pdev)
420 {
421 u16 cw, new;
422 int pos;
423
424 /* first, turn on INTx */
425 pci_read_config_word(pdev, PCI_COMMAND, &cw);
426 new = cw & ~PCI_COMMAND_INTX_DISABLE;
427 if (new != cw)
428 pci_write_config_word(pdev, PCI_COMMAND, new);
429
430 pos = pdev->msi_cap;
431 if (pos) {
432 /* then turn off MSI */
433 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
434 new = cw & ~PCI_MSI_FLAGS_ENABLE;
435 if (new != cw)
436 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
437 }
438 pos = pdev->msix_cap;
439 if (pos) {
440 /* then turn off MSIx */
441 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw);
442 new = cw & ~PCI_MSIX_FLAGS_ENABLE;
443 if (new != cw)
444 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new);
445 }
446 }
447
448 /*
449 * These two routines are helper routines for the device reset code
450 * to move all the pcie code out of the chip-specific driver code.
451 */
qib_pcie_getcmd(struct qib_devdata * dd,u16 * cmd,u8 * iline,u8 * cline)452 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
453 {
454 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
455 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
456 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
457 }
458
qib_pcie_reenable(struct qib_devdata * dd,u16 cmd,u8 iline,u8 cline)459 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
460 {
461 int r;
462 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
463 dd->pcibar0);
464 if (r)
465 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
466 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
467 dd->pcibar1);
468 if (r)
469 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
470 /* now re-enable memory access, and restore cosmetic settings */
471 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
472 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
473 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
474 r = pci_enable_device(dd->pcidev);
475 if (r)
476 qib_dev_err(dd,
477 "pci_enable_device failed after reset: %d\n", r);
478 }
479
480
481 static int qib_pcie_coalesce;
482 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
483 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
484
485 /*
486 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
487 * chipsets. This is known to be unsafe for some revisions of some
488 * of these chipsets, with some BIOS settings, and enabling it on those
489 * systems may result in the system crashing, and/or data corruption.
490 */
qib_tune_pcie_coalesce(struct qib_devdata * dd)491 static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
492 {
493 int r;
494 struct pci_dev *parent;
495 u16 devid;
496 u32 mask, bits, val;
497
498 if (!qib_pcie_coalesce)
499 return;
500
501 /* Find out supported and configured values for parent (root) */
502 parent = dd->pcidev->bus->self;
503 if (parent->bus->parent) {
504 qib_devinfo(dd->pcidev, "Parent not root\n");
505 return;
506 }
507 if (!pci_is_pcie(parent))
508 return;
509 if (parent->vendor != 0x8086)
510 return;
511
512 /*
513 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1
514 * - bit 11: COALESCE_FORCE: need to set to 0
515 * - bit 10: COALESCE_EN: need to set to 1
516 * (but limitations on some on some chipsets)
517 *
518 * On the Intel 5000, 5100, and 7300 chipsets, there is
519 * also: - bit 25:24: COALESCE_MODE, need to set to 0
520 */
521 devid = parent->device;
522 if (devid >= 0x25e2 && devid <= 0x25fa) {
523 /* 5000 P/V/X/Z */
524 if (parent->revision <= 0xb2)
525 bits = 1U << 10;
526 else
527 bits = 7U << 10;
528 mask = (3U << 24) | (7U << 10);
529 } else if (devid >= 0x65e2 && devid <= 0x65fa) {
530 /* 5100 */
531 bits = 1U << 10;
532 mask = (3U << 24) | (7U << 10);
533 } else if (devid >= 0x4021 && devid <= 0x402e) {
534 /* 5400 */
535 bits = 7U << 10;
536 mask = 7U << 10;
537 } else if (devid >= 0x3604 && devid <= 0x360a) {
538 /* 7300 */
539 bits = 7U << 10;
540 mask = (3U << 24) | (7U << 10);
541 } else {
542 /* not one of the chipsets that we know about */
543 return;
544 }
545 pci_read_config_dword(parent, 0x48, &val);
546 val &= ~mask;
547 val |= bits;
548 r = pci_write_config_dword(parent, 0x48, val);
549 }
550
551 /*
552 * BIOS may not set PCIe bus-utilization parameters for best performance.
553 * Check and optionally adjust them to maximize our throughput.
554 */
555 static int qib_pcie_caps;
556 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
557 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
558
qib_tune_pcie_caps(struct qib_devdata * dd)559 static void qib_tune_pcie_caps(struct qib_devdata *dd)
560 {
561 struct pci_dev *parent;
562 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
563 u16 rc_mrrs, ep_mrrs, max_mrrs;
564
565 /* Find out supported and configured values for parent (root) */
566 parent = dd->pcidev->bus->self;
567 if (!pci_is_root_bus(parent->bus)) {
568 qib_devinfo(dd->pcidev, "Parent not root\n");
569 return;
570 }
571
572 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
573 return;
574
575 rc_mpss = parent->pcie_mpss;
576 rc_mps = ffs(pcie_get_mps(parent)) - 8;
577 /* Find out supported and configured values for endpoint (us) */
578 ep_mpss = dd->pcidev->pcie_mpss;
579 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
580
581 /* Find max payload supported by root, endpoint */
582 if (rc_mpss > ep_mpss)
583 rc_mpss = ep_mpss;
584
585 /* If Supported greater than limit in module param, limit it */
586 if (rc_mpss > (qib_pcie_caps & 7))
587 rc_mpss = qib_pcie_caps & 7;
588 /* If less than (allowed, supported), bump root payload */
589 if (rc_mpss > rc_mps) {
590 rc_mps = rc_mpss;
591 pcie_set_mps(parent, 128 << rc_mps);
592 }
593 /* If less than (allowed, supported), bump endpoint payload */
594 if (rc_mpss > ep_mps) {
595 ep_mps = rc_mpss;
596 pcie_set_mps(dd->pcidev, 128 << ep_mps);
597 }
598
599 /*
600 * Now the Read Request size.
601 * No field for max supported, but PCIe spec limits it to 4096,
602 * which is code '5' (log2(4096) - 7)
603 */
604 max_mrrs = 5;
605 if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
606 max_mrrs = (qib_pcie_caps >> 4) & 7;
607
608 max_mrrs = 128 << max_mrrs;
609 rc_mrrs = pcie_get_readrq(parent);
610 ep_mrrs = pcie_get_readrq(dd->pcidev);
611
612 if (max_mrrs > rc_mrrs) {
613 rc_mrrs = max_mrrs;
614 pcie_set_readrq(parent, rc_mrrs);
615 }
616 if (max_mrrs > ep_mrrs) {
617 ep_mrrs = max_mrrs;
618 pcie_set_readrq(dd->pcidev, ep_mrrs);
619 }
620 }
621 /* End of PCIe capability tuning */
622
623 /*
624 * From here through qib_pci_err_handler definition is invoked via
625 * PCI error infrastructure, registered via pci
626 */
627 static pci_ers_result_t
qib_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)628 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
629 {
630 struct qib_devdata *dd = pci_get_drvdata(pdev);
631 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
632
633 switch (state) {
634 case pci_channel_io_normal:
635 qib_devinfo(pdev, "State Normal, ignoring\n");
636 break;
637
638 case pci_channel_io_frozen:
639 qib_devinfo(pdev, "State Frozen, requesting reset\n");
640 pci_disable_device(pdev);
641 ret = PCI_ERS_RESULT_NEED_RESET;
642 break;
643
644 case pci_channel_io_perm_failure:
645 qib_devinfo(pdev, "State Permanent Failure, disabling\n");
646 if (dd) {
647 /* no more register accesses! */
648 dd->flags &= ~QIB_PRESENT;
649 qib_disable_after_error(dd);
650 }
651 /* else early, or other problem */
652 ret = PCI_ERS_RESULT_DISCONNECT;
653 break;
654
655 default: /* shouldn't happen */
656 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
657 state);
658 break;
659 }
660 return ret;
661 }
662
663 static pci_ers_result_t
qib_pci_mmio_enabled(struct pci_dev * pdev)664 qib_pci_mmio_enabled(struct pci_dev *pdev)
665 {
666 u64 words = 0U;
667 struct qib_devdata *dd = pci_get_drvdata(pdev);
668 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
669
670 if (dd && dd->pport) {
671 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
672 if (words == ~0ULL)
673 ret = PCI_ERS_RESULT_NEED_RESET;
674 }
675 qib_devinfo(pdev,
676 "QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
677 words, ret);
678 return ret;
679 }
680
681 static pci_ers_result_t
qib_pci_slot_reset(struct pci_dev * pdev)682 qib_pci_slot_reset(struct pci_dev *pdev)
683 {
684 qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
685 return PCI_ERS_RESULT_CAN_RECOVER;
686 }
687
688 static pci_ers_result_t
qib_pci_link_reset(struct pci_dev * pdev)689 qib_pci_link_reset(struct pci_dev *pdev)
690 {
691 qib_devinfo(pdev, "QIB link_reset function called, ignored\n");
692 return PCI_ERS_RESULT_CAN_RECOVER;
693 }
694
695 static void
qib_pci_resume(struct pci_dev * pdev)696 qib_pci_resume(struct pci_dev *pdev)
697 {
698 struct qib_devdata *dd = pci_get_drvdata(pdev);
699 qib_devinfo(pdev, "QIB resume function called\n");
700 pci_cleanup_aer_uncorrect_error_status(pdev);
701 /*
702 * Running jobs will fail, since it's asynchronous
703 * unlike sysfs-requested reset. Better than
704 * doing nothing.
705 */
706 qib_init(dd, 1); /* same as re-init after reset */
707 }
708
709 const struct pci_error_handlers qib_pci_err_handler = {
710 .error_detected = qib_pci_error_detected,
711 .mmio_enabled = qib_pci_mmio_enabled,
712 .link_reset = qib_pci_link_reset,
713 .slot_reset = qib_pci_slot_reset,
714 .resume = qib_pci_resume,
715 };
716