1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26 #include <linux/hdmi.h>
27 #include <linux/gcd.h>
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "r600d.h"
33 #include "atom.h"
34
35 /*
36 * HDMI color format
37 */
38 enum r600_hdmi_color_format {
39 RGB = 0,
40 YCC_422 = 1,
41 YCC_444 = 2
42 };
43
44 /*
45 * IEC60958 status bits
46 */
47 enum r600_hdmi_iec_status_bits {
48 AUDIO_STATUS_DIG_ENABLE = 0x01,
49 AUDIO_STATUS_V = 0x02,
50 AUDIO_STATUS_VCFG = 0x04,
51 AUDIO_STATUS_EMPHASIS = 0x08,
52 AUDIO_STATUS_COPYRIGHT = 0x10,
53 AUDIO_STATUS_NONAUDIO = 0x20,
54 AUDIO_STATUS_PROFESSIONAL = 0x40,
55 AUDIO_STATUS_LEVEL = 0x80
56 };
57
58 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
59 /* 32kHz 44.1kHz 48kHz */
60 /* Clock N CTS N CTS N CTS */
61 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
62 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
63 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
64 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
65 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
66 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
67 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
68 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
69 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
70 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
71 };
72
73
74 /*
75 * check if the chipset is supported
76 */
r600_audio_chipset_supported(struct radeon_device * rdev)77 static int r600_audio_chipset_supported(struct radeon_device *rdev)
78 {
79 return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
80 }
81
r600_audio_status(struct radeon_device * rdev)82 static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
83 {
84 struct r600_audio_pin status;
85 uint32_t value;
86
87 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
88
89 /* number of channels */
90 status.channels = (value & 0x7) + 1;
91
92 /* bits per sample */
93 switch ((value & 0xF0) >> 4) {
94 case 0x0:
95 status.bits_per_sample = 8;
96 break;
97 case 0x1:
98 status.bits_per_sample = 16;
99 break;
100 case 0x2:
101 status.bits_per_sample = 20;
102 break;
103 case 0x3:
104 status.bits_per_sample = 24;
105 break;
106 case 0x4:
107 status.bits_per_sample = 32;
108 break;
109 default:
110 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
111 (int)value);
112 status.bits_per_sample = 16;
113 }
114
115 /* current sampling rate in HZ */
116 if (value & 0x4000)
117 status.rate = 44100;
118 else
119 status.rate = 48000;
120 status.rate *= ((value >> 11) & 0x7) + 1;
121 status.rate /= ((value >> 8) & 0x7) + 1;
122
123 value = RREG32(R600_AUDIO_STATUS_BITS);
124
125 /* iec 60958 status bits */
126 status.status_bits = value & 0xff;
127
128 /* iec 60958 category code */
129 status.category_code = (value >> 8) & 0xff;
130
131 return status;
132 }
133
134 /*
135 * update all hdmi interfaces with current audio parameters
136 */
r600_audio_update_hdmi(struct work_struct * work)137 void r600_audio_update_hdmi(struct work_struct *work)
138 {
139 struct radeon_device *rdev = container_of(work, struct radeon_device,
140 audio_work);
141 struct drm_device *dev = rdev->ddev;
142 struct r600_audio_pin audio_status = r600_audio_status(rdev);
143 struct drm_encoder *encoder;
144 bool changed = false;
145
146 if (rdev->audio.pin[0].channels != audio_status.channels ||
147 rdev->audio.pin[0].rate != audio_status.rate ||
148 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
149 rdev->audio.pin[0].status_bits != audio_status.status_bits ||
150 rdev->audio.pin[0].category_code != audio_status.category_code) {
151 rdev->audio.pin[0] = audio_status;
152 changed = true;
153 }
154
155 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
156 if (!radeon_encoder_is_digital(encoder))
157 continue;
158 if (changed || r600_hdmi_buffer_status_changed(encoder))
159 r600_hdmi_update_audio_settings(encoder);
160 }
161 }
162
163 /* enable the audio stream */
r600_audio_enable(struct radeon_device * rdev,struct r600_audio_pin * pin,u8 enable_mask)164 void r600_audio_enable(struct radeon_device *rdev,
165 struct r600_audio_pin *pin,
166 u8 enable_mask)
167 {
168 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
169
170 if (!pin)
171 return;
172
173 if (enable_mask) {
174 tmp |= AUDIO_ENABLED;
175 if (enable_mask & 1)
176 tmp |= PIN0_AUDIO_ENABLED;
177 if (enable_mask & 2)
178 tmp |= PIN1_AUDIO_ENABLED;
179 if (enable_mask & 4)
180 tmp |= PIN2_AUDIO_ENABLED;
181 if (enable_mask & 8)
182 tmp |= PIN3_AUDIO_ENABLED;
183 } else {
184 tmp &= ~(AUDIO_ENABLED |
185 PIN0_AUDIO_ENABLED |
186 PIN1_AUDIO_ENABLED |
187 PIN2_AUDIO_ENABLED |
188 PIN3_AUDIO_ENABLED);
189 }
190
191 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
192 }
193
194 /*
195 * initialize the audio vars
196 */
r600_audio_init(struct radeon_device * rdev)197 int r600_audio_init(struct radeon_device *rdev)
198 {
199 if (!radeon_audio || !r600_audio_chipset_supported(rdev))
200 return 0;
201
202 rdev->audio.enabled = true;
203
204 rdev->audio.num_pins = 1;
205 rdev->audio.pin[0].channels = -1;
206 rdev->audio.pin[0].rate = -1;
207 rdev->audio.pin[0].bits_per_sample = -1;
208 rdev->audio.pin[0].status_bits = 0;
209 rdev->audio.pin[0].category_code = 0;
210 rdev->audio.pin[0].id = 0;
211 /* disable audio. it will be set up later */
212 r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
213
214 return 0;
215 }
216
217 /*
218 * release the audio timer
219 * TODO: How to do this correctly on SMP systems?
220 */
r600_audio_fini(struct radeon_device * rdev)221 void r600_audio_fini(struct radeon_device *rdev)
222 {
223 if (!rdev->audio.enabled)
224 return;
225
226 r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
227
228 rdev->audio.enabled = false;
229 }
230
r600_audio_get_pin(struct radeon_device * rdev)231 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
232 {
233 /* only one pin on 6xx-NI */
234 return &rdev->audio.pin[0];
235 }
236
237 /*
238 * calculate CTS and N values if they are not found in the table
239 */
r600_hdmi_calc_cts(uint32_t clock,int * CTS,int * N,int freq)240 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
241 {
242 int n, cts;
243 unsigned long div, mul;
244
245 /* Safe, but overly large values */
246 n = 128 * freq;
247 cts = clock * 1000;
248
249 /* Smallest valid fraction */
250 div = gcd(n, cts);
251
252 n /= div;
253 cts /= div;
254
255 /*
256 * The optimal N is 128*freq/1000. Calculate the closest larger
257 * value that doesn't truncate any bits.
258 */
259 mul = ((128*freq/1000) + (n-1))/n;
260
261 n *= mul;
262 cts *= mul;
263
264 /* Check that we are in spec (not always possible) */
265 if (n < (128*freq/1500))
266 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
267 if (n > (128*freq/300))
268 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
269
270 *N = n;
271 *CTS = cts;
272
273 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
274 *N, *CTS, freq);
275 }
276
r600_hdmi_acr(uint32_t clock)277 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
278 {
279 struct radeon_hdmi_acr res;
280 u8 i;
281
282 /* Precalculated values for common clocks */
283 for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
284 if (r600_hdmi_predefined_acr[i].clock == clock)
285 return r600_hdmi_predefined_acr[i];
286 }
287
288 /* And odd clocks get manually calculated */
289 r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
290 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
291 r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
292
293 return res;
294 }
295
296 /*
297 * update the N and CTS parameters for a given pixel clock rate
298 */
r600_hdmi_update_ACR(struct drm_encoder * encoder,uint32_t clock)299 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
300 {
301 struct drm_device *dev = encoder->dev;
302 struct radeon_device *rdev = dev->dev_private;
303 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
305 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
306 uint32_t offset = dig->afmt->offset;
307
308 WREG32_P(HDMI0_ACR_32_0 + offset,
309 HDMI0_ACR_CTS_32(acr.cts_32khz),
310 ~HDMI0_ACR_CTS_32_MASK);
311 WREG32_P(HDMI0_ACR_32_1 + offset,
312 HDMI0_ACR_N_32(acr.n_32khz),
313 ~HDMI0_ACR_N_32_MASK);
314
315 WREG32_P(HDMI0_ACR_44_0 + offset,
316 HDMI0_ACR_CTS_44(acr.cts_44_1khz),
317 ~HDMI0_ACR_CTS_44_MASK);
318 WREG32_P(HDMI0_ACR_44_1 + offset,
319 HDMI0_ACR_N_44(acr.n_44_1khz),
320 ~HDMI0_ACR_N_44_MASK);
321
322 WREG32_P(HDMI0_ACR_48_0 + offset,
323 HDMI0_ACR_CTS_48(acr.cts_48khz),
324 ~HDMI0_ACR_CTS_48_MASK);
325 WREG32_P(HDMI0_ACR_48_1 + offset,
326 HDMI0_ACR_N_48(acr.n_48khz),
327 ~HDMI0_ACR_N_48_MASK);
328 }
329
330 /*
331 * build a HDMI Video Info Frame
332 */
r600_hdmi_update_avi_infoframe(struct drm_encoder * encoder,void * buffer,size_t size)333 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
334 size_t size)
335 {
336 struct drm_device *dev = encoder->dev;
337 struct radeon_device *rdev = dev->dev_private;
338 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
339 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
340 uint32_t offset = dig->afmt->offset;
341 uint8_t *frame = buffer + 3;
342 uint8_t *header = buffer;
343
344 WREG32(HDMI0_AVI_INFO0 + offset,
345 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
346 WREG32(HDMI0_AVI_INFO1 + offset,
347 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
348 WREG32(HDMI0_AVI_INFO2 + offset,
349 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
350 WREG32(HDMI0_AVI_INFO3 + offset,
351 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
352 }
353
354 /*
355 * build a Audio Info Frame
356 */
r600_hdmi_update_audio_infoframe(struct drm_encoder * encoder,const void * buffer,size_t size)357 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
358 const void *buffer, size_t size)
359 {
360 struct drm_device *dev = encoder->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
363 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
364 uint32_t offset = dig->afmt->offset;
365 const u8 *frame = buffer + 3;
366
367 WREG32(HDMI0_AUDIO_INFO0 + offset,
368 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
369 WREG32(HDMI0_AUDIO_INFO1 + offset,
370 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
371 }
372
373 /*
374 * test if audio buffer is filled enough to start playing
375 */
r600_hdmi_is_audio_buffer_filled(struct drm_encoder * encoder)376 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
377 {
378 struct drm_device *dev = encoder->dev;
379 struct radeon_device *rdev = dev->dev_private;
380 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
381 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
382 uint32_t offset = dig->afmt->offset;
383
384 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
385 }
386
387 /*
388 * have buffer status changed since last call?
389 */
r600_hdmi_buffer_status_changed(struct drm_encoder * encoder)390 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
391 {
392 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
393 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
394 int status, result;
395
396 if (!dig->afmt || !dig->afmt->enabled)
397 return 0;
398
399 status = r600_hdmi_is_audio_buffer_filled(encoder);
400 result = dig->afmt->last_buffer_filled_status != status;
401 dig->afmt->last_buffer_filled_status = status;
402
403 return result;
404 }
405
406 /*
407 * write the audio workaround status to the hardware
408 */
r600_hdmi_audio_workaround(struct drm_encoder * encoder)409 void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
410 {
411 struct drm_device *dev = encoder->dev;
412 struct radeon_device *rdev = dev->dev_private;
413 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
414 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
415 uint32_t offset = dig->afmt->offset;
416 bool hdmi_audio_workaround = false; /* FIXME */
417 u32 value;
418
419 if (!hdmi_audio_workaround ||
420 r600_hdmi_is_audio_buffer_filled(encoder))
421 value = 0; /* disable workaround */
422 else
423 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
424 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
425 value, ~HDMI0_AUDIO_TEST_EN);
426 }
427
r600_audio_set_dto(struct drm_encoder * encoder,u32 clock)428 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
429 {
430 struct drm_device *dev = encoder->dev;
431 struct radeon_device *rdev = dev->dev_private;
432 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
433 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
434 u32 base_rate = 24000;
435 u32 max_ratio = clock / base_rate;
436 u32 dto_phase;
437 u32 dto_modulo = clock;
438 u32 wallclock_ratio;
439 u32 dto_cntl;
440
441 if (!dig || !dig->afmt)
442 return;
443
444 if (max_ratio >= 8) {
445 dto_phase = 192 * 1000;
446 wallclock_ratio = 3;
447 } else if (max_ratio >= 4) {
448 dto_phase = 96 * 1000;
449 wallclock_ratio = 2;
450 } else if (max_ratio >= 2) {
451 dto_phase = 48 * 1000;
452 wallclock_ratio = 1;
453 } else {
454 dto_phase = 24 * 1000;
455 wallclock_ratio = 0;
456 }
457
458 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
459 * doesn't matter which one you use. Just use the first one.
460 */
461 /* XXX two dtos; generally use dto0 for hdmi */
462 /* Express [24MHz / target pixel clock] as an exact rational
463 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
464 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
465 */
466 if (ASIC_IS_DCE32(rdev)) {
467 if (dig->dig_encoder == 0) {
468 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
469 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
470 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
471 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
472 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
473 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
474 } else {
475 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
476 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
477 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
478 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
479 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
480 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
481 }
482 } else {
483 /* according to the reg specs, this should DCE3.2 only, but in
484 * practice it seems to cover DCE2.0/3.0/3.1 as well.
485 */
486 if (dig->dig_encoder == 0) {
487 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
488 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
489 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
490 } else {
491 WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
492 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
493 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
494 }
495 }
496 }
497
498 /*
499 * update the info frames with the data from the current display mode
500 */
r600_hdmi_setmode(struct drm_encoder * encoder,struct drm_display_mode * mode)501 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
502 {
503 struct drm_device *dev = encoder->dev;
504 struct radeon_device *rdev = dev->dev_private;
505 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
506 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
507 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
508 struct hdmi_avi_infoframe frame;
509 uint32_t offset;
510 uint32_t acr_ctl;
511 ssize_t err;
512
513 if (!dig || !dig->afmt)
514 return;
515
516 /* Silent, r600_hdmi_enable will raise WARN for us */
517 if (!dig->afmt->enabled)
518 return;
519 offset = dig->afmt->offset;
520
521 /* disable audio prior to setting up hw */
522 dig->afmt->pin = r600_audio_get_pin(rdev);
523 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
524
525 r600_audio_set_dto(encoder, mode->clock);
526
527 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
528 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
529 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
530 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
531 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
532 ~(HDMI0_AUDIO_SAMPLE_SEND |
533 HDMI0_AUDIO_DELAY_EN_MASK |
534 HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
535 HDMI0_60958_CS_UPDATE));
536
537 /* DCE 3.0 uses register that's normally for CRC_CONTROL */
538 acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
539 HDMI0_ACR_PACKET_CONTROL;
540 WREG32_P(acr_ctl + offset,
541 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
542 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
543 ~(HDMI0_ACR_SOURCE |
544 HDMI0_ACR_AUTO_SEND));
545
546 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
547 HDMI0_NULL_SEND | /* send null packets when required */
548 HDMI0_GC_SEND | /* send general control packets */
549 HDMI0_GC_CONT); /* send general control packets every frame */
550
551 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
552 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
553 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
554 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
555 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
556
557 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
558 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
559 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
560 ~(HDMI0_AVI_INFO_LINE_MASK |
561 HDMI0_AUDIO_INFO_LINE_MASK));
562
563 WREG32_AND(HDMI0_GC + offset,
564 ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
565
566 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
567 if (err < 0) {
568 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
569 return;
570 }
571
572 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
573 if (err < 0) {
574 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
575 return;
576 }
577
578 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
579
580 /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
581
582 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
583 ~(HDMI0_GENERIC0_SEND |
584 HDMI0_GENERIC0_CONT |
585 HDMI0_GENERIC0_UPDATE |
586 HDMI0_GENERIC1_SEND |
587 HDMI0_GENERIC1_CONT |
588 HDMI0_GENERIC0_LINE_MASK |
589 HDMI0_GENERIC1_LINE_MASK));
590
591 r600_hdmi_update_ACR(encoder, mode->clock);
592
593 WREG32_P(HDMI0_60958_0 + offset,
594 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
595 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
596 HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
597
598 WREG32_P(HDMI0_60958_1 + offset,
599 HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
600 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
601
602 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
603 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
604 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
605 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
606 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
607
608 /* enable audio after to setting up hw */
609 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
610 }
611
612 /**
613 * r600_hdmi_update_audio_settings - Update audio infoframe
614 *
615 * @encoder: drm encoder
616 *
617 * Gets info about current audio stream and updates audio infoframe.
618 */
r600_hdmi_update_audio_settings(struct drm_encoder * encoder)619 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
620 {
621 struct drm_device *dev = encoder->dev;
622 struct radeon_device *rdev = dev->dev_private;
623 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
624 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
625 struct r600_audio_pin audio = r600_audio_status(rdev);
626 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
627 struct hdmi_audio_infoframe frame;
628 uint32_t offset;
629 uint32_t value;
630 ssize_t err;
631
632 if (!dig->afmt || !dig->afmt->enabled)
633 return;
634 offset = dig->afmt->offset;
635
636 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
637 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
638 audio.channels, audio.rate, audio.bits_per_sample);
639 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
640 (int)audio.status_bits, (int)audio.category_code);
641
642 err = hdmi_audio_infoframe_init(&frame);
643 if (err < 0) {
644 DRM_ERROR("failed to setup audio infoframe\n");
645 return;
646 }
647
648 frame.channels = audio.channels;
649
650 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
651 if (err < 0) {
652 DRM_ERROR("failed to pack audio infoframe\n");
653 return;
654 }
655
656 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
657 if (value & HDMI0_AUDIO_TEST_EN)
658 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
659 value & ~HDMI0_AUDIO_TEST_EN);
660
661 WREG32_OR(HDMI0_CONTROL + offset,
662 HDMI0_ERROR_ACK);
663
664 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
665 ~HDMI0_AUDIO_INFO_SOURCE);
666
667 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
668
669 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
670 HDMI0_AUDIO_INFO_CONT |
671 HDMI0_AUDIO_INFO_UPDATE);
672 }
673
674 /*
675 * enable the HDMI engine
676 */
r600_hdmi_enable(struct drm_encoder * encoder,bool enable)677 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
678 {
679 struct drm_device *dev = encoder->dev;
680 struct radeon_device *rdev = dev->dev_private;
681 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
682 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
683 u32 hdmi = HDMI0_ERROR_ACK;
684
685 if (!dig || !dig->afmt)
686 return;
687
688 /* Silent, r600_hdmi_enable will raise WARN for us */
689 if (enable && dig->afmt->enabled)
690 return;
691 if (!enable && !dig->afmt->enabled)
692 return;
693
694 if (!enable && dig->afmt->pin) {
695 r600_audio_enable(rdev, dig->afmt->pin, 0);
696 dig->afmt->pin = NULL;
697 }
698
699 /* Older chipsets require setting HDMI and routing manually */
700 if (!ASIC_IS_DCE3(rdev)) {
701 if (enable)
702 hdmi |= HDMI0_ENABLE;
703 switch (radeon_encoder->encoder_id) {
704 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
705 if (enable) {
706 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
707 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
708 } else {
709 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
710 }
711 break;
712 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
713 if (enable) {
714 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
715 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
716 } else {
717 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
718 }
719 break;
720 case ENCODER_OBJECT_ID_INTERNAL_DDI:
721 if (enable) {
722 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
723 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
724 } else {
725 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
726 }
727 break;
728 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
729 if (enable)
730 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
731 break;
732 default:
733 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
734 radeon_encoder->encoder_id);
735 break;
736 }
737 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
738 }
739
740 if (rdev->irq.installed) {
741 /* if irq is available use it */
742 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
743 if (enable)
744 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
745 else
746 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
747 }
748
749 dig->afmt->enabled = enable;
750
751 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
752 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
753 }
754
755