1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * Modifications for inclusion into the Linux staging tree are
19 * Copyright(c) 2010 Larry Finger. All rights reserved.
20 *
21 * Contact information:
22 * WLAN FAE <wlanfae@realtek.com>
23 * Larry Finger <Larry.Finger@lwfinger.net>
24 *
25 ******************************************************************************/
26 #define _RTL871X_MP_C_
27
28 #include "osdep_service.h"
29 #include "drv_types.h"
30 #include "rtl871x_mp_phy_regdef.h"
31 #include "rtl8712_cmd.h"
32
_init_mp_priv_(struct mp_priv * pmp_priv)33 static void _init_mp_priv_(struct mp_priv *pmp_priv)
34 {
35 pmp_priv->mode = _LOOPBOOK_MODE_;
36 pmp_priv->curr_ch = 1;
37 pmp_priv->curr_modem = MIXED_PHY;
38 pmp_priv->curr_rateidx = 0;
39 pmp_priv->curr_txpoweridx = 0x14;
40 pmp_priv->antenna_tx = ANTENNA_A;
41 pmp_priv->antenna_rx = ANTENNA_AB;
42 pmp_priv->check_mp_pkt = 0;
43 pmp_priv->tx_pktcount = 0;
44 pmp_priv->rx_pktcount = 0;
45 pmp_priv->rx_crcerrpktcount = 0;
46 }
47
init_mp_priv(struct mp_priv * pmp_priv)48 static int init_mp_priv(struct mp_priv *pmp_priv)
49 {
50 int i, res;
51 struct mp_xmit_frame *pmp_xmitframe;
52
53 _init_mp_priv_(pmp_priv);
54 _init_queue(&pmp_priv->free_mp_xmitqueue);
55 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
56 pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
57 sizeof(struct mp_xmit_frame) + 4,
58 GFP_ATOMIC);
59 if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
60 res = _FAIL;
61 goto _exit_init_mp_priv;
62 }
63 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
64 4 -
65 ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
66 pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
67 for (i = 0; i < NR_MP_XMITFRAME; i++) {
68 INIT_LIST_HEAD(&(pmp_xmitframe->list));
69 list_add_tail(&(pmp_xmitframe->list),
70 &(pmp_priv->free_mp_xmitqueue.queue));
71 pmp_xmitframe->pkt = NULL;
72 pmp_xmitframe->frame_tag = MP_FRAMETAG;
73 pmp_xmitframe->padapter = pmp_priv->papdater;
74 pmp_xmitframe++;
75 }
76 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
77 res = _SUCCESS;
78 _exit_init_mp_priv:
79 return res;
80 }
81
free_mp_priv(struct mp_priv * pmp_priv)82 static int free_mp_priv(struct mp_priv *pmp_priv)
83 {
84 kfree(pmp_priv->pallocated_mp_xmitframe_buf);
85 return 0;
86 }
87
mp871xinit(struct _adapter * padapter)88 void mp871xinit(struct _adapter *padapter)
89 {
90 struct mp_priv *pmppriv = &padapter->mppriv;
91
92 pmppriv->papdater = padapter;
93 init_mp_priv(pmppriv);
94 }
95
mp871xdeinit(struct _adapter * padapter)96 void mp871xdeinit(struct _adapter *padapter)
97 {
98 struct mp_priv *pmppriv = &padapter->mppriv;
99
100 free_mp_priv(pmppriv);
101 }
102
103 /*
104 * Special for bb and rf reg read/write
105 */
fw_iocmd_read(struct _adapter * pAdapter,struct IOCMD_STRUCT iocmd)106 static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
107 {
108 u32 cmd32 = 0, val32 = 0;
109 u8 iocmd_class = iocmd.cmdclass;
110 u16 iocmd_value = iocmd.value;
111 u8 iocmd_idx = iocmd.index;
112
113 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
114 if (r8712_fw_cmd(pAdapter, cmd32))
115 r8712_fw_cmd_data(pAdapter, &val32, 1);
116 else
117 val32 = 0;
118 return val32;
119 }
120
fw_iocmd_write(struct _adapter * pAdapter,struct IOCMD_STRUCT iocmd,u32 value)121 static u8 fw_iocmd_write(struct _adapter *pAdapter,
122 struct IOCMD_STRUCT iocmd, u32 value)
123 {
124 u32 cmd32 = 0;
125 u8 iocmd_class = iocmd.cmdclass;
126 u32 iocmd_value = iocmd.value;
127 u8 iocmd_idx = iocmd.index;
128
129 r8712_fw_cmd_data(pAdapter, &value, 0);
130 msleep(100);
131 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
132 return r8712_fw_cmd(pAdapter, cmd32);
133 }
134
135 /* offset : 0X800~0XFFF */
r8712_bb_reg_read(struct _adapter * pAdapter,u16 offset)136 u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
137 {
138 u8 shift = offset & 0x0003; /* 4 byte access */
139 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
140 u32 bb_val = 0;
141 struct IOCMD_STRUCT iocmd;
142
143 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
144 iocmd.value = bb_addr;
145 iocmd.index = IOCMD_BB_READ_IDX;
146 bb_val = fw_iocmd_read(pAdapter, iocmd);
147 if (shift != 0) {
148 u32 bb_val2 = 0;
149
150 bb_val >>= (shift * 8);
151 iocmd.value += 4;
152 bb_val2 = fw_iocmd_read(pAdapter, iocmd);
153 bb_val2 <<= ((4 - shift) * 8);
154 bb_val |= bb_val2;
155 }
156 return bb_val;
157 }
158
159 /* offset : 0X800~0XFFF */
r8712_bb_reg_write(struct _adapter * pAdapter,u16 offset,u32 value)160 u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
161 {
162 u8 shift = offset & 0x0003; /* 4 byte access */
163 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
164 struct IOCMD_STRUCT iocmd;
165
166 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
167 iocmd.value = bb_addr;
168 iocmd.index = IOCMD_BB_WRITE_IDX;
169 if (shift != 0) {
170 u32 oldValue = 0;
171 u32 newValue = value;
172
173 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
174 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
175 value = oldValue | (newValue << (shift * 8));
176 if (fw_iocmd_write(pAdapter, iocmd, value) == false)
177 return false;
178 iocmd.value += 4;
179 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
180 oldValue &= (0xFFFFFFFF << (shift * 8));
181 value = oldValue | (newValue >> ((4 - shift) * 8));
182 }
183 return fw_iocmd_write(pAdapter, iocmd, value);
184 }
185
186 /* offset : 0x00 ~ 0xFF */
r8712_rf_reg_read(struct _adapter * pAdapter,u8 path,u8 offset)187 u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
188 {
189 u16 rf_addr = (path << 8) | offset;
190 struct IOCMD_STRUCT iocmd;
191
192 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
193 iocmd.value = rf_addr;
194 iocmd.index = IOCMD_RF_READ_IDX;
195 return fw_iocmd_read(pAdapter, iocmd);
196 }
197
r8712_rf_reg_write(struct _adapter * pAdapter,u8 path,u8 offset,u32 value)198 u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
199 {
200 u16 rf_addr = (path << 8) | offset;
201 struct IOCMD_STRUCT iocmd;
202
203 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
204 iocmd.value = rf_addr;
205 iocmd.index = IOCMD_RF_WRIT_IDX;
206 return fw_iocmd_write(pAdapter, iocmd, value);
207 }
208
bitshift(u32 bitmask)209 static u32 bitshift(u32 bitmask)
210 {
211 u32 i;
212
213 for (i = 0; i <= 31; i++)
214 if (((bitmask>>i) & 0x1) == 1)
215 break;
216 return i;
217 }
218
get_bb_reg(struct _adapter * pAdapter,u16 offset,u32 bitmask)219 static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
220 {
221 u32 org_value, bit_shift, new_value;
222
223 org_value = r8712_bb_reg_read(pAdapter, offset);
224 bit_shift = bitshift(bitmask);
225 new_value = (org_value & bitmask) >> bit_shift;
226 return new_value;
227 }
228
set_bb_reg(struct _adapter * pAdapter,u16 offset,u32 bitmask,u32 value)229 static u8 set_bb_reg(struct _adapter *pAdapter,
230 u16 offset,
231 u32 bitmask,
232 u32 value)
233 {
234 u32 org_value, bit_shift, new_value;
235
236 if (bitmask != bMaskDWord) {
237 org_value = r8712_bb_reg_read(pAdapter, offset);
238 bit_shift = bitshift(bitmask);
239 new_value = ((org_value & (~bitmask)) | (value << bit_shift));
240 } else
241 new_value = value;
242 return r8712_bb_reg_write(pAdapter, offset, new_value);
243 }
244
get_rf_reg(struct _adapter * pAdapter,u8 path,u8 offset,u32 bitmask)245 static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
246 u32 bitmask)
247 {
248 u32 org_value, bit_shift, new_value;
249
250 org_value = r8712_rf_reg_read(pAdapter, path, offset);
251 bit_shift = bitshift(bitmask);
252 new_value = (org_value & bitmask) >> bit_shift;
253 return new_value;
254 }
255
set_rf_reg(struct _adapter * pAdapter,u8 path,u8 offset,u32 bitmask,u32 value)256 static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
257 u32 value)
258 {
259 u32 org_value, bit_shift, new_value;
260
261 if (bitmask != bMaskDWord) {
262 org_value = r8712_rf_reg_read(pAdapter, path, offset);
263 bit_shift = bitshift(bitmask);
264 new_value = ((org_value & (~bitmask)) | (value << bit_shift));
265 } else
266 new_value = value;
267 return r8712_rf_reg_write(pAdapter, path, offset, new_value);
268 }
269
270 /*
271 * SetChannel
272 * Description
273 * Use H2C command to change channel,
274 * not only modify rf register, but also other setting need to be done.
275 */
r8712_SetChannel(struct _adapter * pAdapter)276 void r8712_SetChannel(struct _adapter *pAdapter)
277 {
278 struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
279 struct cmd_obj *pcmd = NULL;
280 struct SetChannel_parm *pparm = NULL;
281 u16 code = GEN_CMD_CODE(_SetChannel);
282
283 pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
284 if (pcmd == NULL)
285 return;
286 pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
287 if (pparm == NULL) {
288 kfree(pcmd);
289 return;
290 }
291 pparm->curr_ch = pAdapter->mppriv.curr_ch;
292 init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
293 r8712_enqueue_cmd(pcmdpriv, pcmd);
294 }
295
SetCCKTxPower(struct _adapter * pAdapter,u8 TxPower)296 static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
297 {
298 u16 TxAGC = 0;
299
300 TxAGC = TxPower;
301 set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
302 }
303
SetOFDMTxPower(struct _adapter * pAdapter,u8 TxPower)304 static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
305 {
306 u32 TxAGC = 0;
307
308 TxAGC |= ((TxPower<<24)|(TxPower<<16)|(TxPower<<8)|TxPower);
309 set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
310 set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
311 set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
312 set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
313 set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
314 set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
315 }
316
r8712_SetTxPower(struct _adapter * pAdapter)317 void r8712_SetTxPower(struct _adapter *pAdapter)
318 {
319 u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
320
321 SetCCKTxPower(pAdapter, TxPower);
322 SetOFDMTxPower(pAdapter, TxPower);
323 }
324
r8712_SetTxAGCOffset(struct _adapter * pAdapter,u32 ulTxAGCOffset)325 void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
326 {
327 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
328
329 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
330 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
331 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
332 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
333 set_bb_reg(pAdapter, rFPGA0_TxGainStage,
334 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
335 }
336
r8712_SetDataRate(struct _adapter * pAdapter)337 void r8712_SetDataRate(struct _adapter *pAdapter)
338 {
339 u8 path = RF_PATH_A;
340 u8 offset = RF_SYN_G2;
341 u32 value;
342
343 value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
344 r8712_rf_reg_write(pAdapter, path, offset, value);
345 }
346
r8712_SwitchBandwidth(struct _adapter * pAdapter)347 void r8712_SwitchBandwidth(struct _adapter *pAdapter)
348 {
349 /* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */
350 u8 regBwOpMode = 0;
351 u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
352
353 regBwOpMode = r8712_read8(pAdapter, 0x10250203);
354 if (Bandwidth == HT_CHANNEL_WIDTH_20)
355 regBwOpMode |= BIT(2);
356 else
357 regBwOpMode &= ~(BIT(2));
358 r8712_write8(pAdapter, 0x10250203, regBwOpMode);
359 /* 3 2.Set PHY related register */
360 switch (Bandwidth) {
361 /* 20 MHz channel*/
362 case HT_CHANNEL_WIDTH_20:
363 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
364 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
365 /* Use PHY_REG.txt default value. Do not need to change.
366 * Correct the tx power for CCK rate in 40M.
367 * It is set in Tx descriptor for 8192x series
368 */
369 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
370 break;
371 /* 40 MHz channel*/
372 case HT_CHANNEL_WIDTH_40:
373 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
374 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
375 /* Use PHY_REG.txt default value. Do not need to change.
376 * Correct the tx power for CCK rate in 40M.
377 * Set Control channel to upper or lower. These settings are
378 * required only for 40MHz */
379 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
380 (HAL_PRIME_CHNL_OFFSET_DONT_CARE>>1));
381 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
382 HAL_PRIME_CHNL_OFFSET_DONT_CARE);
383 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
384 break;
385 default:
386 break;
387 }
388
389 /* 3 3.Set RF related register */
390 switch (Bandwidth) {
391 case HT_CHANNEL_WIDTH_20:
392 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
393 BIT(10) | BIT(11), 0x01);
394 break;
395 case HT_CHANNEL_WIDTH_40:
396 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
397 BIT(10) | BIT(11), 0x00);
398 break;
399 default:
400 break;
401 }
402 }
403 /*------------------------------Define structure----------------------------*/
404 struct R_ANTENNA_SELECT_OFDM {
405 u32 r_tx_antenna:4;
406 u32 r_ant_l:4;
407 u32 r_ant_non_ht:4;
408 u32 r_ant_ht1:4;
409 u32 r_ant_ht2:4;
410 u32 r_ant_ht_s1:4;
411 u32 r_ant_non_ht_s1:4;
412 u32 OFDM_TXSC:2;
413 u32 Reserved:2;
414 };
415
416 struct R_ANTENNA_SELECT_CCK {
417 u8 r_cckrx_enable_2:2;
418 u8 r_cckrx_enable:2;
419 u8 r_ccktx_enable:4;
420 };
421
r8712_SwitchAntenna(struct _adapter * pAdapter)422 void r8712_SwitchAntenna(struct _adapter *pAdapter)
423 {
424 u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
425 u8 ofdm_rx_ant_sel_val = 0;
426 u8 cck_ant_select_val = 0;
427 u32 cck_ant_sel_val = 0;
428 struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
429
430 p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
431
432 switch (pAdapter->mppriv.antenna_tx) {
433 case ANTENNA_A:
434 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
435 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
436 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
437 ofdm_tx_en_val = 0x3;
438 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
439 p_cck_txrx->r_ccktx_enable = 0x8;
440 break;
441 case ANTENNA_B:
442 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
443 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
444 ofdm_tx_en_val = 0x3;
445 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
446 p_cck_txrx->r_ccktx_enable = 0x4;
447 break;
448 case ANTENNA_AB: /* For 8192S */
449 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
450 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
451 ofdm_tx_en_val = 0x3;
452 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
453 p_cck_txrx->r_ccktx_enable = 0xC;
454 break;
455 default:
456 break;
457 }
458 /*OFDM Tx*/
459 set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
460 /*OFDM Tx*/
461 set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
462 switch (pAdapter->mppriv.antenna_rx) {
463 case ANTENNA_A:
464 ofdm_rx_ant_sel_val = 0x1; /* A */
465 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
466 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
467 break;
468 case ANTENNA_B:
469 ofdm_rx_ant_sel_val = 0x2; /* B */
470 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
471 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
472 break;
473 case ANTENNA_AB:
474 ofdm_rx_ant_sel_val = 0x3; /* AB */
475 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
476 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
477 break;
478 default:
479 break;
480 }
481 /*OFDM Rx*/
482 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
483 ofdm_rx_ant_sel_val);
484 /*OFDM Rx*/
485 set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
486 ofdm_rx_ant_sel_val);
487
488 cck_ant_sel_val = cck_ant_select_val;
489 /*CCK TxRx*/
490 set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
491 }
492
r8712_SetCrystalCap(struct _adapter * pAdapter)493 void r8712_SetCrystalCap(struct _adapter *pAdapter)
494 {
495 set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap,
496 pAdapter->mppriv.curr_crystalcap);
497 }
498
TriggerRFThermalMeter(struct _adapter * pAdapter)499 static void TriggerRFThermalMeter(struct _adapter *pAdapter)
500 {
501 /* 0x24: RF Reg[6:5] */
502 set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
503 }
504
ReadRFThermalMeter(struct _adapter * pAdapter)505 static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
506 {
507 /* 0x24: RF Reg[4:0] */
508 return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
509 }
510
r8712_GetThermalMeter(struct _adapter * pAdapter,u32 * value)511 void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
512 {
513 TriggerRFThermalMeter(pAdapter);
514 msleep(1000);
515 *value = ReadRFThermalMeter(pAdapter);
516 }
517
r8712_SetSingleCarrierTx(struct _adapter * pAdapter,u8 bStart)518 void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
519 {
520 if (bStart) { /* Start Single Carrier. */
521 /* 1. if OFDM block on? */
522 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
523 /*set OFDM block on*/
524 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
525 /* 2. set CCK test mode off, set to CCK normal mode */
526 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
527 /* 3. turn on scramble setting */
528 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
529 /* 4. Turn On Single Carrier Tx and off the other test modes. */
530 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
531 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
532 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
533 } else { /* Stop Single Carrier.*/
534 /* Turn off all test modes.*/
535 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
536 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
537 bDisable);
538 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
539 msleep(20);
540 /*BB Reset*/
541 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
542 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
543 }
544 }
545
r8712_SetSingleToneTx(struct _adapter * pAdapter,u8 bStart)546 void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
547 {
548 u8 rfPath = pAdapter->mppriv.curr_rfpath;
549
550 switch (pAdapter->mppriv.antenna_tx) {
551 case ANTENNA_B:
552 rfPath = RF_PATH_B;
553 break;
554 case ANTENNA_A:
555 default:
556 rfPath = RF_PATH_A;
557 break;
558 }
559 if (bStart) { /* Start Single Tone.*/
560 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
561 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
562 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
563 0xd4000);
564 msleep(100);
565 /* PAD all on.*/
566 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
567 msleep(100);
568 } else { /* Stop Single Tone.*/
569 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
570 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
571 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
572 0x54000);
573 msleep(100);
574 /* PAD all on.*/
575 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
576 msleep(100);
577 }
578 }
579
r8712_SetCarrierSuppressionTx(struct _adapter * pAdapter,u8 bStart)580 void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
581 {
582 if (bStart) { /* Start Carrier Suppression.*/
583 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
584 /* 1. if CCK block on? */
585 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
586 /*set CCK block on*/
587 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
588 bEnable);
589 }
590 /* Turn Off All Test Mode */
591 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
592 bDisable);
593 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
594 bDisable);
595 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
596 bDisable);
597 /*transmit mode*/
598 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
599 /*turn off scramble setting*/
600 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
601 bDisable);
602 /*Set CCK Tx Test Rate*/
603 /*Set FTxRate to 1Mbps*/
604 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
605 }
606 } else { /* Stop Carrier Suppression. */
607 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
608 /*normal mode*/
609 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
610 /*turn on scramble setting*/
611 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
612 bEnable);
613 /*BB Reset*/
614 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
615 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
616 }
617 }
618 }
619
SetCCKContinuousTx(struct _adapter * pAdapter,u8 bStart)620 static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
621 {
622 u32 cckrate;
623
624 if (bStart) {
625 /* 1. if CCK block on? */
626 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
627 /*set CCK block on*/
628 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
629 }
630 /* Turn Off All Test Mode */
631 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
632 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
633 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
634 /*Set CCK Tx Test Rate*/
635 cckrate = pAdapter->mppriv.curr_rateidx;
636 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
637 /*transmit mode*/
638 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
639 /*turn on scramble setting*/
640 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
641 } else {
642 /*normal mode*/
643 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
644 /*turn on scramble setting*/
645 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
646 /*BB Reset*/
647 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
648 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
649 }
650 } /* mpt_StartCckContTx */
651
SetOFDMContinuousTx(struct _adapter * pAdapter,u8 bStart)652 static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
653 {
654 if (bStart) {
655 /* 1. if OFDM block on? */
656 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
657 /*set OFDM block on*/
658 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
659 }
660 /* 2. set CCK test mode off, set to CCK normal mode*/
661 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
662 /* 3. turn on scramble setting */
663 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
664 /* 4. Turn On Continue Tx and turn off the other test modes.*/
665 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
666 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
667 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
668 } else {
669 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
670 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
671 bDisable);
672 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
673 msleep(20);
674 /*BB Reset*/
675 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
676 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
677 }
678 } /* mpt_StartOfdmContTx */
679
r8712_SetContinuousTx(struct _adapter * pAdapter,u8 bStart)680 void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
681 {
682 /* ADC turn off [bit24-21] adc port0 ~ port1 */
683 if (bStart) {
684 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
685 r8712_bb_reg_read(pAdapter,
686 rRx_Wait_CCCA) & 0xFE1FFFFF);
687 msleep(100);
688 }
689 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
690 SetCCKContinuousTx(pAdapter, bStart);
691 else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
692 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
693 SetOFDMContinuousTx(pAdapter, bStart);
694 /* ADC turn on [bit24-21] adc port0 ~ port1 */
695 if (!bStart)
696 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
697 r8712_bb_reg_read(pAdapter,
698 rRx_Wait_CCCA) | 0x01E00000);
699 }
700
r8712_ResetPhyRxPktCount(struct _adapter * pAdapter)701 void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
702 {
703 u32 i, phyrx_set = 0;
704
705 for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
706 phyrx_set = 0;
707 phyrx_set |= (i << 28); /*select*/
708 phyrx_set |= 0x08000000; /* set counter to zero*/
709 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
710 }
711 }
712
GetPhyRxPktCounts(struct _adapter * pAdapter,u32 selbit)713 static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
714 {
715 /*selection*/
716 u32 phyrx_set = 0, count = 0;
717 u32 SelectBit;
718
719 SelectBit = selbit << 28;
720 phyrx_set |= (SelectBit & 0xF0000000);
721 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
722 /*Read packet count*/
723 count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
724 return count;
725 }
726
r8712_GetPhyRxPktReceived(struct _adapter * pAdapter)727 u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
728 {
729 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
730
731 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
732 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
733 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
734 return OFDM_cnt + CCK_cnt + HT_cnt;
735 }
736
r8712_GetPhyRxPktCRC32Error(struct _adapter * pAdapter)737 u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
738 {
739 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
740
741 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
742 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
743 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
744 return OFDM_cnt + CCK_cnt + HT_cnt;
745 }
746