1 /*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "atom.h"
31 #include <linux/backlight.h>
32
33 extern int atom_debug;
34
35 static u8
radeon_atom_get_backlight_level_from_reg(struct radeon_device * rdev)36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37 {
38 u8 backlight_level;
39 u32 bios_2_scratch;
40
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 else
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48
49 return backlight_level;
50 }
51
52 static void
radeon_atom_set_backlight_level_to_reg(struct radeon_device * rdev,u8 backlight_level)53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 u8 backlight_level)
55 {
56 u32 bios_2_scratch;
57
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 else
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
66
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 else
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71 }
72
73 u8
atombios_get_backlight_level(struct radeon_encoder * radeon_encoder)74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75 {
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
78
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 return 0;
81
82 return radeon_atom_get_backlight_level_from_reg(rdev);
83 }
84
85 void
atombios_set_backlight_level(struct radeon_encoder * radeon_encoder,u8 level)86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
87 {
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 int index;
94
95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 return;
97
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
100 dig = radeon_encoder->enc_priv;
101 dig->backlight_level = level;
102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 } else {
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 }
117 break;
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 else {
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128 }
129 break;
130 default:
131 break;
132 }
133 }
134 }
135
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137
radeon_atom_bl_level(struct backlight_device * bd)138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
139 {
140 u8 level;
141
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
144 level = 0;
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
147 else
148 level = bd->props.brightness;
149
150 return level;
151 }
152
radeon_atom_backlight_update_status(struct backlight_device * bd)153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154 {
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
157
158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
159
160 return 0;
161 }
162
radeon_atom_backlight_get_brightness(struct backlight_device * bd)163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164 {
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
169
170 return radeon_atom_get_backlight_level_from_reg(rdev);
171 }
172
173 static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
176 };
177
radeon_atom_backlight_init(struct radeon_encoder * radeon_encoder,struct drm_connector * drm_connector)178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
180 {
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
187 char bl_name[16];
188
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, drm_connector->kdev,
217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
225 dig = radeon_encoder->enc_priv;
226 dig->bl_dev = bd;
227
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
232 * off again.
233 */
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
238
239 DRM_INFO("radeon atom DIG backlight initialized\n");
240
241 return;
242
243 error:
244 kfree(pdata);
245 return;
246 }
247
radeon_atom_backlight_exit(struct radeon_encoder * radeon_encoder)248 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
249 {
250 struct drm_device *dev = radeon_encoder->base.dev;
251 struct radeon_device *rdev = dev->dev_private;
252 struct backlight_device *bd = NULL;
253 struct radeon_encoder_atom_dig *dig;
254
255 if (!radeon_encoder->enc_priv)
256 return;
257
258 if (!rdev->is_atom_bios)
259 return;
260
261 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
262 return;
263
264 dig = radeon_encoder->enc_priv;
265 bd = dig->bl_dev;
266 dig->bl_dev = NULL;
267
268 if (bd) {
269 struct radeon_legacy_backlight_privdata *pdata;
270
271 pdata = bl_get_data(bd);
272 backlight_device_unregister(bd);
273 kfree(pdata);
274
275 DRM_INFO("radeon atom LVDS backlight unloaded\n");
276 }
277 }
278
279 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
280
radeon_atom_backlight_init(struct radeon_encoder * encoder)281 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
282 {
283 }
284
radeon_atom_backlight_exit(struct radeon_encoder * encoder)285 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
286 {
287 }
288
289 #endif
290
291 /* evil but including atombios.h is much worse */
292 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
293 struct drm_display_mode *mode);
294
radeon_atom_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)295 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
296 const struct drm_display_mode *mode,
297 struct drm_display_mode *adjusted_mode)
298 {
299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 struct drm_device *dev = encoder->dev;
301 struct radeon_device *rdev = dev->dev_private;
302
303 /* set the active encoder to connector routing */
304 radeon_encoder_set_active_device(encoder);
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
306
307 /* hw bug */
308 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
309 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
310 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
311
312 /* vertical FP must be at least 1 */
313 if (mode->crtc_vsync_start == mode->crtc_vdisplay)
314 adjusted_mode->crtc_vsync_start++;
315
316 /* get the native mode for scaling */
317 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
318 radeon_panel_mode_fixup(encoder, adjusted_mode);
319 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
320 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
321 if (tv_dac) {
322 if (tv_dac->tv_std == TV_STD_NTSC ||
323 tv_dac->tv_std == TV_STD_NTSC_J ||
324 tv_dac->tv_std == TV_STD_PAL_M)
325 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
326 else
327 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
328 }
329 } else if (radeon_encoder->rmx_type != RMX_OFF) {
330 radeon_panel_mode_fixup(encoder, adjusted_mode);
331 }
332
333 if (ASIC_IS_DCE3(rdev) &&
334 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
335 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
336 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
337 radeon_dp_set_link_config(connector, adjusted_mode);
338 }
339
340 return true;
341 }
342
343 static void
atombios_dac_setup(struct drm_encoder * encoder,int action)344 atombios_dac_setup(struct drm_encoder *encoder, int action)
345 {
346 struct drm_device *dev = encoder->dev;
347 struct radeon_device *rdev = dev->dev_private;
348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
350 int index = 0;
351 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
352
353 memset(&args, 0, sizeof(args));
354
355 switch (radeon_encoder->encoder_id) {
356 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
358 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
359 break;
360 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
362 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
363 break;
364 }
365
366 args.ucAction = action;
367
368 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
369 args.ucDacStandard = ATOM_DAC1_PS2;
370 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
371 args.ucDacStandard = ATOM_DAC1_CV;
372 else {
373 switch (dac_info->tv_std) {
374 case TV_STD_PAL:
375 case TV_STD_PAL_M:
376 case TV_STD_SCART_PAL:
377 case TV_STD_SECAM:
378 case TV_STD_PAL_CN:
379 args.ucDacStandard = ATOM_DAC1_PAL;
380 break;
381 case TV_STD_NTSC:
382 case TV_STD_NTSC_J:
383 case TV_STD_PAL_60:
384 default:
385 args.ucDacStandard = ATOM_DAC1_NTSC;
386 break;
387 }
388 }
389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
390
391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392
393 }
394
395 static void
atombios_tv_setup(struct drm_encoder * encoder,int action)396 atombios_tv_setup(struct drm_encoder *encoder, int action)
397 {
398 struct drm_device *dev = encoder->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 TV_ENCODER_CONTROL_PS_ALLOCATION args;
402 int index = 0;
403 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
404
405 memset(&args, 0, sizeof(args));
406
407 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
408
409 args.sTVEncoder.ucAction = action;
410
411 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
413 else {
414 switch (dac_info->tv_std) {
415 case TV_STD_NTSC:
416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
417 break;
418 case TV_STD_PAL:
419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
420 break;
421 case TV_STD_PAL_M:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
423 break;
424 case TV_STD_PAL_60:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
426 break;
427 case TV_STD_NTSC_J:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
429 break;
430 case TV_STD_SCART_PAL:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
432 break;
433 case TV_STD_SECAM:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
435 break;
436 case TV_STD_PAL_CN:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
438 break;
439 default:
440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
441 break;
442 }
443 }
444
445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
446
447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
448
449 }
450
radeon_atom_get_bpc(struct drm_encoder * encoder)451 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
452 {
453 int bpc = 8;
454
455 if (encoder->crtc) {
456 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
457 bpc = radeon_crtc->bpc;
458 }
459
460 switch (bpc) {
461 case 0:
462 return PANEL_BPC_UNDEFINE;
463 case 6:
464 return PANEL_6BIT_PER_COLOR;
465 case 8:
466 default:
467 return PANEL_8BIT_PER_COLOR;
468 case 10:
469 return PANEL_10BIT_PER_COLOR;
470 case 12:
471 return PANEL_12BIT_PER_COLOR;
472 case 16:
473 return PANEL_16BIT_PER_COLOR;
474 }
475 }
476
477 union dvo_encoder_control {
478 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
479 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
480 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
481 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
482 };
483
484 void
atombios_dvo_setup(struct drm_encoder * encoder,int action)485 atombios_dvo_setup(struct drm_encoder *encoder, int action)
486 {
487 struct drm_device *dev = encoder->dev;
488 struct radeon_device *rdev = dev->dev_private;
489 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
490 union dvo_encoder_control args;
491 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
492 uint8_t frev, crev;
493
494 memset(&args, 0, sizeof(args));
495
496 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
497 return;
498
499 /* some R4xx chips have the wrong frev */
500 if (rdev->family <= CHIP_RV410)
501 frev = 1;
502
503 switch (frev) {
504 case 1:
505 switch (crev) {
506 case 1:
507 /* R4xx, R5xx */
508 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
509
510 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
511 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
512
513 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
514 break;
515 case 2:
516 /* RS600/690/740 */
517 args.dvo.sDVOEncoder.ucAction = action;
518 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
519 /* DFP1, CRT1, TV1 depending on the type of port */
520 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
521
522 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
523 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
524 break;
525 case 3:
526 /* R6xx */
527 args.dvo_v3.ucAction = action;
528 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
529 args.dvo_v3.ucDVOConfig = 0; /* XXX */
530 break;
531 case 4:
532 /* DCE8 */
533 args.dvo_v4.ucAction = action;
534 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535 args.dvo_v4.ucDVOConfig = 0; /* XXX */
536 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
537 break;
538 default:
539 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
540 break;
541 }
542 break;
543 default:
544 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
545 break;
546 }
547
548 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
549 }
550
551 union lvds_encoder_control {
552 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
553 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
554 };
555
556 void
atombios_digital_setup(struct drm_encoder * encoder,int action)557 atombios_digital_setup(struct drm_encoder *encoder, int action)
558 {
559 struct drm_device *dev = encoder->dev;
560 struct radeon_device *rdev = dev->dev_private;
561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
562 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
563 union lvds_encoder_control args;
564 int index = 0;
565 int hdmi_detected = 0;
566 uint8_t frev, crev;
567
568 if (!dig)
569 return;
570
571 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
572 hdmi_detected = 1;
573
574 memset(&args, 0, sizeof(args));
575
576 switch (radeon_encoder->encoder_id) {
577 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
578 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
579 break;
580 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
582 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
583 break;
584 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
585 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
586 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
587 else
588 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
589 break;
590 }
591
592 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
593 return;
594
595 switch (frev) {
596 case 1:
597 case 2:
598 switch (crev) {
599 case 1:
600 args.v1.ucMisc = 0;
601 args.v1.ucAction = action;
602 if (hdmi_detected)
603 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
604 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
605 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
606 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
607 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
608 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
609 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
610 } else {
611 if (dig->linkb)
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
613 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
614 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
615 /*if (pScrn->rgbBits == 8) */
616 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
617 }
618 break;
619 case 2:
620 case 3:
621 args.v2.ucMisc = 0;
622 args.v2.ucAction = action;
623 if (crev == 3) {
624 if (dig->coherent_mode)
625 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
626 }
627 if (hdmi_detected)
628 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
629 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
630 args.v2.ucTruncate = 0;
631 args.v2.ucSpatial = 0;
632 args.v2.ucTemporal = 0;
633 args.v2.ucFRC = 0;
634 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
635 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
636 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
637 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
638 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
639 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
640 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
641 }
642 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
643 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
644 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
645 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
646 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
647 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
648 }
649 } else {
650 if (dig->linkb)
651 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
652 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
653 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
654 }
655 break;
656 default:
657 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
658 break;
659 }
660 break;
661 default:
662 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
663 break;
664 }
665
666 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
667 }
668
669 int
atombios_get_encoder_mode(struct drm_encoder * encoder)670 atombios_get_encoder_mode(struct drm_encoder *encoder)
671 {
672 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
673 struct drm_connector *connector;
674 struct radeon_connector *radeon_connector;
675 struct radeon_connector_atom_dig *dig_connector;
676
677 /* dp bridges are always DP */
678 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
679 return ATOM_ENCODER_MODE_DP;
680
681 /* DVO is always DVO */
682 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
683 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
684 return ATOM_ENCODER_MODE_DVO;
685
686 connector = radeon_get_connector_for_encoder(encoder);
687 /* if we don't have an active device yet, just use one of
688 * the connectors tied to the encoder.
689 */
690 if (!connector)
691 connector = radeon_get_connector_for_encoder_init(encoder);
692 radeon_connector = to_radeon_connector(connector);
693
694 switch (connector->connector_type) {
695 case DRM_MODE_CONNECTOR_DVII:
696 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
697 if (radeon_audio != 0) {
698 if (radeon_connector->use_digital &&
699 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
700 return ATOM_ENCODER_MODE_HDMI;
701 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
702 (radeon_connector->audio == RADEON_AUDIO_AUTO))
703 return ATOM_ENCODER_MODE_HDMI;
704 else if (radeon_connector->use_digital)
705 return ATOM_ENCODER_MODE_DVI;
706 else
707 return ATOM_ENCODER_MODE_CRT;
708 } else if (radeon_connector->use_digital) {
709 return ATOM_ENCODER_MODE_DVI;
710 } else {
711 return ATOM_ENCODER_MODE_CRT;
712 }
713 break;
714 case DRM_MODE_CONNECTOR_DVID:
715 case DRM_MODE_CONNECTOR_HDMIA:
716 default:
717 if (radeon_audio != 0) {
718 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
719 return ATOM_ENCODER_MODE_HDMI;
720 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
721 (radeon_connector->audio == RADEON_AUDIO_AUTO))
722 return ATOM_ENCODER_MODE_HDMI;
723 else
724 return ATOM_ENCODER_MODE_DVI;
725 } else {
726 return ATOM_ENCODER_MODE_DVI;
727 }
728 break;
729 case DRM_MODE_CONNECTOR_LVDS:
730 return ATOM_ENCODER_MODE_LVDS;
731 break;
732 case DRM_MODE_CONNECTOR_DisplayPort:
733 dig_connector = radeon_connector->con_priv;
734 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
735 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
736 return ATOM_ENCODER_MODE_DP;
737 } else if (radeon_audio != 0) {
738 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
739 return ATOM_ENCODER_MODE_HDMI;
740 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
741 (radeon_connector->audio == RADEON_AUDIO_AUTO))
742 return ATOM_ENCODER_MODE_HDMI;
743 else
744 return ATOM_ENCODER_MODE_DVI;
745 } else {
746 return ATOM_ENCODER_MODE_DVI;
747 }
748 break;
749 case DRM_MODE_CONNECTOR_eDP:
750 return ATOM_ENCODER_MODE_DP;
751 case DRM_MODE_CONNECTOR_DVIA:
752 case DRM_MODE_CONNECTOR_VGA:
753 return ATOM_ENCODER_MODE_CRT;
754 break;
755 case DRM_MODE_CONNECTOR_Composite:
756 case DRM_MODE_CONNECTOR_SVIDEO:
757 case DRM_MODE_CONNECTOR_9PinDIN:
758 /* fix me */
759 return ATOM_ENCODER_MODE_TV;
760 /*return ATOM_ENCODER_MODE_CV;*/
761 break;
762 }
763 }
764
765 /*
766 * DIG Encoder/Transmitter Setup
767 *
768 * DCE 3.0/3.1
769 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
770 * Supports up to 3 digital outputs
771 * - 2 DIG encoder blocks.
772 * DIG1 can drive UNIPHY link A or link B
773 * DIG2 can drive UNIPHY link B or LVTMA
774 *
775 * DCE 3.2
776 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
777 * Supports up to 5 digital outputs
778 * - 2 DIG encoder blocks.
779 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
780 *
781 * DCE 4.0/5.0/6.0
782 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
783 * Supports up to 6 digital outputs
784 * - 6 DIG encoder blocks.
785 * - DIG to PHY mapping is hardcoded
786 * DIG1 drives UNIPHY0 link A, A+B
787 * DIG2 drives UNIPHY0 link B
788 * DIG3 drives UNIPHY1 link A, A+B
789 * DIG4 drives UNIPHY1 link B
790 * DIG5 drives UNIPHY2 link A, A+B
791 * DIG6 drives UNIPHY2 link B
792 *
793 * DCE 4.1
794 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
795 * Supports up to 6 digital outputs
796 * - 2 DIG encoder blocks.
797 * llano
798 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
799 * ontario
800 * DIG1 drives UNIPHY0/1/2 link A
801 * DIG2 drives UNIPHY0/1/2 link B
802 *
803 * Routing
804 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
805 * Examples:
806 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
807 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
808 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
809 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
810 */
811
812 union dig_encoder_control {
813 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
814 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
815 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
816 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
817 };
818
819 void
atombios_dig_encoder_setup(struct drm_encoder * encoder,int action,int panel_mode)820 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
821 {
822 struct drm_device *dev = encoder->dev;
823 struct radeon_device *rdev = dev->dev_private;
824 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
825 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
826 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
827 union dig_encoder_control args;
828 int index = 0;
829 uint8_t frev, crev;
830 int dp_clock = 0;
831 int dp_lane_count = 0;
832 int hpd_id = RADEON_HPD_NONE;
833
834 if (connector) {
835 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
836 struct radeon_connector_atom_dig *dig_connector =
837 radeon_connector->con_priv;
838
839 dp_clock = dig_connector->dp_clock;
840 dp_lane_count = dig_connector->dp_lane_count;
841 hpd_id = radeon_connector->hpd.hpd;
842 }
843
844 /* no dig encoder assigned */
845 if (dig->dig_encoder == -1)
846 return;
847
848 memset(&args, 0, sizeof(args));
849
850 if (ASIC_IS_DCE4(rdev))
851 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
852 else {
853 if (dig->dig_encoder)
854 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
855 else
856 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
857 }
858
859 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
860 return;
861
862 switch (frev) {
863 case 1:
864 switch (crev) {
865 case 1:
866 args.v1.ucAction = action;
867 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
868 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
869 args.v3.ucPanelMode = panel_mode;
870 else
871 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
872
873 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
874 args.v1.ucLaneNum = dp_lane_count;
875 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
876 args.v1.ucLaneNum = 8;
877 else
878 args.v1.ucLaneNum = 4;
879
880 switch (radeon_encoder->encoder_id) {
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
882 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
883 break;
884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
885 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
886 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
887 break;
888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
889 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
890 break;
891 }
892 if (dig->linkb)
893 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
894 else
895 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
896
897 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
899
900 break;
901 case 2:
902 case 3:
903 args.v3.ucAction = action;
904 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
905 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
906 args.v3.ucPanelMode = panel_mode;
907 else
908 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
909
910 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
911 args.v3.ucLaneNum = dp_lane_count;
912 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
913 args.v3.ucLaneNum = 8;
914 else
915 args.v3.ucLaneNum = 4;
916
917 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
918 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
919 args.v3.acConfig.ucDigSel = dig->dig_encoder;
920 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
921 break;
922 case 4:
923 args.v4.ucAction = action;
924 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
925 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
926 args.v4.ucPanelMode = panel_mode;
927 else
928 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
929
930 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
931 args.v4.ucLaneNum = dp_lane_count;
932 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
933 args.v4.ucLaneNum = 8;
934 else
935 args.v4.ucLaneNum = 4;
936
937 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
938 if (dp_clock == 540000)
939 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
940 else if (dp_clock == 324000)
941 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
942 else if (dp_clock == 270000)
943 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
944 else
945 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
946 }
947 args.v4.acConfig.ucDigSel = dig->dig_encoder;
948 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
949 if (hpd_id == RADEON_HPD_NONE)
950 args.v4.ucHPD_ID = 0;
951 else
952 args.v4.ucHPD_ID = hpd_id + 1;
953 break;
954 default:
955 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
956 break;
957 }
958 break;
959 default:
960 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
961 break;
962 }
963
964 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
965
966 }
967
968 union dig_transmitter_control {
969 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
970 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
971 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
972 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
973 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
974 };
975
976 void
atombios_dig_transmitter_setup(struct drm_encoder * encoder,int action,uint8_t lane_num,uint8_t lane_set)977 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
978 {
979 struct drm_device *dev = encoder->dev;
980 struct radeon_device *rdev = dev->dev_private;
981 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
982 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
983 struct drm_connector *connector;
984 union dig_transmitter_control args;
985 int index = 0;
986 uint8_t frev, crev;
987 bool is_dp = false;
988 int pll_id = 0;
989 int dp_clock = 0;
990 int dp_lane_count = 0;
991 int connector_object_id = 0;
992 int igp_lane_info = 0;
993 int dig_encoder = dig->dig_encoder;
994 int hpd_id = RADEON_HPD_NONE;
995
996 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
997 connector = radeon_get_connector_for_encoder_init(encoder);
998 /* just needed to avoid bailing in the encoder check. the encoder
999 * isn't used for init
1000 */
1001 dig_encoder = 0;
1002 } else
1003 connector = radeon_get_connector_for_encoder(encoder);
1004
1005 if (connector) {
1006 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1007 struct radeon_connector_atom_dig *dig_connector =
1008 radeon_connector->con_priv;
1009
1010 hpd_id = radeon_connector->hpd.hpd;
1011 dp_clock = dig_connector->dp_clock;
1012 dp_lane_count = dig_connector->dp_lane_count;
1013 connector_object_id =
1014 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1015 igp_lane_info = dig_connector->igp_lane_info;
1016 }
1017
1018 if (encoder->crtc) {
1019 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1020 pll_id = radeon_crtc->pll_id;
1021 }
1022
1023 /* no dig encoder assigned */
1024 if (dig_encoder == -1)
1025 return;
1026
1027 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1028 is_dp = true;
1029
1030 memset(&args, 0, sizeof(args));
1031
1032 switch (radeon_encoder->encoder_id) {
1033 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1034 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1035 break;
1036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1038 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1039 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1040 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1041 break;
1042 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1043 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1044 break;
1045 }
1046
1047 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1048 return;
1049
1050 switch (frev) {
1051 case 1:
1052 switch (crev) {
1053 case 1:
1054 args.v1.ucAction = action;
1055 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1056 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1057 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1058 args.v1.asMode.ucLaneSel = lane_num;
1059 args.v1.asMode.ucLaneSet = lane_set;
1060 } else {
1061 if (is_dp)
1062 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1063 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1064 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1065 else
1066 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1067 }
1068
1069 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1070
1071 if (dig_encoder)
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1073 else
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1075
1076 if ((rdev->flags & RADEON_IS_IGP) &&
1077 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1078 if (is_dp ||
1079 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1080 if (igp_lane_info & 0x1)
1081 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1082 else if (igp_lane_info & 0x2)
1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1084 else if (igp_lane_info & 0x4)
1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1086 else if (igp_lane_info & 0x8)
1087 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1088 } else {
1089 if (igp_lane_info & 0x3)
1090 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1091 else if (igp_lane_info & 0xc)
1092 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1093 }
1094 }
1095
1096 if (dig->linkb)
1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1098 else
1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1100
1101 if (is_dp)
1102 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1103 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1104 if (dig->coherent_mode)
1105 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1106 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1107 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1108 }
1109 break;
1110 case 2:
1111 args.v2.ucAction = action;
1112 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1113 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1114 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1115 args.v2.asMode.ucLaneSel = lane_num;
1116 args.v2.asMode.ucLaneSet = lane_set;
1117 } else {
1118 if (is_dp)
1119 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1120 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1121 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1122 else
1123 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1124 }
1125
1126 args.v2.acConfig.ucEncoderSel = dig_encoder;
1127 if (dig->linkb)
1128 args.v2.acConfig.ucLinkSel = 1;
1129
1130 switch (radeon_encoder->encoder_id) {
1131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1132 args.v2.acConfig.ucTransmitterSel = 0;
1133 break;
1134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1135 args.v2.acConfig.ucTransmitterSel = 1;
1136 break;
1137 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1138 args.v2.acConfig.ucTransmitterSel = 2;
1139 break;
1140 }
1141
1142 if (is_dp) {
1143 args.v2.acConfig.fCoherentMode = 1;
1144 args.v2.acConfig.fDPConnector = 1;
1145 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1146 if (dig->coherent_mode)
1147 args.v2.acConfig.fCoherentMode = 1;
1148 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1149 args.v2.acConfig.fDualLinkConnector = 1;
1150 }
1151 break;
1152 case 3:
1153 args.v3.ucAction = action;
1154 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1155 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1156 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1157 args.v3.asMode.ucLaneSel = lane_num;
1158 args.v3.asMode.ucLaneSet = lane_set;
1159 } else {
1160 if (is_dp)
1161 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1162 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1163 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1164 else
1165 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1166 }
1167
1168 if (is_dp)
1169 args.v3.ucLaneNum = dp_lane_count;
1170 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1171 args.v3.ucLaneNum = 8;
1172 else
1173 args.v3.ucLaneNum = 4;
1174
1175 if (dig->linkb)
1176 args.v3.acConfig.ucLinkSel = 1;
1177 if (dig_encoder & 1)
1178 args.v3.acConfig.ucEncoderSel = 1;
1179
1180 /* Select the PLL for the PHY
1181 * DP PHY should be clocked from external src if there is
1182 * one.
1183 */
1184 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1185 if (is_dp && rdev->clock.dp_extclk)
1186 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1187 else
1188 args.v3.acConfig.ucRefClkSource = pll_id;
1189
1190 switch (radeon_encoder->encoder_id) {
1191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1192 args.v3.acConfig.ucTransmitterSel = 0;
1193 break;
1194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1195 args.v3.acConfig.ucTransmitterSel = 1;
1196 break;
1197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1198 args.v3.acConfig.ucTransmitterSel = 2;
1199 break;
1200 }
1201
1202 if (is_dp)
1203 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1204 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1205 if (dig->coherent_mode)
1206 args.v3.acConfig.fCoherentMode = 1;
1207 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1208 args.v3.acConfig.fDualLinkConnector = 1;
1209 }
1210 break;
1211 case 4:
1212 args.v4.ucAction = action;
1213 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1214 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1215 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1216 args.v4.asMode.ucLaneSel = lane_num;
1217 args.v4.asMode.ucLaneSet = lane_set;
1218 } else {
1219 if (is_dp)
1220 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1221 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1222 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1223 else
1224 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1225 }
1226
1227 if (is_dp)
1228 args.v4.ucLaneNum = dp_lane_count;
1229 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1230 args.v4.ucLaneNum = 8;
1231 else
1232 args.v4.ucLaneNum = 4;
1233
1234 if (dig->linkb)
1235 args.v4.acConfig.ucLinkSel = 1;
1236 if (dig_encoder & 1)
1237 args.v4.acConfig.ucEncoderSel = 1;
1238
1239 /* Select the PLL for the PHY
1240 * DP PHY should be clocked from external src if there is
1241 * one.
1242 */
1243 /* On DCE5 DCPLL usually generates the DP ref clock */
1244 if (is_dp) {
1245 if (rdev->clock.dp_extclk)
1246 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1247 else
1248 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1249 } else
1250 args.v4.acConfig.ucRefClkSource = pll_id;
1251
1252 switch (radeon_encoder->encoder_id) {
1253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1254 args.v4.acConfig.ucTransmitterSel = 0;
1255 break;
1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1257 args.v4.acConfig.ucTransmitterSel = 1;
1258 break;
1259 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1260 args.v4.acConfig.ucTransmitterSel = 2;
1261 break;
1262 }
1263
1264 if (is_dp)
1265 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1266 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1267 if (dig->coherent_mode)
1268 args.v4.acConfig.fCoherentMode = 1;
1269 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1270 args.v4.acConfig.fDualLinkConnector = 1;
1271 }
1272 break;
1273 case 5:
1274 args.v5.ucAction = action;
1275 if (is_dp)
1276 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1277 else
1278 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1279
1280 switch (radeon_encoder->encoder_id) {
1281 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1282 if (dig->linkb)
1283 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1284 else
1285 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1286 break;
1287 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1288 if (dig->linkb)
1289 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1290 else
1291 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1292 break;
1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1294 if (dig->linkb)
1295 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1296 else
1297 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1298 break;
1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1300 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1301 break;
1302 }
1303 if (is_dp)
1304 args.v5.ucLaneNum = dp_lane_count;
1305 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1306 args.v5.ucLaneNum = 8;
1307 else
1308 args.v5.ucLaneNum = 4;
1309 args.v5.ucConnObjId = connector_object_id;
1310 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1311
1312 if (is_dp && rdev->clock.dp_extclk)
1313 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1314 else
1315 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1316
1317 if (is_dp)
1318 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1319 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1320 if (dig->coherent_mode)
1321 args.v5.asConfig.ucCoherentMode = 1;
1322 }
1323 if (hpd_id == RADEON_HPD_NONE)
1324 args.v5.asConfig.ucHPDSel = 0;
1325 else
1326 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1327 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1328 args.v5.ucDPLaneSet = lane_set;
1329 break;
1330 default:
1331 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1332 break;
1333 }
1334 break;
1335 default:
1336 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1337 break;
1338 }
1339
1340 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1341 }
1342
1343 bool
atombios_set_edp_panel_power(struct drm_connector * connector,int action)1344 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1345 {
1346 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1347 struct drm_device *dev = radeon_connector->base.dev;
1348 struct radeon_device *rdev = dev->dev_private;
1349 union dig_transmitter_control args;
1350 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1351 uint8_t frev, crev;
1352
1353 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1354 goto done;
1355
1356 if (!ASIC_IS_DCE4(rdev))
1357 goto done;
1358
1359 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1360 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1361 goto done;
1362
1363 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1364 goto done;
1365
1366 memset(&args, 0, sizeof(args));
1367
1368 args.v1.ucAction = action;
1369
1370 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1371
1372 /* wait for the panel to power up */
1373 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1374 int i;
1375
1376 for (i = 0; i < 300; i++) {
1377 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1378 return true;
1379 mdelay(1);
1380 }
1381 return false;
1382 }
1383 done:
1384 return true;
1385 }
1386
1387 union external_encoder_control {
1388 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1389 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1390 };
1391
1392 static void
atombios_external_encoder_setup(struct drm_encoder * encoder,struct drm_encoder * ext_encoder,int action)1393 atombios_external_encoder_setup(struct drm_encoder *encoder,
1394 struct drm_encoder *ext_encoder,
1395 int action)
1396 {
1397 struct drm_device *dev = encoder->dev;
1398 struct radeon_device *rdev = dev->dev_private;
1399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1400 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1401 union external_encoder_control args;
1402 struct drm_connector *connector;
1403 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1404 u8 frev, crev;
1405 int dp_clock = 0;
1406 int dp_lane_count = 0;
1407 int connector_object_id = 0;
1408 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1409
1410 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1411 connector = radeon_get_connector_for_encoder_init(encoder);
1412 else
1413 connector = radeon_get_connector_for_encoder(encoder);
1414
1415 if (connector) {
1416 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1417 struct radeon_connector_atom_dig *dig_connector =
1418 radeon_connector->con_priv;
1419
1420 dp_clock = dig_connector->dp_clock;
1421 dp_lane_count = dig_connector->dp_lane_count;
1422 connector_object_id =
1423 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1424 }
1425
1426 memset(&args, 0, sizeof(args));
1427
1428 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1429 return;
1430
1431 switch (frev) {
1432 case 1:
1433 /* no params on frev 1 */
1434 break;
1435 case 2:
1436 switch (crev) {
1437 case 1:
1438 case 2:
1439 args.v1.sDigEncoder.ucAction = action;
1440 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1441 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1442
1443 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1444 if (dp_clock == 270000)
1445 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1446 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1447 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1448 args.v1.sDigEncoder.ucLaneNum = 8;
1449 else
1450 args.v1.sDigEncoder.ucLaneNum = 4;
1451 break;
1452 case 3:
1453 args.v3.sExtEncoder.ucAction = action;
1454 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1455 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1456 else
1457 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1458 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1459
1460 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1461 if (dp_clock == 270000)
1462 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1463 else if (dp_clock == 540000)
1464 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1465 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1466 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1467 args.v3.sExtEncoder.ucLaneNum = 8;
1468 else
1469 args.v3.sExtEncoder.ucLaneNum = 4;
1470 switch (ext_enum) {
1471 case GRAPH_OBJECT_ENUM_ID1:
1472 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1473 break;
1474 case GRAPH_OBJECT_ENUM_ID2:
1475 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1476 break;
1477 case GRAPH_OBJECT_ENUM_ID3:
1478 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1479 break;
1480 }
1481 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1482 break;
1483 default:
1484 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1485 return;
1486 }
1487 break;
1488 default:
1489 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1490 return;
1491 }
1492 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1493 }
1494
1495 static void
atombios_yuv_setup(struct drm_encoder * encoder,bool enable)1496 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1497 {
1498 struct drm_device *dev = encoder->dev;
1499 struct radeon_device *rdev = dev->dev_private;
1500 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1501 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1502 ENABLE_YUV_PS_ALLOCATION args;
1503 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1504 uint32_t temp, reg;
1505
1506 memset(&args, 0, sizeof(args));
1507
1508 if (rdev->family >= CHIP_R600)
1509 reg = R600_BIOS_3_SCRATCH;
1510 else
1511 reg = RADEON_BIOS_3_SCRATCH;
1512
1513 /* XXX: fix up scratch reg handling */
1514 temp = RREG32(reg);
1515 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1516 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1517 (radeon_crtc->crtc_id << 18)));
1518 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1519 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1520 else
1521 WREG32(reg, 0);
1522
1523 if (enable)
1524 args.ucEnable = ATOM_ENABLE;
1525 args.ucCRTC = radeon_crtc->crtc_id;
1526
1527 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1528
1529 WREG32(reg, temp);
1530 }
1531
1532 static void
radeon_atom_encoder_dpms_avivo(struct drm_encoder * encoder,int mode)1533 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1534 {
1535 struct drm_device *dev = encoder->dev;
1536 struct radeon_device *rdev = dev->dev_private;
1537 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1538 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1539 int index = 0;
1540
1541 memset(&args, 0, sizeof(args));
1542
1543 switch (radeon_encoder->encoder_id) {
1544 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1545 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1546 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1547 break;
1548 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1549 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1550 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1551 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1552 break;
1553 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1554 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1555 break;
1556 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1557 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1558 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1559 else
1560 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1561 break;
1562 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1564 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1565 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1566 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1567 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1568 else
1569 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1570 break;
1571 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1572 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1573 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1574 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1575 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1576 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1577 else
1578 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1579 break;
1580 default:
1581 return;
1582 }
1583
1584 switch (mode) {
1585 case DRM_MODE_DPMS_ON:
1586 args.ucAction = ATOM_ENABLE;
1587 /* workaround for DVOOutputControl on some RS690 systems */
1588 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1589 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1590 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1591 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1592 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1593 } else
1594 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1595 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1596 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1597
1598 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1599 }
1600 break;
1601 case DRM_MODE_DPMS_STANDBY:
1602 case DRM_MODE_DPMS_SUSPEND:
1603 case DRM_MODE_DPMS_OFF:
1604 args.ucAction = ATOM_DISABLE;
1605 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1606 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1607 args.ucAction = ATOM_LCD_BLOFF;
1608 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1609 }
1610 break;
1611 }
1612 }
1613
1614 static void
radeon_atom_encoder_dpms_dig(struct drm_encoder * encoder,int mode)1615 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1616 {
1617 struct drm_device *dev = encoder->dev;
1618 struct radeon_device *rdev = dev->dev_private;
1619 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1620 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1621 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1622 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1623 struct radeon_connector *radeon_connector = NULL;
1624 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1625 bool travis_quirk = false;
1626
1627 if (connector) {
1628 radeon_connector = to_radeon_connector(connector);
1629 radeon_dig_connector = radeon_connector->con_priv;
1630 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1631 ENCODER_OBJECT_ID_TRAVIS) &&
1632 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1633 !ASIC_IS_DCE5(rdev))
1634 travis_quirk = true;
1635 }
1636
1637 switch (mode) {
1638 case DRM_MODE_DPMS_ON:
1639 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1640 if (!connector)
1641 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1642 else
1643 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1644
1645 /* setup and enable the encoder */
1646 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1647 atombios_dig_encoder_setup(encoder,
1648 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1649 dig->panel_mode);
1650 if (ext_encoder) {
1651 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1652 atombios_external_encoder_setup(encoder, ext_encoder,
1653 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1654 }
1655 } else if (ASIC_IS_DCE4(rdev)) {
1656 /* setup and enable the encoder */
1657 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1658 } else {
1659 /* setup and enable the encoder and transmitter */
1660 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1661 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1662 }
1663 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1664 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1665 atombios_set_edp_panel_power(connector,
1666 ATOM_TRANSMITTER_ACTION_POWER_ON);
1667 radeon_dig_connector->edp_on = true;
1668 }
1669 }
1670 /* enable the transmitter */
1671 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1672 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1673 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1674 radeon_dp_link_train(encoder, connector);
1675 if (ASIC_IS_DCE4(rdev))
1676 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1677 }
1678 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1679 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1680 if (ext_encoder)
1681 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1682 break;
1683 case DRM_MODE_DPMS_STANDBY:
1684 case DRM_MODE_DPMS_SUSPEND:
1685 case DRM_MODE_DPMS_OFF:
1686 if (ASIC_IS_DCE4(rdev)) {
1687 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1688 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1689 }
1690 if (ext_encoder)
1691 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1692 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1693 atombios_dig_transmitter_setup(encoder,
1694 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1695
1696 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1697 connector && !travis_quirk)
1698 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1699 if (ASIC_IS_DCE4(rdev)) {
1700 /* disable the transmitter */
1701 atombios_dig_transmitter_setup(encoder,
1702 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1703 } else {
1704 /* disable the encoder and transmitter */
1705 atombios_dig_transmitter_setup(encoder,
1706 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1707 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1708 }
1709 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1710 if (travis_quirk)
1711 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1712 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1713 atombios_set_edp_panel_power(connector,
1714 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1715 radeon_dig_connector->edp_on = false;
1716 }
1717 }
1718 break;
1719 }
1720 }
1721
1722 static void
radeon_atom_encoder_dpms(struct drm_encoder * encoder,int mode)1723 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1724 {
1725 struct drm_device *dev = encoder->dev;
1726 struct radeon_device *rdev = dev->dev_private;
1727 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1728
1729 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1730 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1731 radeon_encoder->active_device);
1732 switch (radeon_encoder->encoder_id) {
1733 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1734 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1735 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1736 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1737 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1738 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1739 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1740 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1741 radeon_atom_encoder_dpms_avivo(encoder, mode);
1742 break;
1743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1744 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1745 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1747 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1748 radeon_atom_encoder_dpms_dig(encoder, mode);
1749 break;
1750 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1751 if (ASIC_IS_DCE5(rdev)) {
1752 switch (mode) {
1753 case DRM_MODE_DPMS_ON:
1754 atombios_dvo_setup(encoder, ATOM_ENABLE);
1755 break;
1756 case DRM_MODE_DPMS_STANDBY:
1757 case DRM_MODE_DPMS_SUSPEND:
1758 case DRM_MODE_DPMS_OFF:
1759 atombios_dvo_setup(encoder, ATOM_DISABLE);
1760 break;
1761 }
1762 } else if (ASIC_IS_DCE3(rdev))
1763 radeon_atom_encoder_dpms_dig(encoder, mode);
1764 else
1765 radeon_atom_encoder_dpms_avivo(encoder, mode);
1766 break;
1767 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1768 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1769 if (ASIC_IS_DCE5(rdev)) {
1770 switch (mode) {
1771 case DRM_MODE_DPMS_ON:
1772 atombios_dac_setup(encoder, ATOM_ENABLE);
1773 break;
1774 case DRM_MODE_DPMS_STANDBY:
1775 case DRM_MODE_DPMS_SUSPEND:
1776 case DRM_MODE_DPMS_OFF:
1777 atombios_dac_setup(encoder, ATOM_DISABLE);
1778 break;
1779 }
1780 } else
1781 radeon_atom_encoder_dpms_avivo(encoder, mode);
1782 break;
1783 default:
1784 return;
1785 }
1786
1787 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1788
1789 }
1790
1791 union crtc_source_param {
1792 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1793 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1794 };
1795
1796 static void
atombios_set_encoder_crtc_source(struct drm_encoder * encoder)1797 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1798 {
1799 struct drm_device *dev = encoder->dev;
1800 struct radeon_device *rdev = dev->dev_private;
1801 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1802 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1803 union crtc_source_param args;
1804 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1805 uint8_t frev, crev;
1806 struct radeon_encoder_atom_dig *dig;
1807
1808 memset(&args, 0, sizeof(args));
1809
1810 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1811 return;
1812
1813 switch (frev) {
1814 case 1:
1815 switch (crev) {
1816 case 1:
1817 default:
1818 if (ASIC_IS_AVIVO(rdev))
1819 args.v1.ucCRTC = radeon_crtc->crtc_id;
1820 else {
1821 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1822 args.v1.ucCRTC = radeon_crtc->crtc_id;
1823 } else {
1824 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1825 }
1826 }
1827 switch (radeon_encoder->encoder_id) {
1828 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1829 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1830 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1831 break;
1832 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1833 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1834 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1835 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1836 else
1837 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1838 break;
1839 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1840 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1841 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1842 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1843 break;
1844 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1845 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1846 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1847 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1848 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1849 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1850 else
1851 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1852 break;
1853 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1855 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1856 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1857 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1858 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1859 else
1860 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1861 break;
1862 }
1863 break;
1864 case 2:
1865 args.v2.ucCRTC = radeon_crtc->crtc_id;
1866 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1867 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1868
1869 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1870 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1871 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1872 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1873 else
1874 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1875 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1876 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1877 } else {
1878 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1879 }
1880 switch (radeon_encoder->encoder_id) {
1881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1882 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1885 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1886 dig = radeon_encoder->enc_priv;
1887 switch (dig->dig_encoder) {
1888 case 0:
1889 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1890 break;
1891 case 1:
1892 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1893 break;
1894 case 2:
1895 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1896 break;
1897 case 3:
1898 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1899 break;
1900 case 4:
1901 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1902 break;
1903 case 5:
1904 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1905 break;
1906 case 6:
1907 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1908 break;
1909 }
1910 break;
1911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1912 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1913 break;
1914 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1915 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1916 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1917 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1918 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1919 else
1920 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1921 break;
1922 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1923 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1924 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1925 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1926 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1927 else
1928 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1929 break;
1930 }
1931 break;
1932 }
1933 break;
1934 default:
1935 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1936 return;
1937 }
1938
1939 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1940
1941 /* update scratch regs with new routing */
1942 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1943 }
1944
1945 static void
atombios_apply_encoder_quirks(struct drm_encoder * encoder,struct drm_display_mode * mode)1946 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1947 struct drm_display_mode *mode)
1948 {
1949 struct drm_device *dev = encoder->dev;
1950 struct radeon_device *rdev = dev->dev_private;
1951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1952 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1953
1954 /* Funky macbooks */
1955 if ((dev->pdev->device == 0x71C5) &&
1956 (dev->pdev->subsystem_vendor == 0x106b) &&
1957 (dev->pdev->subsystem_device == 0x0080)) {
1958 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1959 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1960
1961 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1962 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1963
1964 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1965 }
1966 }
1967
1968 /* set scaler clears this on some chips */
1969 if (ASIC_IS_AVIVO(rdev) &&
1970 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1971 if (ASIC_IS_DCE8(rdev)) {
1972 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1973 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1974 CIK_INTERLEAVE_EN);
1975 else
1976 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1977 } else if (ASIC_IS_DCE4(rdev)) {
1978 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1979 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1980 EVERGREEN_INTERLEAVE_EN);
1981 else
1982 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1983 } else {
1984 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1985 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1986 AVIVO_D1MODE_INTERLEAVE_EN);
1987 else
1988 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1989 }
1990 }
1991 }
1992
radeon_atom_pick_dig_encoder(struct drm_encoder * encoder)1993 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1994 {
1995 struct drm_device *dev = encoder->dev;
1996 struct radeon_device *rdev = dev->dev_private;
1997 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1998 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1999 struct drm_encoder *test_encoder;
2000 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2001 uint32_t dig_enc_in_use = 0;
2002
2003 if (ASIC_IS_DCE6(rdev)) {
2004 /* DCE6 */
2005 switch (radeon_encoder->encoder_id) {
2006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2007 if (dig->linkb)
2008 return 1;
2009 else
2010 return 0;
2011 break;
2012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2013 if (dig->linkb)
2014 return 3;
2015 else
2016 return 2;
2017 break;
2018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2019 if (dig->linkb)
2020 return 5;
2021 else
2022 return 4;
2023 break;
2024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2025 return 6;
2026 break;
2027 }
2028 } else if (ASIC_IS_DCE4(rdev)) {
2029 /* DCE4/5 */
2030 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2031 /* ontario follows DCE4 */
2032 if (rdev->family == CHIP_PALM) {
2033 if (dig->linkb)
2034 return 1;
2035 else
2036 return 0;
2037 } else
2038 /* llano follows DCE3.2 */
2039 return radeon_crtc->crtc_id;
2040 } else {
2041 switch (radeon_encoder->encoder_id) {
2042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2043 if (dig->linkb)
2044 return 1;
2045 else
2046 return 0;
2047 break;
2048 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2049 if (dig->linkb)
2050 return 3;
2051 else
2052 return 2;
2053 break;
2054 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2055 if (dig->linkb)
2056 return 5;
2057 else
2058 return 4;
2059 break;
2060 }
2061 }
2062 }
2063
2064 /* on DCE32 and encoder can driver any block so just crtc id */
2065 if (ASIC_IS_DCE32(rdev)) {
2066 return radeon_crtc->crtc_id;
2067 }
2068
2069 /* on DCE3 - LVTMA can only be driven by DIGB */
2070 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2071 struct radeon_encoder *radeon_test_encoder;
2072
2073 if (encoder == test_encoder)
2074 continue;
2075
2076 if (!radeon_encoder_is_digital(test_encoder))
2077 continue;
2078
2079 radeon_test_encoder = to_radeon_encoder(test_encoder);
2080 dig = radeon_test_encoder->enc_priv;
2081
2082 if (dig->dig_encoder >= 0)
2083 dig_enc_in_use |= (1 << dig->dig_encoder);
2084 }
2085
2086 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2087 if (dig_enc_in_use & 0x2)
2088 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2089 return 1;
2090 }
2091 if (!(dig_enc_in_use & 1))
2092 return 0;
2093 return 1;
2094 }
2095
2096 /* This only needs to be called once at startup */
2097 void
radeon_atom_encoder_init(struct radeon_device * rdev)2098 radeon_atom_encoder_init(struct radeon_device *rdev)
2099 {
2100 struct drm_device *dev = rdev->ddev;
2101 struct drm_encoder *encoder;
2102
2103 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2105 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2106
2107 switch (radeon_encoder->encoder_id) {
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2112 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2113 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2114 break;
2115 default:
2116 break;
2117 }
2118
2119 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2120 atombios_external_encoder_setup(encoder, ext_encoder,
2121 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2122 }
2123 }
2124
2125 static void
radeon_atom_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2126 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2127 struct drm_display_mode *mode,
2128 struct drm_display_mode *adjusted_mode)
2129 {
2130 struct drm_device *dev = encoder->dev;
2131 struct radeon_device *rdev = dev->dev_private;
2132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2133
2134 radeon_encoder->pixel_clock = adjusted_mode->clock;
2135
2136 /* need to call this here rather than in prepare() since we need some crtc info */
2137 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2138
2139 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2140 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2141 atombios_yuv_setup(encoder, true);
2142 else
2143 atombios_yuv_setup(encoder, false);
2144 }
2145
2146 switch (radeon_encoder->encoder_id) {
2147 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2148 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2149 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2150 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2151 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2152 break;
2153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2155 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2156 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2158 /* handled in dpms */
2159 break;
2160 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2161 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2162 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2163 atombios_dvo_setup(encoder, ATOM_ENABLE);
2164 break;
2165 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2166 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2167 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2169 atombios_dac_setup(encoder, ATOM_ENABLE);
2170 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2171 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2172 atombios_tv_setup(encoder, ATOM_ENABLE);
2173 else
2174 atombios_tv_setup(encoder, ATOM_DISABLE);
2175 }
2176 break;
2177 }
2178
2179 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2180
2181 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2182 if (rdev->asic->display.hdmi_enable)
2183 radeon_hdmi_enable(rdev, encoder, true);
2184 if (rdev->asic->display.hdmi_setmode)
2185 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2186 }
2187 }
2188
2189 static bool
atombios_dac_load_detect(struct drm_encoder * encoder,struct drm_connector * connector)2190 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2191 {
2192 struct drm_device *dev = encoder->dev;
2193 struct radeon_device *rdev = dev->dev_private;
2194 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2195 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2196
2197 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2198 ATOM_DEVICE_CV_SUPPORT |
2199 ATOM_DEVICE_CRT_SUPPORT)) {
2200 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2201 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2202 uint8_t frev, crev;
2203
2204 memset(&args, 0, sizeof(args));
2205
2206 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2207 return false;
2208
2209 args.sDacload.ucMisc = 0;
2210
2211 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2212 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2213 args.sDacload.ucDacType = ATOM_DAC_A;
2214 else
2215 args.sDacload.ucDacType = ATOM_DAC_B;
2216
2217 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2218 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2219 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2220 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2221 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2222 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2223 if (crev >= 3)
2224 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2225 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2226 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2227 if (crev >= 3)
2228 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2229 }
2230
2231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2232
2233 return true;
2234 } else
2235 return false;
2236 }
2237
2238 static enum drm_connector_status
radeon_atom_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)2239 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2240 {
2241 struct drm_device *dev = encoder->dev;
2242 struct radeon_device *rdev = dev->dev_private;
2243 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2244 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2245 uint32_t bios_0_scratch;
2246
2247 if (!atombios_dac_load_detect(encoder, connector)) {
2248 DRM_DEBUG_KMS("detect returned false \n");
2249 return connector_status_unknown;
2250 }
2251
2252 if (rdev->family >= CHIP_R600)
2253 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2254 else
2255 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2256
2257 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2258 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2259 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2260 return connector_status_connected;
2261 }
2262 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2263 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2264 return connector_status_connected;
2265 }
2266 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2267 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2268 return connector_status_connected;
2269 }
2270 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2271 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2272 return connector_status_connected; /* CTV */
2273 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2274 return connector_status_connected; /* STV */
2275 }
2276 return connector_status_disconnected;
2277 }
2278
2279 static enum drm_connector_status
radeon_atom_dig_detect(struct drm_encoder * encoder,struct drm_connector * connector)2280 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2281 {
2282 struct drm_device *dev = encoder->dev;
2283 struct radeon_device *rdev = dev->dev_private;
2284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2285 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2286 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2287 u32 bios_0_scratch;
2288
2289 if (!ASIC_IS_DCE4(rdev))
2290 return connector_status_unknown;
2291
2292 if (!ext_encoder)
2293 return connector_status_unknown;
2294
2295 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2296 return connector_status_unknown;
2297
2298 /* load detect on the dp bridge */
2299 atombios_external_encoder_setup(encoder, ext_encoder,
2300 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2301
2302 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2303
2304 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2305 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2306 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2307 return connector_status_connected;
2308 }
2309 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2310 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2311 return connector_status_connected;
2312 }
2313 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2314 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2315 return connector_status_connected;
2316 }
2317 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2318 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2319 return connector_status_connected; /* CTV */
2320 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2321 return connector_status_connected; /* STV */
2322 }
2323 return connector_status_disconnected;
2324 }
2325
2326 void
radeon_atom_ext_encoder_setup_ddc(struct drm_encoder * encoder)2327 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2328 {
2329 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2330
2331 if (ext_encoder)
2332 /* ddc_setup on the dp bridge */
2333 atombios_external_encoder_setup(encoder, ext_encoder,
2334 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2335
2336 }
2337
radeon_atom_encoder_prepare(struct drm_encoder * encoder)2338 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2339 {
2340 struct radeon_device *rdev = encoder->dev->dev_private;
2341 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2343
2344 if ((radeon_encoder->active_device &
2345 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2346 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2347 ENCODER_OBJECT_ID_NONE)) {
2348 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2349 if (dig) {
2350 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2351 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2352 if (rdev->family >= CHIP_R600)
2353 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2354 else
2355 /* RS600/690/740 have only 1 afmt block */
2356 dig->afmt = rdev->mode_info.afmt[0];
2357 }
2358 }
2359 }
2360
2361 radeon_atom_output_lock(encoder, true);
2362
2363 if (connector) {
2364 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2365
2366 /* select the clock/data port if it uses a router */
2367 if (radeon_connector->router.cd_valid)
2368 radeon_router_select_cd_port(radeon_connector);
2369
2370 /* turn eDP panel on for mode set */
2371 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2372 atombios_set_edp_panel_power(connector,
2373 ATOM_TRANSMITTER_ACTION_POWER_ON);
2374 }
2375
2376 /* this is needed for the pll/ss setup to work correctly in some cases */
2377 atombios_set_encoder_crtc_source(encoder);
2378 /* set up the FMT blocks */
2379 if (ASIC_IS_DCE8(rdev))
2380 dce8_program_fmt(encoder);
2381 else if (ASIC_IS_DCE4(rdev))
2382 dce4_program_fmt(encoder);
2383 else if (ASIC_IS_DCE3(rdev))
2384 dce3_program_fmt(encoder);
2385 else if (ASIC_IS_AVIVO(rdev))
2386 avivo_program_fmt(encoder);
2387 }
2388
radeon_atom_encoder_commit(struct drm_encoder * encoder)2389 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2390 {
2391 /* need to call this here as we need the crtc set up */
2392 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2393 radeon_atom_output_lock(encoder, false);
2394 }
2395
radeon_atom_encoder_disable(struct drm_encoder * encoder)2396 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2397 {
2398 struct drm_device *dev = encoder->dev;
2399 struct radeon_device *rdev = dev->dev_private;
2400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2401 struct radeon_encoder_atom_dig *dig;
2402
2403 /* check for pre-DCE3 cards with shared encoders;
2404 * can't really use the links individually, so don't disable
2405 * the encoder if it's in use by another connector
2406 */
2407 if (!ASIC_IS_DCE3(rdev)) {
2408 struct drm_encoder *other_encoder;
2409 struct radeon_encoder *other_radeon_encoder;
2410
2411 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2412 other_radeon_encoder = to_radeon_encoder(other_encoder);
2413 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2414 drm_helper_encoder_in_use(other_encoder))
2415 goto disable_done;
2416 }
2417 }
2418
2419 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2420
2421 switch (radeon_encoder->encoder_id) {
2422 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2423 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2424 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2425 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2426 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2427 break;
2428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2429 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2430 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2431 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2432 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2433 /* handled in dpms */
2434 break;
2435 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2436 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2437 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2438 atombios_dvo_setup(encoder, ATOM_DISABLE);
2439 break;
2440 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2441 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2442 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2443 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2444 atombios_dac_setup(encoder, ATOM_DISABLE);
2445 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2446 atombios_tv_setup(encoder, ATOM_DISABLE);
2447 break;
2448 }
2449
2450 disable_done:
2451 if (radeon_encoder_is_digital(encoder)) {
2452 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2453 if (rdev->asic->display.hdmi_enable)
2454 radeon_hdmi_enable(rdev, encoder, false);
2455 }
2456 dig = radeon_encoder->enc_priv;
2457 dig->dig_encoder = -1;
2458 }
2459 radeon_encoder->active_device = 0;
2460 }
2461
2462 /* these are handled by the primary encoders */
radeon_atom_ext_prepare(struct drm_encoder * encoder)2463 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2464 {
2465
2466 }
2467
radeon_atom_ext_commit(struct drm_encoder * encoder)2468 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2469 {
2470
2471 }
2472
2473 static void
radeon_atom_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2474 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2475 struct drm_display_mode *mode,
2476 struct drm_display_mode *adjusted_mode)
2477 {
2478
2479 }
2480
radeon_atom_ext_disable(struct drm_encoder * encoder)2481 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2482 {
2483
2484 }
2485
2486 static void
radeon_atom_ext_dpms(struct drm_encoder * encoder,int mode)2487 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2488 {
2489
2490 }
2491
radeon_atom_ext_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2492 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2493 const struct drm_display_mode *mode,
2494 struct drm_display_mode *adjusted_mode)
2495 {
2496 return true;
2497 }
2498
2499 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2500 .dpms = radeon_atom_ext_dpms,
2501 .mode_fixup = radeon_atom_ext_mode_fixup,
2502 .prepare = radeon_atom_ext_prepare,
2503 .mode_set = radeon_atom_ext_mode_set,
2504 .commit = radeon_atom_ext_commit,
2505 .disable = radeon_atom_ext_disable,
2506 /* no detect for TMDS/LVDS yet */
2507 };
2508
2509 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2510 .dpms = radeon_atom_encoder_dpms,
2511 .mode_fixup = radeon_atom_mode_fixup,
2512 .prepare = radeon_atom_encoder_prepare,
2513 .mode_set = radeon_atom_encoder_mode_set,
2514 .commit = radeon_atom_encoder_commit,
2515 .disable = radeon_atom_encoder_disable,
2516 .detect = radeon_atom_dig_detect,
2517 };
2518
2519 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2520 .dpms = radeon_atom_encoder_dpms,
2521 .mode_fixup = radeon_atom_mode_fixup,
2522 .prepare = radeon_atom_encoder_prepare,
2523 .mode_set = radeon_atom_encoder_mode_set,
2524 .commit = radeon_atom_encoder_commit,
2525 .detect = radeon_atom_dac_detect,
2526 };
2527
radeon_enc_destroy(struct drm_encoder * encoder)2528 void radeon_enc_destroy(struct drm_encoder *encoder)
2529 {
2530 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2531 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2532 radeon_atom_backlight_exit(radeon_encoder);
2533 kfree(radeon_encoder->enc_priv);
2534 drm_encoder_cleanup(encoder);
2535 kfree(radeon_encoder);
2536 }
2537
2538 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2539 .destroy = radeon_enc_destroy,
2540 };
2541
2542 static struct radeon_encoder_atom_dac *
radeon_atombios_set_dac_info(struct radeon_encoder * radeon_encoder)2543 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2544 {
2545 struct drm_device *dev = radeon_encoder->base.dev;
2546 struct radeon_device *rdev = dev->dev_private;
2547 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2548
2549 if (!dac)
2550 return NULL;
2551
2552 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2553 return dac;
2554 }
2555
2556 static struct radeon_encoder_atom_dig *
radeon_atombios_set_dig_info(struct radeon_encoder * radeon_encoder)2557 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2558 {
2559 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2560 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2561
2562 if (!dig)
2563 return NULL;
2564
2565 /* coherent mode by default */
2566 dig->coherent_mode = true;
2567 dig->dig_encoder = -1;
2568
2569 if (encoder_enum == 2)
2570 dig->linkb = true;
2571 else
2572 dig->linkb = false;
2573
2574 return dig;
2575 }
2576
2577 void
radeon_add_atom_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)2578 radeon_add_atom_encoder(struct drm_device *dev,
2579 uint32_t encoder_enum,
2580 uint32_t supported_device,
2581 u16 caps)
2582 {
2583 struct radeon_device *rdev = dev->dev_private;
2584 struct drm_encoder *encoder;
2585 struct radeon_encoder *radeon_encoder;
2586
2587 /* see if we already added it */
2588 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2589 radeon_encoder = to_radeon_encoder(encoder);
2590 if (radeon_encoder->encoder_enum == encoder_enum) {
2591 radeon_encoder->devices |= supported_device;
2592 return;
2593 }
2594
2595 }
2596
2597 /* add a new one */
2598 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2599 if (!radeon_encoder)
2600 return;
2601
2602 encoder = &radeon_encoder->base;
2603 switch (rdev->num_crtc) {
2604 case 1:
2605 encoder->possible_crtcs = 0x1;
2606 break;
2607 case 2:
2608 default:
2609 encoder->possible_crtcs = 0x3;
2610 break;
2611 case 4:
2612 encoder->possible_crtcs = 0xf;
2613 break;
2614 case 6:
2615 encoder->possible_crtcs = 0x3f;
2616 break;
2617 }
2618
2619 radeon_encoder->enc_priv = NULL;
2620
2621 radeon_encoder->encoder_enum = encoder_enum;
2622 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2623 radeon_encoder->devices = supported_device;
2624 radeon_encoder->rmx_type = RMX_OFF;
2625 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2626 radeon_encoder->is_ext_encoder = false;
2627 radeon_encoder->caps = caps;
2628
2629 switch (radeon_encoder->encoder_id) {
2630 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2631 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2632 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2633 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2634 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2635 radeon_encoder->rmx_type = RMX_FULL;
2636 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2637 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2638 } else {
2639 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2640 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2641 }
2642 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2643 break;
2644 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2645 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2646 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2647 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2648 break;
2649 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2650 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2653 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2654 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2655 break;
2656 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2658 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2659 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2660 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2664 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2665 radeon_encoder->rmx_type = RMX_FULL;
2666 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2667 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2668 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2669 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2670 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2671 } else {
2672 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2673 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2674 }
2675 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2676 break;
2677 case ENCODER_OBJECT_ID_SI170B:
2678 case ENCODER_OBJECT_ID_CH7303:
2679 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2680 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2681 case ENCODER_OBJECT_ID_TITFP513:
2682 case ENCODER_OBJECT_ID_VT1623:
2683 case ENCODER_OBJECT_ID_HDMI_SI1930:
2684 case ENCODER_OBJECT_ID_TRAVIS:
2685 case ENCODER_OBJECT_ID_NUTMEG:
2686 /* these are handled by the primary encoders */
2687 radeon_encoder->is_ext_encoder = true;
2688 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2689 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2690 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2691 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2692 else
2693 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2694 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2695 break;
2696 }
2697 }
2698