1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23 #include <drm/drmP.h>
24 #include "radeon.h"
25 #include "avivod.h"
26 #include "atom.h"
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
30
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34
35 static const char *radeon_pm_state_type_name[5] = {
36 "",
37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41 };
42
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
radeon_pm_get_type_index(struct radeon_device * rdev,enum radeon_pm_state_type ps_type,int instance)50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53 {
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66 }
67
radeon_pm_acpi_event_handler(struct radeon_device * rdev)68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
69 {
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->family == CHIP_ARUBA) {
77 if (rdev->asic->dpm.enable_bapm)
78 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
79 }
80 mutex_unlock(&rdev->pm.mutex);
81 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
82 if (rdev->pm.profile == PM_PROFILE_AUTO) {
83 mutex_lock(&rdev->pm.mutex);
84 radeon_pm_update_profile(rdev);
85 radeon_pm_set_clocks(rdev);
86 mutex_unlock(&rdev->pm.mutex);
87 }
88 }
89 }
90
radeon_pm_update_profile(struct radeon_device * rdev)91 static void radeon_pm_update_profile(struct radeon_device *rdev)
92 {
93 switch (rdev->pm.profile) {
94 case PM_PROFILE_DEFAULT:
95 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
96 break;
97 case PM_PROFILE_AUTO:
98 if (power_supply_is_system_supplied() > 0) {
99 if (rdev->pm.active_crtc_count > 1)
100 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
101 else
102 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
103 } else {
104 if (rdev->pm.active_crtc_count > 1)
105 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
106 else
107 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
108 }
109 break;
110 case PM_PROFILE_LOW:
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
113 else
114 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
115 break;
116 case PM_PROFILE_MID:
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
119 else
120 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
121 break;
122 case PM_PROFILE_HIGH:
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
125 else
126 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
127 break;
128 }
129
130 if (rdev->pm.active_crtc_count == 0) {
131 rdev->pm.requested_power_state_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
133 rdev->pm.requested_clock_mode_index =
134 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
135 } else {
136 rdev->pm.requested_power_state_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
138 rdev->pm.requested_clock_mode_index =
139 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
140 }
141 }
142
radeon_unmap_vram_bos(struct radeon_device * rdev)143 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
144 {
145 struct radeon_bo *bo, *n;
146
147 if (list_empty(&rdev->gem.objects))
148 return;
149
150 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
151 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
152 ttm_bo_unmap_virtual(&bo->tbo);
153 }
154 }
155
radeon_sync_with_vblank(struct radeon_device * rdev)156 static void radeon_sync_with_vblank(struct radeon_device *rdev)
157 {
158 if (rdev->pm.active_crtcs) {
159 rdev->pm.vblank_sync = false;
160 wait_event_timeout(
161 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
162 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
163 }
164 }
165
radeon_set_power_state(struct radeon_device * rdev)166 static void radeon_set_power_state(struct radeon_device *rdev)
167 {
168 u32 sclk, mclk;
169 bool misc_after = false;
170
171 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
172 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
173 return;
174
175 if (radeon_gui_idle(rdev)) {
176 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
177 clock_info[rdev->pm.requested_clock_mode_index].sclk;
178 if (sclk > rdev->pm.default_sclk)
179 sclk = rdev->pm.default_sclk;
180
181 /* starting with BTC, there is one state that is used for both
182 * MH and SH. Difference is that we always use the high clock index for
183 * mclk and vddci.
184 */
185 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
186 (rdev->family >= CHIP_BARTS) &&
187 rdev->pm.active_crtc_count &&
188 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
189 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
190 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
191 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
192 else
193 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
194 clock_info[rdev->pm.requested_clock_mode_index].mclk;
195
196 if (mclk > rdev->pm.default_mclk)
197 mclk = rdev->pm.default_mclk;
198
199 /* upvolt before raising clocks, downvolt after lowering clocks */
200 if (sclk < rdev->pm.current_sclk)
201 misc_after = true;
202
203 radeon_sync_with_vblank(rdev);
204
205 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
206 if (!radeon_pm_in_vbl(rdev))
207 return;
208 }
209
210 radeon_pm_prepare(rdev);
211
212 if (!misc_after)
213 /* voltage, pcie lanes, etc.*/
214 radeon_pm_misc(rdev);
215
216 /* set engine clock */
217 if (sclk != rdev->pm.current_sclk) {
218 radeon_pm_debug_check_in_vbl(rdev, false);
219 radeon_set_engine_clock(rdev, sclk);
220 radeon_pm_debug_check_in_vbl(rdev, true);
221 rdev->pm.current_sclk = sclk;
222 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
223 }
224
225 /* set memory clock */
226 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
227 radeon_pm_debug_check_in_vbl(rdev, false);
228 radeon_set_memory_clock(rdev, mclk);
229 radeon_pm_debug_check_in_vbl(rdev, true);
230 rdev->pm.current_mclk = mclk;
231 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
232 }
233
234 if (misc_after)
235 /* voltage, pcie lanes, etc.*/
236 radeon_pm_misc(rdev);
237
238 radeon_pm_finish(rdev);
239
240 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
241 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
242 } else
243 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 }
245
radeon_pm_set_clocks(struct radeon_device * rdev)246 static void radeon_pm_set_clocks(struct radeon_device *rdev)
247 {
248 int i, r;
249
250 /* no need to take locks, etc. if nothing's going to change */
251 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
252 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
253 return;
254
255 mutex_lock(&rdev->ddev->struct_mutex);
256 down_write(&rdev->pm.mclk_lock);
257 mutex_lock(&rdev->ring_lock);
258
259 /* wait for the rings to drain */
260 for (i = 0; i < RADEON_NUM_RINGS; i++) {
261 struct radeon_ring *ring = &rdev->ring[i];
262 if (!ring->ready) {
263 continue;
264 }
265 r = radeon_fence_wait_empty(rdev, i);
266 if (r) {
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev->ring_lock);
269 up_write(&rdev->pm.mclk_lock);
270 mutex_unlock(&rdev->ddev->struct_mutex);
271 return;
272 }
273 }
274
275 radeon_unmap_vram_bos(rdev);
276
277 if (rdev->irq.installed) {
278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.active_crtcs & (1 << i)) {
280 rdev->pm.req_vblank |= (1 << i);
281 drm_vblank_get(rdev->ddev, i);
282 }
283 }
284 }
285
286 radeon_set_power_state(rdev);
287
288 if (rdev->irq.installed) {
289 for (i = 0; i < rdev->num_crtc; i++) {
290 if (rdev->pm.req_vblank & (1 << i)) {
291 rdev->pm.req_vblank &= ~(1 << i);
292 drm_vblank_put(rdev->ddev, i);
293 }
294 }
295 }
296
297 /* update display watermarks based on new power state */
298 radeon_update_bandwidth_info(rdev);
299 if (rdev->pm.active_crtc_count)
300 radeon_bandwidth_update(rdev);
301
302 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
303
304 mutex_unlock(&rdev->ring_lock);
305 up_write(&rdev->pm.mclk_lock);
306 mutex_unlock(&rdev->ddev->struct_mutex);
307 }
308
radeon_pm_print_states(struct radeon_device * rdev)309 static void radeon_pm_print_states(struct radeon_device *rdev)
310 {
311 int i, j;
312 struct radeon_power_state *power_state;
313 struct radeon_pm_clock_info *clock_info;
314
315 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
316 for (i = 0; i < rdev->pm.num_power_states; i++) {
317 power_state = &rdev->pm.power_state[i];
318 DRM_DEBUG_DRIVER("State %d: %s\n", i,
319 radeon_pm_state_type_name[power_state->type]);
320 if (i == rdev->pm.default_power_state_index)
321 DRM_DEBUG_DRIVER("\tDefault");
322 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
323 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
324 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
325 DRM_DEBUG_DRIVER("\tSingle display only\n");
326 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
327 for (j = 0; j < power_state->num_clock_modes; j++) {
328 clock_info = &(power_state->clock_info[j]);
329 if (rdev->flags & RADEON_IS_IGP)
330 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
331 j,
332 clock_info->sclk * 10);
333 else
334 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
335 j,
336 clock_info->sclk * 10,
337 clock_info->mclk * 10,
338 clock_info->voltage.voltage);
339 }
340 }
341 }
342
radeon_get_pm_profile(struct device * dev,struct device_attribute * attr,char * buf)343 static ssize_t radeon_get_pm_profile(struct device *dev,
344 struct device_attribute *attr,
345 char *buf)
346 {
347 struct drm_device *ddev = dev_get_drvdata(dev);
348 struct radeon_device *rdev = ddev->dev_private;
349 int cp = rdev->pm.profile;
350
351 return snprintf(buf, PAGE_SIZE, "%s\n",
352 (cp == PM_PROFILE_AUTO) ? "auto" :
353 (cp == PM_PROFILE_LOW) ? "low" :
354 (cp == PM_PROFILE_MID) ? "mid" :
355 (cp == PM_PROFILE_HIGH) ? "high" : "default");
356 }
357
radeon_set_pm_profile(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)358 static ssize_t radeon_set_pm_profile(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf,
361 size_t count)
362 {
363 struct drm_device *ddev = dev_get_drvdata(dev);
364 struct radeon_device *rdev = ddev->dev_private;
365
366 /* Can't set profile when the card is off */
367 if ((rdev->flags & RADEON_IS_PX) &&
368 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
369 return -EINVAL;
370
371 mutex_lock(&rdev->pm.mutex);
372 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
373 if (strncmp("default", buf, strlen("default")) == 0)
374 rdev->pm.profile = PM_PROFILE_DEFAULT;
375 else if (strncmp("auto", buf, strlen("auto")) == 0)
376 rdev->pm.profile = PM_PROFILE_AUTO;
377 else if (strncmp("low", buf, strlen("low")) == 0)
378 rdev->pm.profile = PM_PROFILE_LOW;
379 else if (strncmp("mid", buf, strlen("mid")) == 0)
380 rdev->pm.profile = PM_PROFILE_MID;
381 else if (strncmp("high", buf, strlen("high")) == 0)
382 rdev->pm.profile = PM_PROFILE_HIGH;
383 else {
384 count = -EINVAL;
385 goto fail;
386 }
387 radeon_pm_update_profile(rdev);
388 radeon_pm_set_clocks(rdev);
389 } else
390 count = -EINVAL;
391
392 fail:
393 mutex_unlock(&rdev->pm.mutex);
394
395 return count;
396 }
397
radeon_get_pm_method(struct device * dev,struct device_attribute * attr,char * buf)398 static ssize_t radeon_get_pm_method(struct device *dev,
399 struct device_attribute *attr,
400 char *buf)
401 {
402 struct drm_device *ddev = dev_get_drvdata(dev);
403 struct radeon_device *rdev = ddev->dev_private;
404 int pm = rdev->pm.pm_method;
405
406 return snprintf(buf, PAGE_SIZE, "%s\n",
407 (pm == PM_METHOD_DYNPM) ? "dynpm" :
408 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
409 }
410
radeon_set_pm_method(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)411 static ssize_t radeon_set_pm_method(struct device *dev,
412 struct device_attribute *attr,
413 const char *buf,
414 size_t count)
415 {
416 struct drm_device *ddev = dev_get_drvdata(dev);
417 struct radeon_device *rdev = ddev->dev_private;
418
419 /* Can't set method when the card is off */
420 if ((rdev->flags & RADEON_IS_PX) &&
421 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
422 count = -EINVAL;
423 goto fail;
424 }
425
426 /* we don't support the legacy modes with dpm */
427 if (rdev->pm.pm_method == PM_METHOD_DPM) {
428 count = -EINVAL;
429 goto fail;
430 }
431
432 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
433 mutex_lock(&rdev->pm.mutex);
434 rdev->pm.pm_method = PM_METHOD_DYNPM;
435 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
436 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
437 mutex_unlock(&rdev->pm.mutex);
438 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
439 mutex_lock(&rdev->pm.mutex);
440 /* disable dynpm */
441 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
442 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
443 rdev->pm.pm_method = PM_METHOD_PROFILE;
444 mutex_unlock(&rdev->pm.mutex);
445 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
446 } else {
447 count = -EINVAL;
448 goto fail;
449 }
450 radeon_pm_compute_clocks(rdev);
451 fail:
452 return count;
453 }
454
radeon_get_dpm_state(struct device * dev,struct device_attribute * attr,char * buf)455 static ssize_t radeon_get_dpm_state(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458 {
459 struct drm_device *ddev = dev_get_drvdata(dev);
460 struct radeon_device *rdev = ddev->dev_private;
461 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
462
463 return snprintf(buf, PAGE_SIZE, "%s\n",
464 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
465 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
466 }
467
radeon_set_dpm_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)468 static ssize_t radeon_set_dpm_state(struct device *dev,
469 struct device_attribute *attr,
470 const char *buf,
471 size_t count)
472 {
473 struct drm_device *ddev = dev_get_drvdata(dev);
474 struct radeon_device *rdev = ddev->dev_private;
475
476 mutex_lock(&rdev->pm.mutex);
477 if (strncmp("battery", buf, strlen("battery")) == 0)
478 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
479 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
481 else if (strncmp("performance", buf, strlen("performance")) == 0)
482 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
483 else {
484 mutex_unlock(&rdev->pm.mutex);
485 count = -EINVAL;
486 goto fail;
487 }
488 mutex_unlock(&rdev->pm.mutex);
489
490 /* Can't set dpm state when the card is off */
491 if (!(rdev->flags & RADEON_IS_PX) ||
492 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
493 radeon_pm_compute_clocks(rdev);
494
495 fail:
496 return count;
497 }
498
radeon_get_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,char * buf)499 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
500 struct device_attribute *attr,
501 char *buf)
502 {
503 struct drm_device *ddev = dev_get_drvdata(dev);
504 struct radeon_device *rdev = ddev->dev_private;
505 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
506
507 if ((rdev->flags & RADEON_IS_PX) &&
508 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
509 return snprintf(buf, PAGE_SIZE, "off\n");
510
511 return snprintf(buf, PAGE_SIZE, "%s\n",
512 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
513 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
514 }
515
radeon_set_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)516 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
517 struct device_attribute *attr,
518 const char *buf,
519 size_t count)
520 {
521 struct drm_device *ddev = dev_get_drvdata(dev);
522 struct radeon_device *rdev = ddev->dev_private;
523 enum radeon_dpm_forced_level level;
524 int ret = 0;
525
526 /* Can't force performance level when the card is off */
527 if ((rdev->flags & RADEON_IS_PX) &&
528 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
529 return -EINVAL;
530
531 mutex_lock(&rdev->pm.mutex);
532 if (strncmp("low", buf, strlen("low")) == 0) {
533 level = RADEON_DPM_FORCED_LEVEL_LOW;
534 } else if (strncmp("high", buf, strlen("high")) == 0) {
535 level = RADEON_DPM_FORCED_LEVEL_HIGH;
536 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
537 level = RADEON_DPM_FORCED_LEVEL_AUTO;
538 } else {
539 count = -EINVAL;
540 goto fail;
541 }
542 if (rdev->asic->dpm.force_performance_level) {
543 if (rdev->pm.dpm.thermal_active) {
544 count = -EINVAL;
545 goto fail;
546 }
547 ret = radeon_dpm_force_performance_level(rdev, level);
548 if (ret)
549 count = -EINVAL;
550 }
551 fail:
552 mutex_unlock(&rdev->pm.mutex);
553
554 return count;
555 }
556
557 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
558 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
559 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
560 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
561 radeon_get_dpm_forced_performance_level,
562 radeon_set_dpm_forced_performance_level);
563
radeon_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)564 static ssize_t radeon_hwmon_show_temp(struct device *dev,
565 struct device_attribute *attr,
566 char *buf)
567 {
568 struct radeon_device *rdev = dev_get_drvdata(dev);
569 struct drm_device *ddev = rdev->ddev;
570 int temp;
571
572 /* Can't get temperature when the card is off */
573 if ((rdev->flags & RADEON_IS_PX) &&
574 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
575 return -EINVAL;
576
577 if (rdev->asic->pm.get_temperature)
578 temp = radeon_get_temperature(rdev);
579 else
580 temp = 0;
581
582 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
583 }
584
radeon_hwmon_show_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)585 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
586 struct device_attribute *attr,
587 char *buf)
588 {
589 struct radeon_device *rdev = dev_get_drvdata(dev);
590 int hyst = to_sensor_dev_attr(attr)->index;
591 int temp;
592
593 if (hyst)
594 temp = rdev->pm.dpm.thermal.min_temp;
595 else
596 temp = rdev->pm.dpm.thermal.max_temp;
597
598 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
599 }
600
601 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
602 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
603 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
604
605 static struct attribute *hwmon_attributes[] = {
606 &sensor_dev_attr_temp1_input.dev_attr.attr,
607 &sensor_dev_attr_temp1_crit.dev_attr.attr,
608 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
609 NULL
610 };
611
hwmon_attributes_visible(struct kobject * kobj,struct attribute * attr,int index)612 static umode_t hwmon_attributes_visible(struct kobject *kobj,
613 struct attribute *attr, int index)
614 {
615 struct device *dev = container_of(kobj, struct device, kobj);
616 struct radeon_device *rdev = dev_get_drvdata(dev);
617
618 /* Skip limit attributes if DPM is not enabled */
619 if (rdev->pm.pm_method != PM_METHOD_DPM &&
620 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
621 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
622 return 0;
623
624 return attr->mode;
625 }
626
627 static const struct attribute_group hwmon_attrgroup = {
628 .attrs = hwmon_attributes,
629 .is_visible = hwmon_attributes_visible,
630 };
631
632 static const struct attribute_group *hwmon_groups[] = {
633 &hwmon_attrgroup,
634 NULL
635 };
636
radeon_hwmon_init(struct radeon_device * rdev)637 static int radeon_hwmon_init(struct radeon_device *rdev)
638 {
639 int err = 0;
640
641 switch (rdev->pm.int_thermal_type) {
642 case THERMAL_TYPE_RV6XX:
643 case THERMAL_TYPE_RV770:
644 case THERMAL_TYPE_EVERGREEN:
645 case THERMAL_TYPE_NI:
646 case THERMAL_TYPE_SUMO:
647 case THERMAL_TYPE_SI:
648 case THERMAL_TYPE_CI:
649 case THERMAL_TYPE_KV:
650 if (rdev->asic->pm.get_temperature == NULL)
651 return err;
652 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
653 "radeon", rdev,
654 hwmon_groups);
655 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
656 err = PTR_ERR(rdev->pm.int_hwmon_dev);
657 dev_err(rdev->dev,
658 "Unable to register hwmon device: %d\n", err);
659 }
660 break;
661 default:
662 break;
663 }
664
665 return err;
666 }
667
radeon_hwmon_fini(struct radeon_device * rdev)668 static void radeon_hwmon_fini(struct radeon_device *rdev)
669 {
670 if (rdev->pm.int_hwmon_dev)
671 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
672 }
673
radeon_dpm_thermal_work_handler(struct work_struct * work)674 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
675 {
676 struct radeon_device *rdev =
677 container_of(work, struct radeon_device,
678 pm.dpm.thermal.work);
679 /* switch to the thermal state */
680 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
681
682 if (!rdev->pm.dpm_enabled)
683 return;
684
685 if (rdev->asic->pm.get_temperature) {
686 int temp = radeon_get_temperature(rdev);
687
688 if (temp < rdev->pm.dpm.thermal.min_temp)
689 /* switch back the user state */
690 dpm_state = rdev->pm.dpm.user_state;
691 } else {
692 if (rdev->pm.dpm.thermal.high_to_low)
693 /* switch back the user state */
694 dpm_state = rdev->pm.dpm.user_state;
695 }
696 mutex_lock(&rdev->pm.mutex);
697 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
698 rdev->pm.dpm.thermal_active = true;
699 else
700 rdev->pm.dpm.thermal_active = false;
701 rdev->pm.dpm.state = dpm_state;
702 mutex_unlock(&rdev->pm.mutex);
703
704 radeon_pm_compute_clocks(rdev);
705 }
706
radeon_dpm_single_display(struct radeon_device * rdev)707 static bool radeon_dpm_single_display(struct radeon_device *rdev)
708 {
709 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
710 true : false;
711
712 /* check if the vblank period is too short to adjust the mclk */
713 if (single_display && rdev->asic->dpm.vblank_too_short) {
714 if (radeon_dpm_vblank_too_short(rdev))
715 single_display = false;
716 }
717
718 return single_display;
719 }
720
radeon_dpm_pick_power_state(struct radeon_device * rdev,enum radeon_pm_state_type dpm_state)721 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
722 enum radeon_pm_state_type dpm_state)
723 {
724 int i;
725 struct radeon_ps *ps;
726 u32 ui_class;
727 bool single_display = radeon_dpm_single_display(rdev);
728
729 /* certain older asics have a separare 3D performance state,
730 * so try that first if the user selected performance
731 */
732 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
733 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
734 /* balanced states don't exist at the moment */
735 if (dpm_state == POWER_STATE_TYPE_BALANCED)
736 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
737
738 restart_search:
739 /* Pick the best power state based on current conditions */
740 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
741 ps = &rdev->pm.dpm.ps[i];
742 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
743 switch (dpm_state) {
744 /* user states */
745 case POWER_STATE_TYPE_BATTERY:
746 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
747 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
748 if (single_display)
749 return ps;
750 } else
751 return ps;
752 }
753 break;
754 case POWER_STATE_TYPE_BALANCED:
755 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
756 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
757 if (single_display)
758 return ps;
759 } else
760 return ps;
761 }
762 break;
763 case POWER_STATE_TYPE_PERFORMANCE:
764 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
765 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
766 if (single_display)
767 return ps;
768 } else
769 return ps;
770 }
771 break;
772 /* internal states */
773 case POWER_STATE_TYPE_INTERNAL_UVD:
774 if (rdev->pm.dpm.uvd_ps)
775 return rdev->pm.dpm.uvd_ps;
776 else
777 break;
778 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
779 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
780 return ps;
781 break;
782 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
783 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
784 return ps;
785 break;
786 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
787 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
788 return ps;
789 break;
790 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
791 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
792 return ps;
793 break;
794 case POWER_STATE_TYPE_INTERNAL_BOOT:
795 return rdev->pm.dpm.boot_ps;
796 case POWER_STATE_TYPE_INTERNAL_THERMAL:
797 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
798 return ps;
799 break;
800 case POWER_STATE_TYPE_INTERNAL_ACPI:
801 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
802 return ps;
803 break;
804 case POWER_STATE_TYPE_INTERNAL_ULV:
805 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
806 return ps;
807 break;
808 case POWER_STATE_TYPE_INTERNAL_3DPERF:
809 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
810 return ps;
811 break;
812 default:
813 break;
814 }
815 }
816 /* use a fallback state if we didn't match */
817 switch (dpm_state) {
818 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
819 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
820 goto restart_search;
821 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
822 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
823 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
824 if (rdev->pm.dpm.uvd_ps) {
825 return rdev->pm.dpm.uvd_ps;
826 } else {
827 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
828 goto restart_search;
829 }
830 case POWER_STATE_TYPE_INTERNAL_THERMAL:
831 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
832 goto restart_search;
833 case POWER_STATE_TYPE_INTERNAL_ACPI:
834 dpm_state = POWER_STATE_TYPE_BATTERY;
835 goto restart_search;
836 case POWER_STATE_TYPE_BATTERY:
837 case POWER_STATE_TYPE_BALANCED:
838 case POWER_STATE_TYPE_INTERNAL_3DPERF:
839 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
840 goto restart_search;
841 default:
842 break;
843 }
844
845 return NULL;
846 }
847
radeon_dpm_change_power_state_locked(struct radeon_device * rdev)848 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
849 {
850 int i;
851 struct radeon_ps *ps;
852 enum radeon_pm_state_type dpm_state;
853 int ret;
854 bool single_display = radeon_dpm_single_display(rdev);
855
856 /* if dpm init failed */
857 if (!rdev->pm.dpm_enabled)
858 return;
859
860 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
861 /* add other state override checks here */
862 if ((!rdev->pm.dpm.thermal_active) &&
863 (!rdev->pm.dpm.uvd_active))
864 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
865 }
866 dpm_state = rdev->pm.dpm.state;
867
868 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
869 if (ps)
870 rdev->pm.dpm.requested_ps = ps;
871 else
872 return;
873
874 /* no need to reprogram if nothing changed unless we are on BTC+ */
875 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
876 /* vce just modifies an existing state so force a change */
877 if (ps->vce_active != rdev->pm.dpm.vce_active)
878 goto force;
879 /* user has made a display change (such as timing) */
880 if (rdev->pm.dpm.single_display != single_display)
881 goto force;
882 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
883 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
884 * all we need to do is update the display configuration.
885 */
886 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
887 /* update display watermarks based on new power state */
888 radeon_bandwidth_update(rdev);
889 /* update displays */
890 radeon_dpm_display_configuration_changed(rdev);
891 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
892 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
893 }
894 return;
895 } else {
896 /* for BTC+ if the num crtcs hasn't changed and state is the same,
897 * nothing to do, if the num crtcs is > 1 and state is the same,
898 * update display configuration.
899 */
900 if (rdev->pm.dpm.new_active_crtcs ==
901 rdev->pm.dpm.current_active_crtcs) {
902 return;
903 } else {
904 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
905 (rdev->pm.dpm.new_active_crtc_count > 1)) {
906 /* update display watermarks based on new power state */
907 radeon_bandwidth_update(rdev);
908 /* update displays */
909 radeon_dpm_display_configuration_changed(rdev);
910 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
911 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
912 return;
913 }
914 }
915 }
916 }
917
918 force:
919 if (radeon_dpm == 1) {
920 printk("switching from power state:\n");
921 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
922 printk("switching to power state:\n");
923 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
924 }
925
926 mutex_lock(&rdev->ddev->struct_mutex);
927 down_write(&rdev->pm.mclk_lock);
928 mutex_lock(&rdev->ring_lock);
929
930 /* update whether vce is active */
931 ps->vce_active = rdev->pm.dpm.vce_active;
932
933 ret = radeon_dpm_pre_set_power_state(rdev);
934 if (ret)
935 goto done;
936
937 /* update display watermarks based on new power state */
938 radeon_bandwidth_update(rdev);
939 /* update displays */
940 radeon_dpm_display_configuration_changed(rdev);
941
942 /* wait for the rings to drain */
943 for (i = 0; i < RADEON_NUM_RINGS; i++) {
944 struct radeon_ring *ring = &rdev->ring[i];
945 if (ring->ready)
946 radeon_fence_wait_empty(rdev, i);
947 }
948
949 /* program the new power state */
950 radeon_dpm_set_power_state(rdev);
951
952 /* update current power state */
953 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
954
955 radeon_dpm_post_set_power_state(rdev);
956
957 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
958 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
959 rdev->pm.dpm.single_display = single_display;
960
961 if (rdev->asic->dpm.force_performance_level) {
962 if (rdev->pm.dpm.thermal_active) {
963 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
964 /* force low perf level for thermal */
965 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
966 /* save the user's level */
967 rdev->pm.dpm.forced_level = level;
968 } else {
969 /* otherwise, user selected level */
970 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
971 }
972 }
973
974 done:
975 mutex_unlock(&rdev->ring_lock);
976 up_write(&rdev->pm.mclk_lock);
977 mutex_unlock(&rdev->ddev->struct_mutex);
978 }
979
radeon_dpm_enable_uvd(struct radeon_device * rdev,bool enable)980 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
981 {
982 enum radeon_pm_state_type dpm_state;
983
984 if (rdev->asic->dpm.powergate_uvd) {
985 mutex_lock(&rdev->pm.mutex);
986 /* don't powergate anything if we
987 have active but pause streams */
988 enable |= rdev->pm.dpm.sd > 0;
989 enable |= rdev->pm.dpm.hd > 0;
990 /* enable/disable UVD */
991 radeon_dpm_powergate_uvd(rdev, !enable);
992 mutex_unlock(&rdev->pm.mutex);
993 } else {
994 if (enable) {
995 mutex_lock(&rdev->pm.mutex);
996 rdev->pm.dpm.uvd_active = true;
997 /* disable this for now */
998 #if 0
999 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1000 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1001 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1002 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1003 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1004 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1005 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1006 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1007 else
1008 #endif
1009 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1010 rdev->pm.dpm.state = dpm_state;
1011 mutex_unlock(&rdev->pm.mutex);
1012 } else {
1013 mutex_lock(&rdev->pm.mutex);
1014 rdev->pm.dpm.uvd_active = false;
1015 mutex_unlock(&rdev->pm.mutex);
1016 }
1017
1018 radeon_pm_compute_clocks(rdev);
1019 }
1020 }
1021
radeon_dpm_enable_vce(struct radeon_device * rdev,bool enable)1022 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1023 {
1024 if (enable) {
1025 mutex_lock(&rdev->pm.mutex);
1026 rdev->pm.dpm.vce_active = true;
1027 /* XXX select vce level based on ring/task */
1028 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1029 mutex_unlock(&rdev->pm.mutex);
1030 } else {
1031 mutex_lock(&rdev->pm.mutex);
1032 rdev->pm.dpm.vce_active = false;
1033 mutex_unlock(&rdev->pm.mutex);
1034 }
1035
1036 radeon_pm_compute_clocks(rdev);
1037 }
1038
radeon_pm_suspend_old(struct radeon_device * rdev)1039 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1040 {
1041 mutex_lock(&rdev->pm.mutex);
1042 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1043 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1044 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1045 }
1046 mutex_unlock(&rdev->pm.mutex);
1047
1048 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1049 }
1050
radeon_pm_suspend_dpm(struct radeon_device * rdev)1051 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1052 {
1053 mutex_lock(&rdev->pm.mutex);
1054 /* disable dpm */
1055 radeon_dpm_disable(rdev);
1056 /* reset the power state */
1057 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1058 rdev->pm.dpm_enabled = false;
1059 mutex_unlock(&rdev->pm.mutex);
1060 }
1061
radeon_pm_suspend(struct radeon_device * rdev)1062 void radeon_pm_suspend(struct radeon_device *rdev)
1063 {
1064 if (rdev->pm.pm_method == PM_METHOD_DPM)
1065 radeon_pm_suspend_dpm(rdev);
1066 else
1067 radeon_pm_suspend_old(rdev);
1068 }
1069
radeon_pm_resume_old(struct radeon_device * rdev)1070 static void radeon_pm_resume_old(struct radeon_device *rdev)
1071 {
1072 /* set up the default clocks if the MC ucode is loaded */
1073 if ((rdev->family >= CHIP_BARTS) &&
1074 (rdev->family <= CHIP_CAYMAN) &&
1075 rdev->mc_fw) {
1076 if (rdev->pm.default_vddc)
1077 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1078 SET_VOLTAGE_TYPE_ASIC_VDDC);
1079 if (rdev->pm.default_vddci)
1080 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1081 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1082 if (rdev->pm.default_sclk)
1083 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1084 if (rdev->pm.default_mclk)
1085 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1086 }
1087 /* asic init will reset the default power state */
1088 mutex_lock(&rdev->pm.mutex);
1089 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1090 rdev->pm.current_clock_mode_index = 0;
1091 rdev->pm.current_sclk = rdev->pm.default_sclk;
1092 rdev->pm.current_mclk = rdev->pm.default_mclk;
1093 if (rdev->pm.power_state) {
1094 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1095 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1096 }
1097 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1098 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1099 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1100 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1101 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1102 }
1103 mutex_unlock(&rdev->pm.mutex);
1104 radeon_pm_compute_clocks(rdev);
1105 }
1106
radeon_pm_resume_dpm(struct radeon_device * rdev)1107 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1108 {
1109 int ret;
1110
1111 /* asic init will reset to the boot state */
1112 mutex_lock(&rdev->pm.mutex);
1113 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1114 radeon_dpm_setup_asic(rdev);
1115 ret = radeon_dpm_enable(rdev);
1116 mutex_unlock(&rdev->pm.mutex);
1117 if (ret)
1118 goto dpm_resume_fail;
1119 rdev->pm.dpm_enabled = true;
1120 return;
1121
1122 dpm_resume_fail:
1123 DRM_ERROR("radeon: dpm resume failed\n");
1124 if ((rdev->family >= CHIP_BARTS) &&
1125 (rdev->family <= CHIP_CAYMAN) &&
1126 rdev->mc_fw) {
1127 if (rdev->pm.default_vddc)
1128 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1129 SET_VOLTAGE_TYPE_ASIC_VDDC);
1130 if (rdev->pm.default_vddci)
1131 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1132 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1133 if (rdev->pm.default_sclk)
1134 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1135 if (rdev->pm.default_mclk)
1136 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1137 }
1138 }
1139
radeon_pm_resume(struct radeon_device * rdev)1140 void radeon_pm_resume(struct radeon_device *rdev)
1141 {
1142 if (rdev->pm.pm_method == PM_METHOD_DPM)
1143 radeon_pm_resume_dpm(rdev);
1144 else
1145 radeon_pm_resume_old(rdev);
1146 }
1147
radeon_pm_init_old(struct radeon_device * rdev)1148 static int radeon_pm_init_old(struct radeon_device *rdev)
1149 {
1150 int ret;
1151
1152 rdev->pm.profile = PM_PROFILE_DEFAULT;
1153 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1154 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1155 rdev->pm.dynpm_can_upclock = true;
1156 rdev->pm.dynpm_can_downclock = true;
1157 rdev->pm.default_sclk = rdev->clock.default_sclk;
1158 rdev->pm.default_mclk = rdev->clock.default_mclk;
1159 rdev->pm.current_sclk = rdev->clock.default_sclk;
1160 rdev->pm.current_mclk = rdev->clock.default_mclk;
1161 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1162
1163 if (rdev->bios) {
1164 if (rdev->is_atom_bios)
1165 radeon_atombios_get_power_modes(rdev);
1166 else
1167 radeon_combios_get_power_modes(rdev);
1168 radeon_pm_print_states(rdev);
1169 radeon_pm_init_profile(rdev);
1170 /* set up the default clocks if the MC ucode is loaded */
1171 if ((rdev->family >= CHIP_BARTS) &&
1172 (rdev->family <= CHIP_CAYMAN) &&
1173 rdev->mc_fw) {
1174 if (rdev->pm.default_vddc)
1175 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1176 SET_VOLTAGE_TYPE_ASIC_VDDC);
1177 if (rdev->pm.default_vddci)
1178 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1179 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1180 if (rdev->pm.default_sclk)
1181 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1182 if (rdev->pm.default_mclk)
1183 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1184 }
1185 }
1186
1187 /* set up the internal thermal sensor if applicable */
1188 ret = radeon_hwmon_init(rdev);
1189 if (ret)
1190 return ret;
1191
1192 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1193
1194 if (rdev->pm.num_power_states > 1) {
1195 if (radeon_debugfs_pm_init(rdev)) {
1196 DRM_ERROR("Failed to register debugfs file for PM!\n");
1197 }
1198
1199 DRM_INFO("radeon: power management initialized\n");
1200 }
1201
1202 return 0;
1203 }
1204
radeon_dpm_print_power_states(struct radeon_device * rdev)1205 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1206 {
1207 int i;
1208
1209 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1210 printk("== power state %d ==\n", i);
1211 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1212 }
1213 }
1214
radeon_pm_init_dpm(struct radeon_device * rdev)1215 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1216 {
1217 int ret;
1218
1219 /* default to balanced state */
1220 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1221 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1222 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1223 rdev->pm.default_sclk = rdev->clock.default_sclk;
1224 rdev->pm.default_mclk = rdev->clock.default_mclk;
1225 rdev->pm.current_sclk = rdev->clock.default_sclk;
1226 rdev->pm.current_mclk = rdev->clock.default_mclk;
1227 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1228
1229 if (rdev->bios && rdev->is_atom_bios)
1230 radeon_atombios_get_power_modes(rdev);
1231 else
1232 return -EINVAL;
1233
1234 /* set up the internal thermal sensor if applicable */
1235 ret = radeon_hwmon_init(rdev);
1236 if (ret)
1237 return ret;
1238
1239 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1240 mutex_lock(&rdev->pm.mutex);
1241 radeon_dpm_init(rdev);
1242 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1243 if (radeon_dpm == 1)
1244 radeon_dpm_print_power_states(rdev);
1245 radeon_dpm_setup_asic(rdev);
1246 ret = radeon_dpm_enable(rdev);
1247 mutex_unlock(&rdev->pm.mutex);
1248 if (ret)
1249 goto dpm_failed;
1250 rdev->pm.dpm_enabled = true;
1251
1252 if (radeon_debugfs_pm_init(rdev)) {
1253 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1254 }
1255
1256 DRM_INFO("radeon: dpm initialized\n");
1257
1258 return 0;
1259
1260 dpm_failed:
1261 rdev->pm.dpm_enabled = false;
1262 if ((rdev->family >= CHIP_BARTS) &&
1263 (rdev->family <= CHIP_CAYMAN) &&
1264 rdev->mc_fw) {
1265 if (rdev->pm.default_vddc)
1266 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1267 SET_VOLTAGE_TYPE_ASIC_VDDC);
1268 if (rdev->pm.default_vddci)
1269 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1270 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1271 if (rdev->pm.default_sclk)
1272 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1273 if (rdev->pm.default_mclk)
1274 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1275 }
1276 DRM_ERROR("radeon: dpm initialization failed\n");
1277 return ret;
1278 }
1279
1280 struct radeon_dpm_quirk {
1281 u32 chip_vendor;
1282 u32 chip_device;
1283 u32 subsys_vendor;
1284 u32 subsys_device;
1285 };
1286
1287 /* cards with dpm stability problems */
1288 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1289 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1290 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1291 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1292 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1293 { 0, 0, 0, 0 },
1294 };
1295
radeon_pm_init(struct radeon_device * rdev)1296 int radeon_pm_init(struct radeon_device *rdev)
1297 {
1298 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1299 bool disable_dpm = false;
1300
1301 /* Apply dpm quirks */
1302 while (p && p->chip_device != 0) {
1303 if (rdev->pdev->vendor == p->chip_vendor &&
1304 rdev->pdev->device == p->chip_device &&
1305 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1306 rdev->pdev->subsystem_device == p->subsys_device) {
1307 disable_dpm = true;
1308 break;
1309 }
1310 ++p;
1311 }
1312
1313 /* enable dpm on rv6xx+ */
1314 switch (rdev->family) {
1315 case CHIP_RV610:
1316 case CHIP_RV630:
1317 case CHIP_RV620:
1318 case CHIP_RV635:
1319 case CHIP_RV670:
1320 case CHIP_RS780:
1321 case CHIP_RS880:
1322 case CHIP_RV770:
1323 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1324 if (!rdev->rlc_fw)
1325 rdev->pm.pm_method = PM_METHOD_PROFILE;
1326 else if ((rdev->family >= CHIP_RV770) &&
1327 (!(rdev->flags & RADEON_IS_IGP)) &&
1328 (!rdev->smc_fw))
1329 rdev->pm.pm_method = PM_METHOD_PROFILE;
1330 else if (radeon_dpm == 1)
1331 rdev->pm.pm_method = PM_METHOD_DPM;
1332 else
1333 rdev->pm.pm_method = PM_METHOD_PROFILE;
1334 break;
1335 case CHIP_RV730:
1336 case CHIP_RV710:
1337 case CHIP_RV740:
1338 case CHIP_CEDAR:
1339 case CHIP_REDWOOD:
1340 case CHIP_JUNIPER:
1341 case CHIP_CYPRESS:
1342 case CHIP_HEMLOCK:
1343 case CHIP_PALM:
1344 case CHIP_SUMO:
1345 case CHIP_SUMO2:
1346 case CHIP_BARTS:
1347 case CHIP_TURKS:
1348 case CHIP_CAICOS:
1349 case CHIP_CAYMAN:
1350 case CHIP_ARUBA:
1351 case CHIP_TAHITI:
1352 case CHIP_PITCAIRN:
1353 case CHIP_VERDE:
1354 case CHIP_OLAND:
1355 case CHIP_HAINAN:
1356 case CHIP_BONAIRE:
1357 case CHIP_KABINI:
1358 case CHIP_KAVERI:
1359 case CHIP_HAWAII:
1360 case CHIP_MULLINS:
1361 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1362 if (!rdev->rlc_fw)
1363 rdev->pm.pm_method = PM_METHOD_PROFILE;
1364 else if ((rdev->family >= CHIP_RV770) &&
1365 (!(rdev->flags & RADEON_IS_IGP)) &&
1366 (!rdev->smc_fw))
1367 rdev->pm.pm_method = PM_METHOD_PROFILE;
1368 else if (disable_dpm && (radeon_dpm == -1))
1369 rdev->pm.pm_method = PM_METHOD_PROFILE;
1370 else if (radeon_dpm == 0)
1371 rdev->pm.pm_method = PM_METHOD_PROFILE;
1372 else
1373 rdev->pm.pm_method = PM_METHOD_DPM;
1374 break;
1375 default:
1376 /* default to profile method */
1377 rdev->pm.pm_method = PM_METHOD_PROFILE;
1378 break;
1379 }
1380
1381 if (rdev->pm.pm_method == PM_METHOD_DPM)
1382 return radeon_pm_init_dpm(rdev);
1383 else
1384 return radeon_pm_init_old(rdev);
1385 }
1386
radeon_pm_late_init(struct radeon_device * rdev)1387 int radeon_pm_late_init(struct radeon_device *rdev)
1388 {
1389 int ret = 0;
1390
1391 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1392 if (rdev->pm.dpm_enabled) {
1393 if (!rdev->pm.sysfs_initialized) {
1394 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1395 if (ret)
1396 DRM_ERROR("failed to create device file for dpm state\n");
1397 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1398 if (ret)
1399 DRM_ERROR("failed to create device file for dpm state\n");
1400 /* XXX: these are noops for dpm but are here for backwards compat */
1401 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1402 if (ret)
1403 DRM_ERROR("failed to create device file for power profile\n");
1404 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1405 if (ret)
1406 DRM_ERROR("failed to create device file for power method\n");
1407 if (!ret)
1408 rdev->pm.sysfs_initialized = true;
1409 }
1410
1411 mutex_lock(&rdev->pm.mutex);
1412 ret = radeon_dpm_late_enable(rdev);
1413 mutex_unlock(&rdev->pm.mutex);
1414 if (ret) {
1415 rdev->pm.dpm_enabled = false;
1416 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1417 } else {
1418 /* set the dpm state for PX since there won't be
1419 * a modeset to call this.
1420 */
1421 radeon_pm_compute_clocks(rdev);
1422 }
1423 }
1424 } else {
1425 if ((rdev->pm.num_power_states > 1) &&
1426 (!rdev->pm.sysfs_initialized)) {
1427 /* where's the best place to put these? */
1428 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1429 if (ret)
1430 DRM_ERROR("failed to create device file for power profile\n");
1431 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1432 if (ret)
1433 DRM_ERROR("failed to create device file for power method\n");
1434 if (!ret)
1435 rdev->pm.sysfs_initialized = true;
1436 }
1437 }
1438 return ret;
1439 }
1440
radeon_pm_fini_old(struct radeon_device * rdev)1441 static void radeon_pm_fini_old(struct radeon_device *rdev)
1442 {
1443 if (rdev->pm.num_power_states > 1) {
1444 mutex_lock(&rdev->pm.mutex);
1445 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1446 rdev->pm.profile = PM_PROFILE_DEFAULT;
1447 radeon_pm_update_profile(rdev);
1448 radeon_pm_set_clocks(rdev);
1449 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1450 /* reset default clocks */
1451 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1452 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1453 radeon_pm_set_clocks(rdev);
1454 }
1455 mutex_unlock(&rdev->pm.mutex);
1456
1457 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1458
1459 device_remove_file(rdev->dev, &dev_attr_power_profile);
1460 device_remove_file(rdev->dev, &dev_attr_power_method);
1461 }
1462
1463 radeon_hwmon_fini(rdev);
1464 kfree(rdev->pm.power_state);
1465 }
1466
radeon_pm_fini_dpm(struct radeon_device * rdev)1467 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1468 {
1469 if (rdev->pm.num_power_states > 1) {
1470 mutex_lock(&rdev->pm.mutex);
1471 radeon_dpm_disable(rdev);
1472 mutex_unlock(&rdev->pm.mutex);
1473
1474 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1475 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1476 /* XXX backwards compat */
1477 device_remove_file(rdev->dev, &dev_attr_power_profile);
1478 device_remove_file(rdev->dev, &dev_attr_power_method);
1479 }
1480 radeon_dpm_fini(rdev);
1481
1482 radeon_hwmon_fini(rdev);
1483 kfree(rdev->pm.power_state);
1484 }
1485
radeon_pm_fini(struct radeon_device * rdev)1486 void radeon_pm_fini(struct radeon_device *rdev)
1487 {
1488 if (rdev->pm.pm_method == PM_METHOD_DPM)
1489 radeon_pm_fini_dpm(rdev);
1490 else
1491 radeon_pm_fini_old(rdev);
1492 }
1493
radeon_pm_compute_clocks_old(struct radeon_device * rdev)1494 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1495 {
1496 struct drm_device *ddev = rdev->ddev;
1497 struct drm_crtc *crtc;
1498 struct radeon_crtc *radeon_crtc;
1499
1500 if (rdev->pm.num_power_states < 2)
1501 return;
1502
1503 mutex_lock(&rdev->pm.mutex);
1504
1505 rdev->pm.active_crtcs = 0;
1506 rdev->pm.active_crtc_count = 0;
1507 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1508 list_for_each_entry(crtc,
1509 &ddev->mode_config.crtc_list, head) {
1510 radeon_crtc = to_radeon_crtc(crtc);
1511 if (radeon_crtc->enabled) {
1512 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1513 rdev->pm.active_crtc_count++;
1514 }
1515 }
1516 }
1517
1518 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1519 radeon_pm_update_profile(rdev);
1520 radeon_pm_set_clocks(rdev);
1521 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1522 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1523 if (rdev->pm.active_crtc_count > 1) {
1524 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1525 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1526
1527 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1528 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1529 radeon_pm_get_dynpm_state(rdev);
1530 radeon_pm_set_clocks(rdev);
1531
1532 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1533 }
1534 } else if (rdev->pm.active_crtc_count == 1) {
1535 /* TODO: Increase clocks if needed for current mode */
1536
1537 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1538 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1539 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1540 radeon_pm_get_dynpm_state(rdev);
1541 radeon_pm_set_clocks(rdev);
1542
1543 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1544 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1545 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1546 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1547 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1548 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1549 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1550 }
1551 } else { /* count == 0 */
1552 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1553 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1554
1555 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1556 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1557 radeon_pm_get_dynpm_state(rdev);
1558 radeon_pm_set_clocks(rdev);
1559 }
1560 }
1561 }
1562 }
1563
1564 mutex_unlock(&rdev->pm.mutex);
1565 }
1566
radeon_pm_compute_clocks_dpm(struct radeon_device * rdev)1567 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1568 {
1569 struct drm_device *ddev = rdev->ddev;
1570 struct drm_crtc *crtc;
1571 struct radeon_crtc *radeon_crtc;
1572
1573 if (!rdev->pm.dpm_enabled)
1574 return;
1575
1576 mutex_lock(&rdev->pm.mutex);
1577
1578 /* update active crtc counts */
1579 rdev->pm.dpm.new_active_crtcs = 0;
1580 rdev->pm.dpm.new_active_crtc_count = 0;
1581 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1582 list_for_each_entry(crtc,
1583 &ddev->mode_config.crtc_list, head) {
1584 radeon_crtc = to_radeon_crtc(crtc);
1585 if (crtc->enabled) {
1586 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1587 rdev->pm.dpm.new_active_crtc_count++;
1588 }
1589 }
1590 }
1591
1592 /* update battery/ac status */
1593 if (power_supply_is_system_supplied() > 0)
1594 rdev->pm.dpm.ac_power = true;
1595 else
1596 rdev->pm.dpm.ac_power = false;
1597
1598 radeon_dpm_change_power_state_locked(rdev);
1599
1600 mutex_unlock(&rdev->pm.mutex);
1601
1602 }
1603
radeon_pm_compute_clocks(struct radeon_device * rdev)1604 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1605 {
1606 if (rdev->pm.pm_method == PM_METHOD_DPM)
1607 radeon_pm_compute_clocks_dpm(rdev);
1608 else
1609 radeon_pm_compute_clocks_old(rdev);
1610 }
1611
radeon_pm_in_vbl(struct radeon_device * rdev)1612 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1613 {
1614 int crtc, vpos, hpos, vbl_status;
1615 bool in_vbl = true;
1616
1617 /* Iterate over all active crtc's. All crtc's must be in vblank,
1618 * otherwise return in_vbl == false.
1619 */
1620 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1621 if (rdev->pm.active_crtcs & (1 << crtc)) {
1622 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1623 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1624 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1625 in_vbl = false;
1626 }
1627 }
1628
1629 return in_vbl;
1630 }
1631
radeon_pm_debug_check_in_vbl(struct radeon_device * rdev,bool finish)1632 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1633 {
1634 u32 stat_crtc = 0;
1635 bool in_vbl = radeon_pm_in_vbl(rdev);
1636
1637 if (in_vbl == false)
1638 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1639 finish ? "exit" : "entry");
1640 return in_vbl;
1641 }
1642
radeon_dynpm_idle_work_handler(struct work_struct * work)1643 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1644 {
1645 struct radeon_device *rdev;
1646 int resched;
1647 rdev = container_of(work, struct radeon_device,
1648 pm.dynpm_idle_work.work);
1649
1650 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1651 mutex_lock(&rdev->pm.mutex);
1652 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1653 int not_processed = 0;
1654 int i;
1655
1656 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1657 struct radeon_ring *ring = &rdev->ring[i];
1658
1659 if (ring->ready) {
1660 not_processed += radeon_fence_count_emitted(rdev, i);
1661 if (not_processed >= 3)
1662 break;
1663 }
1664 }
1665
1666 if (not_processed >= 3) { /* should upclock */
1667 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1668 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1669 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1670 rdev->pm.dynpm_can_upclock) {
1671 rdev->pm.dynpm_planned_action =
1672 DYNPM_ACTION_UPCLOCK;
1673 rdev->pm.dynpm_action_timeout = jiffies +
1674 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1675 }
1676 } else if (not_processed == 0) { /* should downclock */
1677 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1678 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1679 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1680 rdev->pm.dynpm_can_downclock) {
1681 rdev->pm.dynpm_planned_action =
1682 DYNPM_ACTION_DOWNCLOCK;
1683 rdev->pm.dynpm_action_timeout = jiffies +
1684 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1685 }
1686 }
1687
1688 /* Note, radeon_pm_set_clocks is called with static_switch set
1689 * to false since we want to wait for vbl to avoid flicker.
1690 */
1691 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1692 jiffies > rdev->pm.dynpm_action_timeout) {
1693 radeon_pm_get_dynpm_state(rdev);
1694 radeon_pm_set_clocks(rdev);
1695 }
1696
1697 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1698 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1699 }
1700 mutex_unlock(&rdev->pm.mutex);
1701 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1702 }
1703
1704 /*
1705 * Debugfs info
1706 */
1707 #if defined(CONFIG_DEBUG_FS)
1708
radeon_debugfs_pm_info(struct seq_file * m,void * data)1709 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1710 {
1711 struct drm_info_node *node = (struct drm_info_node *) m->private;
1712 struct drm_device *dev = node->minor->dev;
1713 struct radeon_device *rdev = dev->dev_private;
1714 struct drm_device *ddev = rdev->ddev;
1715
1716 if ((rdev->flags & RADEON_IS_PX) &&
1717 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1718 seq_printf(m, "PX asic powered off\n");
1719 } else if (rdev->pm.dpm_enabled) {
1720 mutex_lock(&rdev->pm.mutex);
1721 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1722 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1723 else
1724 seq_printf(m, "Debugfs support not implemented for this asic\n");
1725 mutex_unlock(&rdev->pm.mutex);
1726 } else {
1727 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1728 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1729 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1730 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1731 else
1732 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1733 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1734 if (rdev->asic->pm.get_memory_clock)
1735 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1736 if (rdev->pm.current_vddc)
1737 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1738 if (rdev->asic->pm.get_pcie_lanes)
1739 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1740 }
1741
1742 return 0;
1743 }
1744
1745 static struct drm_info_list radeon_pm_info_list[] = {
1746 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1747 };
1748 #endif
1749
radeon_debugfs_pm_init(struct radeon_device * rdev)1750 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1751 {
1752 #if defined(CONFIG_DEBUG_FS)
1753 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1754 #else
1755 return 0;
1756 #endif
1757 }
1758