1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26
27 #include "rtsx.h"
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
31 #include "sd.h"
32
33 #define SD_MAX_RETRY_COUNT 3
34
35 static u16 REG_SD_CFG1;
36 static u16 REG_SD_CFG2;
37 static u16 REG_SD_CFG3;
38 static u16 REG_SD_STAT1;
39 static u16 REG_SD_STAT2;
40 static u16 REG_SD_BUS_STAT;
41 static u16 REG_SD_PAD_CTL;
42 static u16 REG_SD_SAMPLE_POINT_CTL;
43 static u16 REG_SD_PUSH_POINT_CTL;
44 static u16 REG_SD_CMD0;
45 static u16 REG_SD_CMD1;
46 static u16 REG_SD_CMD2;
47 static u16 REG_SD_CMD3;
48 static u16 REG_SD_CMD4;
49 static u16 REG_SD_CMD5;
50 static u16 REG_SD_BYTE_CNT_L;
51 static u16 REG_SD_BYTE_CNT_H;
52 static u16 REG_SD_BLOCK_CNT_L;
53 static u16 REG_SD_BLOCK_CNT_H;
54 static u16 REG_SD_TRANSFER;
55 static u16 REG_SD_VPCLK0_CTL;
56 static u16 REG_SD_VPCLK1_CTL;
57 static u16 REG_SD_DCMPS0_CTL;
58 static u16 REG_SD_DCMPS1_CTL;
59
sd_set_err_code(struct rtsx_chip * chip,u8 err_code)60 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
61 {
62 struct sd_info *sd_card = &(chip->sd_card);
63
64 sd_card->err_code |= err_code;
65 }
66
sd_clr_err_code(struct rtsx_chip * chip)67 static inline void sd_clr_err_code(struct rtsx_chip *chip)
68 {
69 struct sd_info *sd_card = &(chip->sd_card);
70
71 sd_card->err_code = 0;
72 }
73
sd_check_err_code(struct rtsx_chip * chip,u8 err_code)74 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
75 {
76 struct sd_info *sd_card = &(chip->sd_card);
77
78 return sd_card->err_code & err_code;
79 }
80
sd_init_reg_addr(struct rtsx_chip * chip)81 static void sd_init_reg_addr(struct rtsx_chip *chip)
82 {
83 REG_SD_CFG1 = 0xFD31;
84 REG_SD_CFG2 = 0xFD33;
85 REG_SD_CFG3 = 0xFD3E;
86 REG_SD_STAT1 = 0xFD30;
87 REG_SD_STAT2 = 0;
88 REG_SD_BUS_STAT = 0;
89 REG_SD_PAD_CTL = 0;
90 REG_SD_SAMPLE_POINT_CTL = 0;
91 REG_SD_PUSH_POINT_CTL = 0;
92 REG_SD_CMD0 = 0xFD34;
93 REG_SD_CMD1 = 0xFD35;
94 REG_SD_CMD2 = 0xFD36;
95 REG_SD_CMD3 = 0xFD37;
96 REG_SD_CMD4 = 0xFD38;
97 REG_SD_CMD5 = 0xFD5A;
98 REG_SD_BYTE_CNT_L = 0xFD39;
99 REG_SD_BYTE_CNT_H = 0xFD3A;
100 REG_SD_BLOCK_CNT_L = 0xFD3B;
101 REG_SD_BLOCK_CNT_H = 0xFD3C;
102 REG_SD_TRANSFER = 0xFD32;
103 REG_SD_VPCLK0_CTL = 0;
104 REG_SD_VPCLK1_CTL = 0;
105 REG_SD_DCMPS0_CTL = 0;
106 REG_SD_DCMPS1_CTL = 0;
107 }
108
sd_check_data0_status(struct rtsx_chip * chip)109 static int sd_check_data0_status(struct rtsx_chip *chip)
110 {
111 u8 stat;
112
113 RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
114
115 if (!(stat & SD_DAT0_STATUS)) {
116 sd_set_err_code(chip, SD_BUSY);
117 TRACE_RET(chip, STATUS_FAIL);
118 }
119
120 return STATUS_SUCCESS;
121 }
122
sd_send_cmd_get_rsp(struct rtsx_chip * chip,u8 cmd_idx,u32 arg,u8 rsp_type,u8 * rsp,int rsp_len)123 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
124 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
125 {
126 struct sd_info *sd_card = &(chip->sd_card);
127 int retval;
128 int timeout = 100;
129 u16 reg_addr;
130 u8 *ptr;
131 int stat_idx = 0;
132 int rty_cnt = 0;
133
134 sd_clr_err_code(chip);
135
136 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
137
138 if (rsp_type == SD_RSP_TYPE_R1b)
139 timeout = 3000;
140
141 RTY_SEND_CMD:
142
143 rtsx_init_cmd(chip);
144
145 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
146 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
147 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
148 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
150
151 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
152 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
153 0x01, PINGPONG_BUFFER);
154 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
155 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
156 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
157 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
158
159 if (rsp_type == SD_RSP_TYPE_R2) {
160 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
161 reg_addr++)
162 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
163
164 stat_idx = 16;
165 } else if (rsp_type != SD_RSP_TYPE_R0) {
166 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
167 reg_addr++)
168 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
169
170 stat_idx = 5;
171 }
172
173 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
174
175 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
176 if (retval < 0) {
177 u8 val;
178
179 rtsx_read_register(chip, REG_SD_STAT1, &val);
180 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
181
182 rtsx_read_register(chip, REG_SD_CFG3, &val);
183 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
184
185 if (retval == -ETIMEDOUT) {
186 if (rsp_type & SD_WAIT_BUSY_END) {
187 retval = sd_check_data0_status(chip);
188 if (retval != STATUS_SUCCESS) {
189 rtsx_clear_sd_error(chip);
190 TRACE_RET(chip, retval);
191 }
192 } else {
193 sd_set_err_code(chip, SD_TO_ERR);
194 }
195 retval = STATUS_TIMEDOUT;
196 } else {
197 retval = STATUS_FAIL;
198 }
199 rtsx_clear_sd_error(chip);
200
201 TRACE_RET(chip, retval);
202 }
203
204 if (rsp_type == SD_RSP_TYPE_R0)
205 return STATUS_SUCCESS;
206
207 ptr = rtsx_get_cmd_data(chip) + 1;
208
209 if ((ptr[0] & 0xC0) != 0) {
210 sd_set_err_code(chip, SD_STS_ERR);
211 TRACE_RET(chip, STATUS_FAIL);
212 }
213
214 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
215 if (ptr[stat_idx] & SD_CRC7_ERR) {
216 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
217 sd_set_err_code(chip, SD_CRC_ERR);
218 TRACE_RET(chip, STATUS_FAIL);
219 }
220 if (rty_cnt < SD_MAX_RETRY_COUNT) {
221 wait_timeout(20);
222 rty_cnt++;
223 goto RTY_SEND_CMD;
224 } else {
225 sd_set_err_code(chip, SD_CRC_ERR);
226 TRACE_RET(chip, STATUS_FAIL);
227 }
228 }
229 }
230
231 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
232 if ((cmd_idx != SEND_RELATIVE_ADDR) &&
233 (cmd_idx != SEND_IF_COND)) {
234 if (cmd_idx != STOP_TRANSMISSION) {
235 if (ptr[1] & 0x80)
236 TRACE_RET(chip, STATUS_FAIL);
237 }
238 #ifdef SUPPORT_SD_LOCK
239 if (ptr[1] & 0x7D)
240 #else
241 if (ptr[1] & 0x7F)
242 #endif
243 {
244 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
245 ptr[1]);
246 TRACE_RET(chip, STATUS_FAIL);
247 }
248 if (ptr[2] & 0xFF) {
249 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
250 ptr[2]);
251 TRACE_RET(chip, STATUS_FAIL);
252 }
253 if (ptr[3] & 0x80) {
254 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
255 ptr[3]);
256 TRACE_RET(chip, STATUS_FAIL);
257 }
258 if (ptr[3] & 0x01)
259 sd_card->sd_data_buf_ready = 1;
260 else
261 sd_card->sd_data_buf_ready = 0;
262 }
263 }
264
265 if (rsp && rsp_len)
266 memcpy(rsp, ptr, rsp_len);
267
268 return STATUS_SUCCESS;
269 }
270
sd_read_data(struct rtsx_chip * chip,u8 trans_mode,u8 * cmd,int cmd_len,u16 byte_cnt,u16 blk_cnt,u8 bus_width,u8 * buf,int buf_len,int timeout)271 static int sd_read_data(struct rtsx_chip *chip,
272 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
273 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
274 int timeout)
275 {
276 struct sd_info *sd_card = &(chip->sd_card);
277 int retval;
278 int i;
279
280 sd_clr_err_code(chip);
281
282 if (!buf)
283 buf_len = 0;
284
285 if (buf_len > 512)
286 TRACE_RET(chip, STATUS_FAIL);
287
288 rtsx_init_cmd(chip);
289
290 if (cmd_len) {
291 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
292 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++)
293 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
294 0xFF, cmd[i]);
295 }
296 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
297 (u8)byte_cnt);
298 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
299 (u8)(byte_cnt >> 8));
300 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
301 (u8)blk_cnt);
302 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
303 (u8)(blk_cnt >> 8));
304
305 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
306
307 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
308 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
309 SD_CHECK_CRC7 | SD_RSP_LEN_6);
310 if (trans_mode != SD_TM_AUTO_TUNING)
311 rtsx_add_cmd(chip, WRITE_REG_CMD,
312 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
313
314 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
315 trans_mode | SD_TRANSFER_START);
316 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
317 SD_TRANSFER_END);
318
319 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
320 if (retval < 0) {
321 if (retval == -ETIMEDOUT) {
322 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
323 SD_RSP_TYPE_R1, NULL, 0);
324 }
325
326 TRACE_RET(chip, STATUS_FAIL);
327 }
328
329 if (buf && buf_len) {
330 retval = rtsx_read_ppbuf(chip, buf, buf_len);
331 if (retval != STATUS_SUCCESS)
332 TRACE_RET(chip, STATUS_FAIL);
333 }
334
335 return STATUS_SUCCESS;
336 }
337
sd_write_data(struct rtsx_chip * chip,u8 trans_mode,u8 * cmd,int cmd_len,u16 byte_cnt,u16 blk_cnt,u8 bus_width,u8 * buf,int buf_len,int timeout)338 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
339 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
340 u8 *buf, int buf_len, int timeout)
341 {
342 struct sd_info *sd_card = &(chip->sd_card);
343 int retval;
344 int i;
345
346 sd_clr_err_code(chip);
347
348 if (!buf)
349 buf_len = 0;
350
351 if (buf_len > 512) {
352 /* This function can't write data more than one page */
353 TRACE_RET(chip, STATUS_FAIL);
354 }
355
356 if (buf && buf_len) {
357 retval = rtsx_write_ppbuf(chip, buf, buf_len);
358 if (retval != STATUS_SUCCESS)
359 TRACE_RET(chip, STATUS_FAIL);
360 }
361
362 rtsx_init_cmd(chip);
363
364 if (cmd_len) {
365 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
366 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
367 rtsx_add_cmd(chip, WRITE_REG_CMD,
368 REG_SD_CMD0 + i, 0xFF, cmd[i]);
369 }
370 }
371 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
372 (u8)byte_cnt);
373 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
374 (u8)(byte_cnt >> 8));
375 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
376 (u8)blk_cnt);
377 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
378 (u8)(blk_cnt >> 8));
379
380 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
381
382 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
383 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
384 SD_CHECK_CRC7 | SD_RSP_LEN_6);
385
386 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
387 trans_mode | SD_TRANSFER_START);
388 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
389 SD_TRANSFER_END);
390
391 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
392 if (retval < 0) {
393 if (retval == -ETIMEDOUT) {
394 sd_send_cmd_get_rsp(chip, SEND_STATUS,
395 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
396 }
397
398 TRACE_RET(chip, STATUS_FAIL);
399 }
400
401 return STATUS_SUCCESS;
402 }
403
sd_check_csd(struct rtsx_chip * chip,char check_wp)404 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
405 {
406 struct sd_info *sd_card = &(chip->sd_card);
407 int retval;
408 int i;
409 u8 csd_ver, trans_speed;
410 u8 rsp[16];
411
412 for (i = 0; i < 6; i++) {
413 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
414 sd_set_err_code(chip, SD_NO_CARD);
415 TRACE_RET(chip, STATUS_FAIL);
416 }
417
418 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
419 SD_RSP_TYPE_R2, rsp, 16);
420 if (retval == STATUS_SUCCESS)
421 break;
422 }
423
424 if (i == 6)
425 TRACE_RET(chip, STATUS_FAIL);
426
427 memcpy(sd_card->raw_csd, rsp + 1, 15);
428
429 dev_dbg(rtsx_dev(chip), "CSD Response:\n");
430 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd);
431
432 csd_ver = (rsp[1] & 0xc0) >> 6;
433 dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
434
435 trans_speed = rsp[4];
436 if ((trans_speed & 0x07) == 0x02) {
437 if ((trans_speed & 0xf8) >= 0x30) {
438 if (chip->asic_code)
439 sd_card->sd_clock = 47;
440 else
441 sd_card->sd_clock = CLK_50;
442
443 } else if ((trans_speed & 0xf8) == 0x28) {
444 if (chip->asic_code)
445 sd_card->sd_clock = 39;
446 else
447 sd_card->sd_clock = CLK_40;
448
449 } else if ((trans_speed & 0xf8) == 0x20) {
450 if (chip->asic_code)
451 sd_card->sd_clock = 29;
452 else
453 sd_card->sd_clock = CLK_30;
454
455 } else if ((trans_speed & 0xf8) >= 0x10) {
456 if (chip->asic_code)
457 sd_card->sd_clock = 23;
458 else
459 sd_card->sd_clock = CLK_20;
460
461 } else if ((trans_speed & 0x08) >= 0x08) {
462 if (chip->asic_code)
463 sd_card->sd_clock = 19;
464 else
465 sd_card->sd_clock = CLK_20;
466 } else {
467 TRACE_RET(chip, STATUS_FAIL);
468 }
469 } else {
470 TRACE_RET(chip, STATUS_FAIL);
471 }
472
473 if (CHK_MMC_SECTOR_MODE(sd_card)) {
474 sd_card->capacity = 0;
475 } else {
476 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
477 u8 blk_size, c_size_mult;
478 u16 c_size;
479
480 blk_size = rsp[6] & 0x0F;
481 c_size = ((u16)(rsp[7] & 0x03) << 10)
482 + ((u16)rsp[8] << 2)
483 + ((u16)(rsp[9] & 0xC0) >> 6);
484 c_size_mult = (u8)((rsp[10] & 0x03) << 1);
485 c_size_mult += (rsp[11] & 0x80) >> 7;
486 sd_card->capacity = (((u32)(c_size + 1)) *
487 (1 << (c_size_mult + 2)))
488 << (blk_size - 9);
489 } else {
490 u32 total_sector = 0;
491
492 total_sector = (((u32)rsp[8] & 0x3f) << 16) |
493 ((u32)rsp[9] << 8) | (u32)rsp[10];
494 sd_card->capacity = (total_sector + 1) << 10;
495 }
496 }
497
498 if (check_wp) {
499 if (rsp[15] & 0x30)
500 chip->card_wp |= SD_CARD;
501
502 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
503 }
504
505 return STATUS_SUCCESS;
506 }
507
sd_set_sample_push_timing(struct rtsx_chip * chip)508 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
509 {
510 struct sd_info *sd_card = &(chip->sd_card);
511
512 u8 val = 0;
513
514 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
515 val |= 0x10;
516
517 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
518 if (chip->asic_code) {
519 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
520 if (val & 0x10)
521 val |= 0x04;
522 else
523 val |= 0x08;
524 }
525 } else {
526 if (val & 0x10)
527 val |= 0x04;
528 else
529 val |= 0x08;
530 }
531 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
532 SD_SAMPLE_POINT_DELAY) {
533 if (val & 0x10)
534 val |= 0x04;
535 else
536 val |= 0x08;
537 }
538
539 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
540
541 return STATUS_SUCCESS;
542 }
543
sd_choose_proper_clock(struct rtsx_chip * chip)544 static void sd_choose_proper_clock(struct rtsx_chip *chip)
545 {
546 struct sd_info *sd_card = &(chip->sd_card);
547
548 if (CHK_SD_SDR104(sd_card)) {
549 if (chip->asic_code)
550 sd_card->sd_clock = chip->asic_sd_sdr104_clk;
551 else
552 sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
553
554 } else if (CHK_SD_DDR50(sd_card)) {
555 if (chip->asic_code)
556 sd_card->sd_clock = chip->asic_sd_ddr50_clk;
557 else
558 sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
559
560 } else if (CHK_SD_SDR50(sd_card)) {
561 if (chip->asic_code)
562 sd_card->sd_clock = chip->asic_sd_sdr50_clk;
563 else
564 sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
565
566 } else if (CHK_SD_HS(sd_card)) {
567 if (chip->asic_code)
568 sd_card->sd_clock = chip->asic_sd_hs_clk;
569 else
570 sd_card->sd_clock = chip->fpga_sd_hs_clk;
571
572 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
573 if (chip->asic_code)
574 sd_card->sd_clock = chip->asic_mmc_52m_clk;
575 else
576 sd_card->sd_clock = chip->fpga_mmc_52m_clk;
577
578 } else if (CHK_MMC_26M(sd_card)) {
579 if (chip->asic_code)
580 sd_card->sd_clock = 48;
581 else
582 sd_card->sd_clock = CLK_50;
583 }
584 }
585
sd_set_clock_divider(struct rtsx_chip * chip,u8 clk_div)586 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
587 {
588 u8 mask = 0, val = 0;
589
590 mask = 0x60;
591 if (clk_div == SD_CLK_DIVIDE_0)
592 val = 0x00;
593 else if (clk_div == SD_CLK_DIVIDE_128)
594 val = 0x40;
595 else if (clk_div == SD_CLK_DIVIDE_256)
596 val = 0x20;
597
598 RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
599
600 return STATUS_SUCCESS;
601 }
602
sd_set_init_para(struct rtsx_chip * chip)603 static int sd_set_init_para(struct rtsx_chip *chip)
604 {
605 struct sd_info *sd_card = &(chip->sd_card);
606 int retval;
607
608 retval = sd_set_sample_push_timing(chip);
609 if (retval != STATUS_SUCCESS)
610 TRACE_RET(chip, STATUS_FAIL);
611
612 sd_choose_proper_clock(chip);
613
614 retval = switch_clock(chip, sd_card->sd_clock);
615 if (retval != STATUS_SUCCESS)
616 TRACE_RET(chip, STATUS_FAIL);
617
618 return STATUS_SUCCESS;
619 }
620
sd_select_card(struct rtsx_chip * chip,int select)621 int sd_select_card(struct rtsx_chip *chip, int select)
622 {
623 struct sd_info *sd_card = &(chip->sd_card);
624 int retval;
625 u8 cmd_idx, cmd_type;
626 u32 addr;
627
628 if (select) {
629 cmd_idx = SELECT_CARD;
630 cmd_type = SD_RSP_TYPE_R1;
631 addr = sd_card->sd_addr;
632 } else {
633 cmd_idx = DESELECT_CARD;
634 cmd_type = SD_RSP_TYPE_R0;
635 addr = 0;
636 }
637
638 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
639 if (retval != STATUS_SUCCESS)
640 TRACE_RET(chip, STATUS_FAIL);
641
642 return STATUS_SUCCESS;
643 }
644
645 #ifdef SUPPORT_SD_LOCK
sd_update_lock_status(struct rtsx_chip * chip)646 static int sd_update_lock_status(struct rtsx_chip *chip)
647 {
648 struct sd_info *sd_card = &(chip->sd_card);
649 int retval;
650 u8 rsp[5];
651
652 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
653 SD_RSP_TYPE_R1, rsp, 5);
654 if (retval != STATUS_SUCCESS)
655 TRACE_RET(chip, STATUS_FAIL);
656
657 if (rsp[1] & 0x02)
658 sd_card->sd_lock_status |= SD_LOCKED;
659 else
660 sd_card->sd_lock_status &= ~SD_LOCKED;
661
662 dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
663 sd_card->sd_lock_status);
664
665 if (rsp[1] & 0x01)
666 TRACE_RET(chip, STATUS_FAIL);
667
668 return STATUS_SUCCESS;
669 }
670 #endif
671
sd_wait_state_data_ready(struct rtsx_chip * chip,u8 state,u8 data_ready,int polling_cnt)672 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
673 u8 data_ready, int polling_cnt)
674 {
675 struct sd_info *sd_card = &(chip->sd_card);
676 int retval, i;
677 u8 rsp[5];
678
679 for (i = 0; i < polling_cnt; i++) {
680 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
681 sd_card->sd_addr, SD_RSP_TYPE_R1, rsp,
682 5);
683 if (retval != STATUS_SUCCESS)
684 TRACE_RET(chip, STATUS_FAIL);
685
686 if (((rsp[3] & 0x1E) == state) &&
687 ((rsp[3] & 0x01) == data_ready))
688 return STATUS_SUCCESS;
689 }
690
691 TRACE_RET(chip, STATUS_FAIL);
692 }
693
sd_change_bank_voltage(struct rtsx_chip * chip,u8 voltage)694 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
695 {
696 int retval;
697
698 if (voltage == SD_IO_3V3) {
699 if (chip->asic_code) {
700 retval = rtsx_write_phy_register(chip, 0x08,
701 0x4FC0 |
702 chip->phy_voltage);
703 if (retval != STATUS_SUCCESS)
704 TRACE_RET(chip, STATUS_FAIL);
705 } else {
706 RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
707 }
708 } else if (voltage == SD_IO_1V8) {
709 if (chip->asic_code) {
710 retval = rtsx_write_phy_register(chip, 0x08,
711 0x4C40 |
712 chip->phy_voltage);
713 if (retval != STATUS_SUCCESS)
714 TRACE_RET(chip, STATUS_FAIL);
715 } else {
716 RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8,
717 SD_IO_USING_1V8);
718 }
719 } else {
720 TRACE_RET(chip, STATUS_FAIL);
721 }
722
723 return STATUS_SUCCESS;
724 }
725
sd_voltage_switch(struct rtsx_chip * chip)726 static int sd_voltage_switch(struct rtsx_chip *chip)
727 {
728 int retval;
729 u8 stat;
730
731 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
732 SD_CLK_TOGGLE_EN);
733
734 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
735 NULL, 0);
736 if (retval != STATUS_SUCCESS)
737 TRACE_RET(chip, STATUS_FAIL);
738
739 udelay(chip->sd_voltage_switch_delay);
740
741 RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
742 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
743 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
744 TRACE_RET(chip, STATUS_FAIL);
745 }
746
747 RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
748 retval = sd_change_bank_voltage(chip, SD_IO_1V8);
749 if (retval != STATUS_SUCCESS)
750 TRACE_RET(chip, STATUS_FAIL);
751
752 wait_timeout(50);
753
754 RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
755 wait_timeout(10);
756
757 RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
758 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
759 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
760 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
761 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
762 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
763 rtsx_write_register(chip, SD_BUS_STAT,
764 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
765 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
766 TRACE_RET(chip, STATUS_FAIL);
767 }
768
769 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
770 0);
771
772 return STATUS_SUCCESS;
773 }
774
sd_reset_dcm(struct rtsx_chip * chip,u8 tune_dir)775 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
776 {
777 if (tune_dir == TUNE_RX) {
778 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
779 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
780 } else {
781 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
782 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
783 }
784
785 return STATUS_SUCCESS;
786 }
787
sd_change_phase(struct rtsx_chip * chip,u8 sample_point,u8 tune_dir)788 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
789 {
790 struct sd_info *sd_card = &(chip->sd_card);
791 u16 SD_VP_CTL, SD_DCMPS_CTL;
792 u8 val;
793 int retval;
794 int ddr_rx = 0;
795
796 dev_dbg(rtsx_dev(chip), "sd_change_phase (sample_point = %d, tune_dir = %d)\n",
797 sample_point, tune_dir);
798
799 if (tune_dir == TUNE_RX) {
800 SD_VP_CTL = SD_VPRX_CTL;
801 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
802 if (CHK_SD_DDR50(sd_card))
803 ddr_rx = 1;
804 } else {
805 SD_VP_CTL = SD_VPTX_CTL;
806 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
807 }
808
809 if (chip->asic_code) {
810 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
811 RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
812 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
813 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET,
814 PHASE_NOT_RESET);
815 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
816 } else {
817 rtsx_read_register(chip, SD_VP_CTL, &val);
818 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
819 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
820 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
821
822 if (ddr_rx) {
823 RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE,
824 PHASE_CHANGE);
825 udelay(50);
826 RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
827 PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
828 } else {
829 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
830 udelay(50);
831 RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
832 PHASE_NOT_RESET | sample_point);
833 }
834 udelay(100);
835
836 rtsx_init_cmd(chip);
837 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
838 DCMPS_CHANGE);
839 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
840 DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
841 retval = rtsx_send_cmd(chip, SD_CARD, 100);
842 if (retval != STATUS_SUCCESS)
843 TRACE_GOTO(chip, Fail);
844
845 val = *rtsx_get_cmd_data(chip);
846 if (val & DCMPS_ERROR)
847 TRACE_GOTO(chip, Fail);
848
849 if ((val & DCMPS_CURRENT_PHASE) != sample_point)
850 TRACE_GOTO(chip, Fail);
851
852 RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
853 if (ddr_rx)
854 RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
855 else
856 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
857
858 udelay(50);
859 }
860
861 RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
862
863 return STATUS_SUCCESS;
864
865 Fail:
866 rtsx_read_register(chip, SD_VP_CTL, &val);
867 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
868 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
869 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
870
871 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
872 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
873 wait_timeout(10);
874 sd_reset_dcm(chip, tune_dir);
875 return STATUS_FAIL;
876 }
877
sd_check_spec(struct rtsx_chip * chip,u8 bus_width)878 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
879 {
880 struct sd_info *sd_card = &(chip->sd_card);
881 int retval;
882 u8 cmd[5], buf[8];
883
884 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
885 SD_RSP_TYPE_R1, NULL, 0);
886 if (retval != STATUS_SUCCESS)
887 TRACE_RET(chip, STATUS_FAIL);
888
889 cmd[0] = 0x40 | SEND_SCR;
890 cmd[1] = 0;
891 cmd[2] = 0;
892 cmd[3] = 0;
893 cmd[4] = 0;
894
895 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
896 buf, 8, 250);
897 if (retval != STATUS_SUCCESS) {
898 rtsx_clear_sd_error(chip);
899 TRACE_RET(chip, STATUS_FAIL);
900 }
901
902 memcpy(sd_card->raw_scr, buf, 8);
903
904 if ((buf[0] & 0x0F) == 0)
905 TRACE_RET(chip, STATUS_FAIL);
906
907 return STATUS_SUCCESS;
908 }
909
sd_query_switch_result(struct rtsx_chip * chip,u8 func_group,u8 func_to_switch,u8 * buf,int buf_len)910 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
911 u8 func_to_switch, u8 *buf, int buf_len)
912 {
913 u8 support_mask = 0, query_switch = 0, switch_busy = 0;
914 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
915
916 if (func_group == SD_FUNC_GROUP_1) {
917 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
918 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
919 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
920
921 switch (func_to_switch) {
922 case HS_SUPPORT:
923 support_mask = HS_SUPPORT_MASK;
924 query_switch = HS_QUERY_SWITCH_OK;
925 switch_busy = HS_SWITCH_BUSY;
926 break;
927
928 case SDR50_SUPPORT:
929 support_mask = SDR50_SUPPORT_MASK;
930 query_switch = SDR50_QUERY_SWITCH_OK;
931 switch_busy = SDR50_SWITCH_BUSY;
932 break;
933
934 case SDR104_SUPPORT:
935 support_mask = SDR104_SUPPORT_MASK;
936 query_switch = SDR104_QUERY_SWITCH_OK;
937 switch_busy = SDR104_SWITCH_BUSY;
938 break;
939
940 case DDR50_SUPPORT:
941 support_mask = DDR50_SUPPORT_MASK;
942 query_switch = DDR50_QUERY_SWITCH_OK;
943 switch_busy = DDR50_SWITCH_BUSY;
944 break;
945
946 default:
947 TRACE_RET(chip, STATUS_FAIL);
948 }
949 } else if (func_group == SD_FUNC_GROUP_3) {
950 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
951 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
952 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
953
954 switch (func_to_switch) {
955 case DRIVING_TYPE_A:
956 support_mask = DRIVING_TYPE_A_MASK;
957 query_switch = TYPE_A_QUERY_SWITCH_OK;
958 switch_busy = TYPE_A_SWITCH_BUSY;
959 break;
960
961 case DRIVING_TYPE_C:
962 support_mask = DRIVING_TYPE_C_MASK;
963 query_switch = TYPE_C_QUERY_SWITCH_OK;
964 switch_busy = TYPE_C_SWITCH_BUSY;
965 break;
966
967 case DRIVING_TYPE_D:
968 support_mask = DRIVING_TYPE_D_MASK;
969 query_switch = TYPE_D_QUERY_SWITCH_OK;
970 switch_busy = TYPE_D_SWITCH_BUSY;
971 break;
972
973 default:
974 TRACE_RET(chip, STATUS_FAIL);
975 }
976 } else if (func_group == SD_FUNC_GROUP_4) {
977 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
978 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
979 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
980
981 switch (func_to_switch) {
982 case CURRENT_LIMIT_400:
983 support_mask = CURRENT_LIMIT_400_MASK;
984 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
985 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
986 break;
987
988 case CURRENT_LIMIT_600:
989 support_mask = CURRENT_LIMIT_600_MASK;
990 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
991 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
992 break;
993
994 case CURRENT_LIMIT_800:
995 support_mask = CURRENT_LIMIT_800_MASK;
996 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
997 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
998 break;
999
1000 default:
1001 TRACE_RET(chip, STATUS_FAIL);
1002 }
1003 } else {
1004 TRACE_RET(chip, STATUS_FAIL);
1005 }
1006
1007 if (func_group == SD_FUNC_GROUP_1) {
1008 if (!(buf[support_offset] & support_mask) ||
1009 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1010 TRACE_RET(chip, STATUS_FAIL);
1011 }
1012 }
1013
1014 /* Check 'Busy Status' */
1015 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1016 ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1017 TRACE_RET(chip, STATUS_FAIL);
1018 }
1019
1020 return STATUS_SUCCESS;
1021 }
1022
sd_check_switch_mode(struct rtsx_chip * chip,u8 mode,u8 func_group,u8 func_to_switch,u8 bus_width)1023 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1024 u8 func_group, u8 func_to_switch, u8 bus_width)
1025 {
1026 struct sd_info *sd_card = &(chip->sd_card);
1027 int retval;
1028 u8 cmd[5], buf[64];
1029
1030 dev_dbg(rtsx_dev(chip), "sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1031 mode, func_group, func_to_switch);
1032
1033 cmd[0] = 0x40 | SWITCH;
1034 cmd[1] = mode;
1035
1036 if (func_group == SD_FUNC_GROUP_1) {
1037 cmd[2] = 0xFF;
1038 cmd[3] = 0xFF;
1039 cmd[4] = 0xF0 + func_to_switch;
1040 } else if (func_group == SD_FUNC_GROUP_3) {
1041 cmd[2] = 0xFF;
1042 cmd[3] = 0xF0 + func_to_switch;
1043 cmd[4] = 0xFF;
1044 } else if (func_group == SD_FUNC_GROUP_4) {
1045 cmd[2] = 0xFF;
1046 cmd[3] = 0x0F + (func_to_switch << 4);
1047 cmd[4] = 0xFF;
1048 } else {
1049 cmd[1] = SD_CHECK_MODE;
1050 cmd[2] = 0xFF;
1051 cmd[3] = 0xFF;
1052 cmd[4] = 0xFF;
1053 }
1054
1055 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1056 buf, 64, 250);
1057 if (retval != STATUS_SUCCESS) {
1058 rtsx_clear_sd_error(chip);
1059 TRACE_RET(chip, STATUS_FAIL);
1060 }
1061
1062 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
1063
1064 if (func_group == NO_ARGUMENT) {
1065 sd_card->func_group1_mask = buf[0x0D];
1066 sd_card->func_group2_mask = buf[0x0B];
1067 sd_card->func_group3_mask = buf[0x09];
1068 sd_card->func_group4_mask = buf[0x07];
1069
1070 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1071 buf[0x0D]);
1072 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1073 buf[0x0B]);
1074 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1075 buf[0x09]);
1076 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1077 buf[0x07]);
1078 } else {
1079 /* Maximum current consumption, check whether current is
1080 * acceptable; bit[511:496] = 0x0000 means some error happened.
1081 */
1082 u16 cc = ((u16)buf[0] << 8) | buf[1];
1083
1084 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1085 cc);
1086 if ((cc == 0) || (cc > 800))
1087 TRACE_RET(chip, STATUS_FAIL);
1088
1089 retval = sd_query_switch_result(chip, func_group,
1090 func_to_switch, buf, 64);
1091 if (retval != STATUS_SUCCESS)
1092 TRACE_RET(chip, STATUS_FAIL);
1093
1094 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1095 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK,
1096 chip->sd_800mA_ocp_thd);
1097 RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK,
1098 PMOS_STRG_800mA);
1099 }
1100 }
1101
1102 return STATUS_SUCCESS;
1103 }
1104
downgrade_switch_mode(u8 func_group,u8 func_to_switch)1105 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1106 {
1107 if (func_group == SD_FUNC_GROUP_1) {
1108 if (func_to_switch > HS_SUPPORT)
1109 func_to_switch--;
1110
1111 } else if (func_group == SD_FUNC_GROUP_4) {
1112 if (func_to_switch > CURRENT_LIMIT_200)
1113 func_to_switch--;
1114 }
1115
1116 return func_to_switch;
1117 }
1118
sd_check_switch(struct rtsx_chip * chip,u8 func_group,u8 func_to_switch,u8 bus_width)1119 static int sd_check_switch(struct rtsx_chip *chip,
1120 u8 func_group, u8 func_to_switch, u8 bus_width)
1121 {
1122 int retval;
1123 int i;
1124 int switch_good = 0;
1125
1126 for (i = 0; i < 3; i++) {
1127 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1128 sd_set_err_code(chip, SD_NO_CARD);
1129 TRACE_RET(chip, STATUS_FAIL);
1130 }
1131
1132 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1133 func_to_switch, bus_width);
1134 if (retval == STATUS_SUCCESS) {
1135 u8 stat;
1136
1137 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1138 func_group, func_to_switch, bus_width);
1139 if (retval == STATUS_SUCCESS) {
1140 switch_good = 1;
1141 break;
1142 }
1143
1144 RTSX_READ_REG(chip, SD_STAT1, &stat);
1145 if (stat & SD_CRC16_ERR) {
1146 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1147 TRACE_RET(chip, STATUS_FAIL);
1148 }
1149 }
1150
1151 func_to_switch = downgrade_switch_mode(func_group,
1152 func_to_switch);
1153
1154 wait_timeout(20);
1155 }
1156
1157 if (!switch_good)
1158 TRACE_RET(chip, STATUS_FAIL);
1159
1160 return STATUS_SUCCESS;
1161 }
1162
sd_switch_function(struct rtsx_chip * chip,u8 bus_width)1163 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1164 {
1165 struct sd_info *sd_card = &(chip->sd_card);
1166 int retval;
1167 int i;
1168 u8 func_to_switch = 0;
1169
1170 /* Get supported functions */
1171 retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1172 NO_ARGUMENT, NO_ARGUMENT, bus_width);
1173 if (retval != STATUS_SUCCESS)
1174 TRACE_RET(chip, STATUS_FAIL);
1175
1176 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1177
1178 /* Function Group 1: Access Mode */
1179 for (i = 0; i < 4; i++) {
1180 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1181 case SDR104_SUPPORT:
1182 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1183 && chip->sdr104_en) {
1184 func_to_switch = SDR104_SUPPORT;
1185 }
1186 break;
1187
1188 case DDR50_SUPPORT:
1189 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1190 && chip->ddr50_en) {
1191 func_to_switch = DDR50_SUPPORT;
1192 }
1193 break;
1194
1195 case SDR50_SUPPORT:
1196 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1197 && chip->sdr50_en) {
1198 func_to_switch = SDR50_SUPPORT;
1199 }
1200 break;
1201
1202 case HS_SUPPORT:
1203 if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1204 func_to_switch = HS_SUPPORT;
1205
1206 break;
1207
1208 default:
1209 continue;
1210 }
1211
1212
1213 if (func_to_switch)
1214 break;
1215
1216 }
1217 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1218 func_to_switch);
1219
1220 #ifdef SUPPORT_SD_LOCK
1221 if ((sd_card->sd_lock_status & SD_SDR_RST)
1222 && (DDR50_SUPPORT == func_to_switch)
1223 && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1224 func_to_switch = SDR50_SUPPORT;
1225 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1226 }
1227 #endif
1228
1229 if (func_to_switch) {
1230 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1231 bus_width);
1232 if (retval != STATUS_SUCCESS) {
1233 if (func_to_switch == SDR104_SUPPORT) {
1234 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1235 } else if (func_to_switch == DDR50_SUPPORT) {
1236 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1237 DDR50_SUPPORT_MASK;
1238 } else if (func_to_switch == SDR50_SUPPORT) {
1239 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1240 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1241 }
1242 TRACE_RET(chip, STATUS_FAIL);
1243 }
1244
1245 if (func_to_switch == SDR104_SUPPORT)
1246 SET_SD_SDR104(sd_card);
1247 else if (func_to_switch == DDR50_SUPPORT)
1248 SET_SD_DDR50(sd_card);
1249 else if (func_to_switch == SDR50_SUPPORT)
1250 SET_SD_SDR50(sd_card);
1251 else
1252 SET_SD_HS(sd_card);
1253 }
1254
1255 if (CHK_SD_DDR50(sd_card)) {
1256 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1257 retval = sd_set_sample_push_timing(chip);
1258 if (retval != STATUS_SUCCESS)
1259 TRACE_RET(chip, STATUS_FAIL);
1260 }
1261
1262 if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1263 /* Do not try to switch current limit if the card doesn't
1264 * support UHS mode or we don't want it to support UHS mode
1265 */
1266 return STATUS_SUCCESS;
1267 }
1268
1269 /* Function Group 4: Current Limit */
1270 func_to_switch = 0xFF;
1271
1272 for (i = 0; i < 4; i++) {
1273 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1274 case CURRENT_LIMIT_800:
1275 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1276 func_to_switch = CURRENT_LIMIT_800;
1277
1278 break;
1279
1280 case CURRENT_LIMIT_600:
1281 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1282 func_to_switch = CURRENT_LIMIT_600;
1283
1284 break;
1285
1286 case CURRENT_LIMIT_400:
1287 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1288 func_to_switch = CURRENT_LIMIT_400;
1289
1290 break;
1291
1292 case CURRENT_LIMIT_200:
1293 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1294 func_to_switch = CURRENT_LIMIT_200;
1295
1296 break;
1297
1298 default:
1299 continue;
1300 }
1301
1302 if (func_to_switch != 0xFF)
1303 break;
1304 }
1305
1306 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1307 func_to_switch);
1308
1309 if (func_to_switch <= CURRENT_LIMIT_800) {
1310 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1311 bus_width);
1312 if (retval != STATUS_SUCCESS) {
1313 if (sd_check_err_code(chip, SD_NO_CARD))
1314 TRACE_RET(chip, STATUS_FAIL);
1315 }
1316 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1317 retval);
1318 }
1319
1320 if (CHK_SD_DDR50(sd_card))
1321 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1322
1323 return STATUS_SUCCESS;
1324 }
1325
sd_wait_data_idle(struct rtsx_chip * chip)1326 static int sd_wait_data_idle(struct rtsx_chip *chip)
1327 {
1328 int retval = STATUS_TIMEDOUT;
1329 int i;
1330 u8 val = 0;
1331
1332 for (i = 0; i < 100; i++) {
1333 RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1334 if (val & SD_DATA_IDLE) {
1335 retval = STATUS_SUCCESS;
1336 break;
1337 }
1338 udelay(100);
1339 }
1340 dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1341
1342 return retval;
1343 }
1344
sd_sdr_tuning_rx_cmd(struct rtsx_chip * chip,u8 sample_point)1345 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1346 {
1347 int retval;
1348 u8 cmd[5];
1349
1350 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1351 if (retval != STATUS_SUCCESS)
1352 TRACE_RET(chip, STATUS_FAIL);
1353
1354 cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1355 cmd[1] = 0;
1356 cmd[2] = 0;
1357 cmd[3] = 0;
1358 cmd[4] = 0;
1359
1360 retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1361 cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1362 if (retval != STATUS_SUCCESS) {
1363 (void)sd_wait_data_idle(chip);
1364
1365 rtsx_clear_sd_error(chip);
1366 TRACE_RET(chip, STATUS_FAIL);
1367 }
1368
1369 return STATUS_SUCCESS;
1370 }
1371
sd_ddr_tuning_rx_cmd(struct rtsx_chip * chip,u8 sample_point)1372 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1373 {
1374 struct sd_info *sd_card = &(chip->sd_card);
1375 int retval;
1376 u8 cmd[5];
1377
1378 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1379 if (retval != STATUS_SUCCESS)
1380 TRACE_RET(chip, STATUS_FAIL);
1381
1382 dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1383
1384 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1385 SD_RSP_TYPE_R1, NULL, 0);
1386 if (retval != STATUS_SUCCESS)
1387 TRACE_RET(chip, STATUS_FAIL);
1388
1389 cmd[0] = 0x40 | SD_STATUS;
1390 cmd[1] = 0;
1391 cmd[2] = 0;
1392 cmd[3] = 0;
1393 cmd[4] = 0;
1394
1395 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1396 cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1397 if (retval != STATUS_SUCCESS) {
1398 (void)sd_wait_data_idle(chip);
1399
1400 rtsx_clear_sd_error(chip);
1401 TRACE_RET(chip, STATUS_FAIL);
1402 }
1403
1404 return STATUS_SUCCESS;
1405 }
1406
mmc_ddr_tunning_rx_cmd(struct rtsx_chip * chip,u8 sample_point)1407 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1408 {
1409 struct sd_info *sd_card = &(chip->sd_card);
1410 int retval;
1411 u8 cmd[5], bus_width;
1412
1413 if (CHK_MMC_8BIT(sd_card))
1414 bus_width = SD_BUS_WIDTH_8;
1415 else if (CHK_MMC_4BIT(sd_card))
1416 bus_width = SD_BUS_WIDTH_4;
1417 else
1418 bus_width = SD_BUS_WIDTH_1;
1419
1420 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1421 if (retval != STATUS_SUCCESS)
1422 TRACE_RET(chip, STATUS_FAIL);
1423
1424 dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1425
1426 cmd[0] = 0x40 | SEND_EXT_CSD;
1427 cmd[1] = 0;
1428 cmd[2] = 0;
1429 cmd[3] = 0;
1430 cmd[4] = 0;
1431
1432 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1433 cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1434 if (retval != STATUS_SUCCESS) {
1435 (void)sd_wait_data_idle(chip);
1436
1437 rtsx_clear_sd_error(chip);
1438 TRACE_RET(chip, STATUS_FAIL);
1439 }
1440
1441 return STATUS_SUCCESS;
1442 }
1443
sd_sdr_tuning_tx_cmd(struct rtsx_chip * chip,u8 sample_point)1444 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1445 {
1446 struct sd_info *sd_card = &(chip->sd_card);
1447 int retval;
1448
1449 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1450 if (retval != STATUS_SUCCESS)
1451 TRACE_RET(chip, STATUS_FAIL);
1452
1453 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1454 SD_RSP_80CLK_TIMEOUT_EN);
1455
1456 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1457 SD_RSP_TYPE_R1, NULL, 0);
1458 if (retval != STATUS_SUCCESS) {
1459 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1460 rtsx_write_register(chip, SD_CFG3,
1461 SD_RSP_80CLK_TIMEOUT_EN, 0);
1462 TRACE_RET(chip, STATUS_FAIL);
1463 }
1464 }
1465
1466 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1467
1468 return STATUS_SUCCESS;
1469 }
1470
sd_ddr_tuning_tx_cmd(struct rtsx_chip * chip,u8 sample_point)1471 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1472 {
1473 struct sd_info *sd_card = &(chip->sd_card);
1474 int retval;
1475 u8 cmd[5], bus_width;
1476
1477 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1478 if (retval != STATUS_SUCCESS)
1479 TRACE_RET(chip, STATUS_FAIL);
1480
1481 if (CHK_SD(sd_card)) {
1482 bus_width = SD_BUS_WIDTH_4;
1483 } else {
1484 if (CHK_MMC_8BIT(sd_card))
1485 bus_width = SD_BUS_WIDTH_8;
1486 else if (CHK_MMC_4BIT(sd_card))
1487 bus_width = SD_BUS_WIDTH_4;
1488 else
1489 bus_width = SD_BUS_WIDTH_1;
1490 }
1491
1492 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1493 if (retval != STATUS_SUCCESS)
1494 TRACE_RET(chip, STATUS_FAIL);
1495
1496 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1497 SD_RSP_80CLK_TIMEOUT_EN);
1498
1499 cmd[0] = 0x40 | PROGRAM_CSD;
1500 cmd[1] = 0;
1501 cmd[2] = 0;
1502 cmd[3] = 0;
1503 cmd[4] = 0;
1504
1505 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1506 cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1507 if (retval != STATUS_SUCCESS) {
1508 rtsx_clear_sd_error(chip);
1509 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1510 TRACE_RET(chip, STATUS_FAIL);
1511 }
1512
1513 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1514
1515 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1516 NULL, 0);
1517
1518 return STATUS_SUCCESS;
1519 }
1520
sd_search_final_phase(struct rtsx_chip * chip,u32 phase_map,u8 tune_dir)1521 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1522 u8 tune_dir)
1523 {
1524 struct sd_info *sd_card = &(chip->sd_card);
1525 struct timing_phase_path path[MAX_PHASE + 1];
1526 int i, j, cont_path_cnt;
1527 int new_block, max_len, final_path_idx;
1528 u8 final_phase = 0xFF;
1529
1530 if (phase_map == 0xFFFFFFFF) {
1531 if (tune_dir == TUNE_RX)
1532 final_phase = (u8)chip->sd_default_rx_phase;
1533 else
1534 final_phase = (u8)chip->sd_default_tx_phase;
1535
1536 goto Search_Finish;
1537 }
1538
1539 cont_path_cnt = 0;
1540 new_block = 1;
1541 j = 0;
1542 for (i = 0; i < MAX_PHASE + 1; i++) {
1543 if (phase_map & (1 << i)) {
1544 if (new_block) {
1545 new_block = 0;
1546 j = cont_path_cnt++;
1547 path[j].start = i;
1548 path[j].end = i;
1549 } else {
1550 path[j].end = i;
1551 }
1552 } else {
1553 new_block = 1;
1554 if (cont_path_cnt) {
1555 int idx = cont_path_cnt - 1;
1556
1557 path[idx].len = path[idx].end -
1558 path[idx].start + 1;
1559 path[idx].mid = path[idx].start +
1560 path[idx].len / 2;
1561 }
1562 }
1563 }
1564
1565 if (cont_path_cnt == 0) {
1566 dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1567 goto Search_Finish;
1568 } else {
1569 int idx = cont_path_cnt - 1;
1570
1571 path[idx].len = path[idx].end - path[idx].start + 1;
1572 path[idx].mid = path[idx].start + path[idx].len / 2;
1573 }
1574
1575 if ((path[0].start == 0) &&
1576 (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1577 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1578 path[0].len += path[cont_path_cnt - 1].len;
1579 path[0].mid = path[0].start + path[0].len / 2;
1580 if (path[0].mid < 0)
1581 path[0].mid += MAX_PHASE + 1;
1582
1583 cont_path_cnt--;
1584 }
1585
1586 max_len = 0;
1587 final_phase = 0;
1588 final_path_idx = 0;
1589 for (i = 0; i < cont_path_cnt; i++) {
1590 if (path[i].len > max_len) {
1591 max_len = path[i].len;
1592 final_phase = (u8)path[i].mid;
1593 final_path_idx = i;
1594 }
1595
1596 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1597 i, path[i].start);
1598 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1599 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1600 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1601 dev_dbg(rtsx_dev(chip), "\n");
1602 }
1603
1604 if (tune_dir == TUNE_TX) {
1605 if (CHK_SD_SDR104(sd_card)) {
1606 if (max_len > 15) {
1607 int temp_mid = (max_len - 16) / 2;
1608 int temp_final_phase =
1609 path[final_path_idx].end -
1610 (max_len - (6 + temp_mid));
1611
1612 if (temp_final_phase < 0)
1613 final_phase = (u8)(temp_final_phase +
1614 MAX_PHASE + 1);
1615 else
1616 final_phase = (u8)temp_final_phase;
1617 }
1618 } else if (CHK_SD_SDR50(sd_card)) {
1619 if (max_len > 12) {
1620 int temp_mid = (max_len - 13) / 2;
1621 int temp_final_phase =
1622 path[final_path_idx].end -
1623 (max_len - (3 + temp_mid));
1624
1625 if (temp_final_phase < 0)
1626 final_phase = (u8)(temp_final_phase +
1627 MAX_PHASE + 1);
1628 else
1629 final_phase = (u8)temp_final_phase;
1630 }
1631 }
1632 }
1633
1634 Search_Finish:
1635 dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1636 return final_phase;
1637 }
1638
sd_tuning_rx(struct rtsx_chip * chip)1639 static int sd_tuning_rx(struct rtsx_chip *chip)
1640 {
1641 struct sd_info *sd_card = &(chip->sd_card);
1642 int retval;
1643 int i, j;
1644 u32 raw_phase_map[3], phase_map;
1645 u8 final_phase;
1646 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1647
1648 if (CHK_SD(sd_card)) {
1649 if (CHK_SD_DDR50(sd_card))
1650 tuning_cmd = sd_ddr_tuning_rx_cmd;
1651 else
1652 tuning_cmd = sd_sdr_tuning_rx_cmd;
1653
1654 } else {
1655 if (CHK_MMC_DDR52(sd_card))
1656 tuning_cmd = mmc_ddr_tunning_rx_cmd;
1657 else
1658 TRACE_RET(chip, STATUS_FAIL);
1659 }
1660
1661 for (i = 0; i < 3; i++) {
1662 raw_phase_map[i] = 0;
1663 for (j = MAX_PHASE; j >= 0; j--) {
1664 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1665 sd_set_err_code(chip, SD_NO_CARD);
1666 TRACE_RET(chip, STATUS_FAIL);
1667 }
1668
1669 retval = tuning_cmd(chip, (u8)j);
1670 if (retval == STATUS_SUCCESS)
1671 raw_phase_map[i] |= 1 << j;
1672 }
1673 }
1674
1675 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1676 for (i = 0; i < 3; i++)
1677 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1678 i, raw_phase_map[i]);
1679
1680 dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1681
1682 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1683 if (final_phase == 0xFF)
1684 TRACE_RET(chip, STATUS_FAIL);
1685
1686 retval = sd_change_phase(chip, final_phase, TUNE_RX);
1687 if (retval != STATUS_SUCCESS)
1688 TRACE_RET(chip, STATUS_FAIL);
1689
1690 return STATUS_SUCCESS;
1691 }
1692
sd_ddr_pre_tuning_tx(struct rtsx_chip * chip)1693 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1694 {
1695 struct sd_info *sd_card = &(chip->sd_card);
1696 int retval;
1697 int i;
1698 u32 phase_map;
1699 u8 final_phase;
1700
1701 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1702 SD_RSP_80CLK_TIMEOUT_EN);
1703
1704 phase_map = 0;
1705 for (i = MAX_PHASE; i >= 0; i--) {
1706 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1707 sd_set_err_code(chip, SD_NO_CARD);
1708 rtsx_write_register(chip, SD_CFG3,
1709 SD_RSP_80CLK_TIMEOUT_EN, 0);
1710 TRACE_RET(chip, STATUS_FAIL);
1711 }
1712
1713 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1714 if (retval != STATUS_SUCCESS)
1715 continue;
1716
1717 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
1718 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL,
1719 0);
1720 if ((retval == STATUS_SUCCESS) ||
1721 !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1722 phase_map |= 1 << i;
1723 }
1724
1725 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1726
1727 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
1728 phase_map);
1729
1730 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1731 if (final_phase == 0xFF)
1732 TRACE_RET(chip, STATUS_FAIL);
1733
1734 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1735 if (retval != STATUS_SUCCESS)
1736 TRACE_RET(chip, STATUS_FAIL);
1737
1738 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
1739 (int)final_phase);
1740
1741 return STATUS_SUCCESS;
1742 }
1743
sd_tuning_tx(struct rtsx_chip * chip)1744 static int sd_tuning_tx(struct rtsx_chip *chip)
1745 {
1746 struct sd_info *sd_card = &(chip->sd_card);
1747 int retval;
1748 int i, j;
1749 u32 raw_phase_map[3], phase_map;
1750 u8 final_phase;
1751 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1752
1753 if (CHK_SD(sd_card)) {
1754 if (CHK_SD_DDR50(sd_card))
1755 tuning_cmd = sd_ddr_tuning_tx_cmd;
1756 else
1757 tuning_cmd = sd_sdr_tuning_tx_cmd;
1758
1759 } else {
1760 if (CHK_MMC_DDR52(sd_card))
1761 tuning_cmd = sd_ddr_tuning_tx_cmd;
1762 else
1763 TRACE_RET(chip, STATUS_FAIL);
1764 }
1765
1766 for (i = 0; i < 3; i++) {
1767 raw_phase_map[i] = 0;
1768 for (j = MAX_PHASE; j >= 0; j--) {
1769 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1770 sd_set_err_code(chip, SD_NO_CARD);
1771 rtsx_write_register(chip, SD_CFG3,
1772 SD_RSP_80CLK_TIMEOUT_EN, 0);
1773 TRACE_RET(chip, STATUS_FAIL);
1774 }
1775
1776 retval = tuning_cmd(chip, (u8)j);
1777 if (retval == STATUS_SUCCESS)
1778 raw_phase_map[i] |= 1 << j;
1779 }
1780 }
1781
1782 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1783 for (i = 0; i < 3; i++)
1784 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
1785 i, raw_phase_map[i]);
1786
1787 dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
1788
1789 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1790 if (final_phase == 0xFF)
1791 TRACE_RET(chip, STATUS_FAIL);
1792
1793 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1794 if (retval != STATUS_SUCCESS)
1795 TRACE_RET(chip, STATUS_FAIL);
1796
1797 return STATUS_SUCCESS;
1798 }
1799
sd_sdr_tuning(struct rtsx_chip * chip)1800 static int sd_sdr_tuning(struct rtsx_chip *chip)
1801 {
1802 int retval;
1803
1804 retval = sd_tuning_tx(chip);
1805 if (retval != STATUS_SUCCESS)
1806 TRACE_RET(chip, STATUS_FAIL);
1807
1808 retval = sd_tuning_rx(chip);
1809 if (retval != STATUS_SUCCESS)
1810 TRACE_RET(chip, STATUS_FAIL);
1811
1812 return STATUS_SUCCESS;
1813 }
1814
sd_ddr_tuning(struct rtsx_chip * chip)1815 static int sd_ddr_tuning(struct rtsx_chip *chip)
1816 {
1817 int retval;
1818
1819 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1820 retval = sd_ddr_pre_tuning_tx(chip);
1821 if (retval != STATUS_SUCCESS)
1822 TRACE_RET(chip, STATUS_FAIL);
1823 } else {
1824 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
1825 TUNE_TX);
1826 if (retval != STATUS_SUCCESS)
1827 TRACE_RET(chip, STATUS_FAIL);
1828 }
1829
1830 retval = sd_tuning_rx(chip);
1831 if (retval != STATUS_SUCCESS)
1832 TRACE_RET(chip, STATUS_FAIL);
1833
1834 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1835 retval = sd_tuning_tx(chip);
1836 if (retval != STATUS_SUCCESS)
1837 TRACE_RET(chip, STATUS_FAIL);
1838 }
1839
1840 return STATUS_SUCCESS;
1841 }
1842
mmc_ddr_tuning(struct rtsx_chip * chip)1843 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1844 {
1845 int retval;
1846
1847 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1848 retval = sd_ddr_pre_tuning_tx(chip);
1849 if (retval != STATUS_SUCCESS)
1850 TRACE_RET(chip, STATUS_FAIL);
1851 } else {
1852 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
1853 TUNE_TX);
1854 if (retval != STATUS_SUCCESS)
1855 TRACE_RET(chip, STATUS_FAIL);
1856 }
1857
1858 retval = sd_tuning_rx(chip);
1859 if (retval != STATUS_SUCCESS)
1860 TRACE_RET(chip, STATUS_FAIL);
1861
1862 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1863 retval = sd_tuning_tx(chip);
1864 if (retval != STATUS_SUCCESS)
1865 TRACE_RET(chip, STATUS_FAIL);
1866 }
1867
1868 return STATUS_SUCCESS;
1869 }
1870
sd_switch_clock(struct rtsx_chip * chip)1871 int sd_switch_clock(struct rtsx_chip *chip)
1872 {
1873 struct sd_info *sd_card = &(chip->sd_card);
1874 int retval;
1875 int re_tuning = 0;
1876
1877 retval = select_card(chip, SD_CARD);
1878 if (retval != STATUS_SUCCESS)
1879 TRACE_RET(chip, STATUS_FAIL);
1880
1881 retval = switch_clock(chip, sd_card->sd_clock);
1882 if (retval != STATUS_SUCCESS)
1883 TRACE_RET(chip, STATUS_FAIL);
1884
1885 if (re_tuning) {
1886 if (CHK_SD(sd_card)) {
1887 if (CHK_SD_DDR50(sd_card))
1888 retval = sd_ddr_tuning(chip);
1889 else
1890 retval = sd_sdr_tuning(chip);
1891 } else {
1892 if (CHK_MMC_DDR52(sd_card))
1893 retval = mmc_ddr_tuning(chip);
1894 }
1895
1896 if (retval != STATUS_SUCCESS)
1897 TRACE_RET(chip, STATUS_FAIL);
1898 }
1899
1900 return STATUS_SUCCESS;
1901 }
1902
sd_prepare_reset(struct rtsx_chip * chip)1903 static int sd_prepare_reset(struct rtsx_chip *chip)
1904 {
1905 struct sd_info *sd_card = &(chip->sd_card);
1906 int retval;
1907
1908 if (chip->asic_code)
1909 sd_card->sd_clock = 29;
1910 else
1911 sd_card->sd_clock = CLK_30;
1912
1913 sd_card->sd_type = 0;
1914 sd_card->seq_mode = 0;
1915 sd_card->sd_data_buf_ready = 0;
1916 sd_card->capacity = 0;
1917
1918 #ifdef SUPPORT_SD_LOCK
1919 sd_card->sd_lock_status = 0;
1920 sd_card->sd_erase_status = 0;
1921 #endif
1922
1923 chip->capacity[chip->card2lun[SD_CARD]] = 0;
1924 chip->sd_io = 0;
1925
1926 retval = sd_set_init_para(chip);
1927 if (retval != STATUS_SUCCESS)
1928 TRACE_RET(chip, retval);
1929
1930 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
1931
1932 RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
1933 SD_STOP | SD_CLR_ERR);
1934
1935 retval = select_card(chip, SD_CARD);
1936 if (retval != STATUS_SUCCESS)
1937 TRACE_RET(chip, STATUS_FAIL);
1938
1939 return STATUS_SUCCESS;
1940 }
1941
sd_pull_ctl_disable(struct rtsx_chip * chip)1942 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
1943 {
1944 if (CHECK_PID(chip, 0x5208)) {
1945 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
1946 XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
1947 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
1948 SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
1949 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
1950 SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
1951 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
1952 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
1953 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
1954 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
1955 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
1956 } else if (CHECK_PID(chip, 0x5288)) {
1957 if (CHECK_BARO_PKG(chip, QFN)) {
1958 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
1959 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
1960 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
1961 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
1962 }
1963 }
1964
1965 return STATUS_SUCCESS;
1966 }
1967
sd_pull_ctl_enable(struct rtsx_chip * chip)1968 int sd_pull_ctl_enable(struct rtsx_chip *chip)
1969 {
1970 int retval;
1971
1972 rtsx_init_cmd(chip);
1973
1974 if (CHECK_PID(chip, 0x5208)) {
1975 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
1976 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
1977 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
1978 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
1979 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
1980 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
1981 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
1982 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
1983 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
1984 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
1985 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
1986 MS_D5_PD | MS_D4_PD);
1987 } else if (CHECK_PID(chip, 0x5288)) {
1988 if (CHECK_BARO_PKG(chip, QFN)) {
1989 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
1990 0xA8);
1991 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
1992 0x5A);
1993 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
1994 0x95);
1995 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
1996 0xAA);
1997 }
1998 }
1999
2000 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2001 if (retval < 0)
2002 TRACE_RET(chip, STATUS_FAIL);
2003
2004 return STATUS_SUCCESS;
2005 }
2006
sd_init_power(struct rtsx_chip * chip)2007 static int sd_init_power(struct rtsx_chip *chip)
2008 {
2009 int retval;
2010
2011 retval = sd_power_off_card3v3(chip);
2012 if (retval != STATUS_SUCCESS)
2013 TRACE_RET(chip, STATUS_FAIL);
2014
2015 if (!chip->ft2_fast_mode)
2016 wait_timeout(250);
2017
2018 retval = enable_card_clock(chip, SD_CARD);
2019 if (retval != STATUS_SUCCESS)
2020 TRACE_RET(chip, STATUS_FAIL);
2021
2022 if (chip->asic_code) {
2023 retval = sd_pull_ctl_enable(chip);
2024 if (retval != STATUS_SUCCESS)
2025 TRACE_RET(chip, STATUS_FAIL);
2026 } else {
2027 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20,
2028 0);
2029 }
2030
2031 if (!chip->ft2_fast_mode) {
2032 retval = card_power_on(chip, SD_CARD);
2033 if (retval != STATUS_SUCCESS)
2034 TRACE_RET(chip, STATUS_FAIL);
2035
2036 wait_timeout(260);
2037
2038 #ifdef SUPPORT_OCP
2039 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2040 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2041 chip->ocp_stat);
2042 TRACE_RET(chip, STATUS_FAIL);
2043 }
2044 #endif
2045 }
2046
2047 RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2048
2049 return STATUS_SUCCESS;
2050 }
2051
sd_dummy_clock(struct rtsx_chip * chip)2052 static int sd_dummy_clock(struct rtsx_chip *chip)
2053 {
2054 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2055 wait_timeout(5);
2056 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2057
2058 return STATUS_SUCCESS;
2059 }
2060
sd_read_lba0(struct rtsx_chip * chip)2061 static int sd_read_lba0(struct rtsx_chip *chip)
2062 {
2063 struct sd_info *sd_card = &(chip->sd_card);
2064 int retval;
2065 u8 cmd[5], bus_width;
2066
2067 cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2068 cmd[1] = 0;
2069 cmd[2] = 0;
2070 cmd[3] = 0;
2071 cmd[4] = 0;
2072
2073 if (CHK_SD(sd_card)) {
2074 bus_width = SD_BUS_WIDTH_4;
2075 } else {
2076 if (CHK_MMC_8BIT(sd_card))
2077 bus_width = SD_BUS_WIDTH_8;
2078 else if (CHK_MMC_4BIT(sd_card))
2079 bus_width = SD_BUS_WIDTH_4;
2080 else
2081 bus_width = SD_BUS_WIDTH_1;
2082 }
2083
2084 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2085 5, 512, 1, bus_width, NULL, 0, 100);
2086 if (retval != STATUS_SUCCESS) {
2087 rtsx_clear_sd_error(chip);
2088 TRACE_RET(chip, STATUS_FAIL);
2089 }
2090
2091 return STATUS_SUCCESS;
2092 }
2093
sd_check_wp_state(struct rtsx_chip * chip)2094 static int sd_check_wp_state(struct rtsx_chip *chip)
2095 {
2096 struct sd_info *sd_card = &(chip->sd_card);
2097 int retval;
2098 u32 val;
2099 u16 sd_card_type;
2100 u8 cmd[5], buf[64];
2101
2102 retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2103 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2104 if (retval != STATUS_SUCCESS)
2105 TRACE_RET(chip, STATUS_FAIL);
2106
2107 cmd[0] = 0x40 | SD_STATUS;
2108 cmd[1] = 0;
2109 cmd[2] = 0;
2110 cmd[3] = 0;
2111 cmd[4] = 0;
2112
2113 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2114 SD_BUS_WIDTH_4, buf, 64, 250);
2115 if (retval != STATUS_SUCCESS) {
2116 rtsx_clear_sd_error(chip);
2117
2118 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2119 SD_RSP_TYPE_R1, NULL, 0);
2120 TRACE_RET(chip, STATUS_FAIL);
2121 }
2122
2123 dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2124 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
2125
2126 sd_card_type = ((u16)buf[2] << 8) | buf[3];
2127 dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2128 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2129 /* ROM card or OTP */
2130 chip->card_wp |= SD_CARD;
2131 }
2132
2133 /* Check SD Machanical Write-Protect Switch */
2134 val = rtsx_readl(chip, RTSX_BIPR);
2135 if (val & SD_WRITE_PROTECT)
2136 chip->card_wp |= SD_CARD;
2137
2138 return STATUS_SUCCESS;
2139 }
2140
reset_sd(struct rtsx_chip * chip)2141 static int reset_sd(struct rtsx_chip *chip)
2142 {
2143 struct sd_info *sd_card = &(chip->sd_card);
2144 int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2145 int sd_dont_switch = 0;
2146 int support_1v8 = 0;
2147 int try_sdio = 1;
2148 u8 rsp[16];
2149 u8 switch_bus_width;
2150 u32 voltage = 0;
2151 int sd20_mode = 0;
2152
2153 SET_SD(sd_card);
2154
2155 Switch_Fail:
2156
2157 i = 0;
2158 j = 0;
2159 k = 0;
2160 hi_cap_flow = 0;
2161
2162 #ifdef SUPPORT_SD_LOCK
2163 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2164 goto SD_UNLOCK_ENTRY;
2165 #endif
2166
2167 retval = sd_prepare_reset(chip);
2168 if (retval != STATUS_SUCCESS)
2169 TRACE_RET(chip, STATUS_FAIL);
2170
2171 retval = sd_dummy_clock(chip);
2172 if (retval != STATUS_SUCCESS)
2173 TRACE_RET(chip, STATUS_FAIL);
2174
2175 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2176 int rty_cnt = 0;
2177
2178 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2179 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2180 sd_set_err_code(chip, SD_NO_CARD);
2181 TRACE_RET(chip, STATUS_FAIL);
2182 }
2183
2184 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2185 SD_RSP_TYPE_R4, rsp, 5);
2186 if (retval == STATUS_SUCCESS) {
2187 int func_num = (rsp[1] >> 4) & 0x07;
2188
2189 if (func_num) {
2190 dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2191 func_num);
2192 chip->sd_io = 1;
2193 TRACE_RET(chip, STATUS_FAIL);
2194 }
2195
2196 break;
2197 }
2198
2199 sd_init_power(chip);
2200
2201 sd_dummy_clock(chip);
2202 }
2203
2204 dev_dbg(rtsx_dev(chip), "Normal card!\n");
2205 }
2206
2207 /* Start Initialization Process of SD Card */
2208 RTY_SD_RST:
2209 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2210 NULL, 0);
2211 if (retval != STATUS_SUCCESS)
2212 TRACE_RET(chip, STATUS_FAIL);
2213
2214 wait_timeout(20);
2215
2216 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2217 SD_RSP_TYPE_R7, rsp, 5);
2218 if (retval == STATUS_SUCCESS) {
2219 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2220 hi_cap_flow = 1;
2221 voltage = SUPPORT_VOLTAGE | 0x40000000;
2222 }
2223 }
2224
2225 if (!hi_cap_flow) {
2226 voltage = SUPPORT_VOLTAGE;
2227
2228 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2229 SD_RSP_TYPE_R0, NULL, 0);
2230 if (retval != STATUS_SUCCESS)
2231 TRACE_RET(chip, STATUS_FAIL);
2232
2233 wait_timeout(20);
2234 }
2235
2236 do {
2237 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2238 NULL, 0);
2239 if (retval != STATUS_SUCCESS) {
2240 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2241 sd_set_err_code(chip, SD_NO_CARD);
2242 TRACE_RET(chip, STATUS_FAIL);
2243 }
2244
2245 j++;
2246 if (j < 3)
2247 goto RTY_SD_RST;
2248 else
2249 TRACE_RET(chip, STATUS_FAIL);
2250 }
2251
2252 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2253 SD_RSP_TYPE_R3, rsp, 5);
2254 if (retval != STATUS_SUCCESS) {
2255 k++;
2256 if (k < 3)
2257 goto RTY_SD_RST;
2258 else
2259 TRACE_RET(chip, STATUS_FAIL);
2260 }
2261
2262 i++;
2263 wait_timeout(20);
2264 } while (!(rsp[1] & 0x80) && (i < 255));
2265
2266 if (i == 255)
2267 TRACE_RET(chip, STATUS_FAIL);
2268
2269 if (hi_cap_flow) {
2270 if (rsp[1] & 0x40)
2271 SET_SD_HCXC(sd_card);
2272 else
2273 CLR_SD_HCXC(sd_card);
2274
2275 support_1v8 = 0;
2276 } else {
2277 CLR_SD_HCXC(sd_card);
2278 support_1v8 = 0;
2279 }
2280 dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2281
2282 if (support_1v8) {
2283 retval = sd_voltage_switch(chip);
2284 if (retval != STATUS_SUCCESS)
2285 TRACE_RET(chip, STATUS_FAIL);
2286 }
2287
2288 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2289 NULL, 0);
2290 if (retval != STATUS_SUCCESS)
2291 TRACE_RET(chip, STATUS_FAIL);
2292
2293 for (i = 0; i < 3; i++) {
2294 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2295 SD_RSP_TYPE_R6, rsp, 5);
2296 if (retval != STATUS_SUCCESS)
2297 TRACE_RET(chip, STATUS_FAIL);
2298
2299 sd_card->sd_addr = (u32)rsp[1] << 24;
2300 sd_card->sd_addr += (u32)rsp[2] << 16;
2301
2302 if (sd_card->sd_addr)
2303 break;
2304 }
2305
2306 retval = sd_check_csd(chip, 1);
2307 if (retval != STATUS_SUCCESS)
2308 TRACE_RET(chip, STATUS_FAIL);
2309
2310 retval = sd_select_card(chip, 1);
2311 if (retval != STATUS_SUCCESS)
2312 TRACE_RET(chip, STATUS_FAIL);
2313
2314 #ifdef SUPPORT_SD_LOCK
2315 SD_UNLOCK_ENTRY:
2316 retval = sd_update_lock_status(chip);
2317 if (retval != STATUS_SUCCESS)
2318 TRACE_RET(chip, STATUS_FAIL);
2319
2320 if (sd_card->sd_lock_status & SD_LOCKED) {
2321 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2322 return STATUS_SUCCESS;
2323 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2324 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2325 }
2326 #endif
2327
2328 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2329 SD_RSP_TYPE_R1, NULL, 0);
2330 if (retval != STATUS_SUCCESS)
2331 TRACE_RET(chip, STATUS_FAIL);
2332
2333 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2334 SD_RSP_TYPE_R1, NULL, 0);
2335 if (retval != STATUS_SUCCESS)
2336 TRACE_RET(chip, STATUS_FAIL);
2337
2338 if (support_1v8) {
2339 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2340 SD_RSP_TYPE_R1, NULL, 0);
2341 if (retval != STATUS_SUCCESS)
2342 TRACE_RET(chip, STATUS_FAIL);
2343
2344 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2345 SD_RSP_TYPE_R1, NULL, 0);
2346 if (retval != STATUS_SUCCESS)
2347 TRACE_RET(chip, STATUS_FAIL);
2348
2349 switch_bus_width = SD_BUS_WIDTH_4;
2350 } else {
2351 switch_bus_width = SD_BUS_WIDTH_1;
2352 }
2353
2354 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2355 NULL, 0);
2356 if (retval != STATUS_SUCCESS)
2357 TRACE_RET(chip, STATUS_FAIL);
2358
2359 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2360 if (retval != STATUS_SUCCESS)
2361 TRACE_RET(chip, STATUS_FAIL);
2362
2363 if (!(sd_card->raw_csd[4] & 0x40))
2364 sd_dont_switch = 1;
2365
2366 if (!sd_dont_switch) {
2367 if (sd20_mode) {
2368 /* Set sd_switch_fail here, because we needn't
2369 * switch to UHS mode
2370 */
2371 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2372 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2373 }
2374
2375 /* Check the card whether follow SD1.1 spec or higher */
2376 retval = sd_check_spec(chip, switch_bus_width);
2377 if (retval == STATUS_SUCCESS) {
2378 retval = sd_switch_function(chip, switch_bus_width);
2379 if (retval != STATUS_SUCCESS) {
2380 sd_init_power(chip);
2381 sd_dont_switch = 1;
2382 try_sdio = 0;
2383
2384 goto Switch_Fail;
2385 }
2386 } else {
2387 if (support_1v8) {
2388 sd_init_power(chip);
2389 sd_dont_switch = 1;
2390 try_sdio = 0;
2391
2392 goto Switch_Fail;
2393 }
2394 }
2395 }
2396
2397 if (!support_1v8) {
2398 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2399 SD_RSP_TYPE_R1, NULL, 0);
2400 if (retval != STATUS_SUCCESS)
2401 TRACE_RET(chip, STATUS_FAIL);
2402
2403 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2404 SD_RSP_TYPE_R1, NULL, 0);
2405 if (retval != STATUS_SUCCESS)
2406 TRACE_RET(chip, STATUS_FAIL);
2407 }
2408
2409 #ifdef SUPPORT_SD_LOCK
2410 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2411 #endif
2412
2413 if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2414 int read_lba0 = 1;
2415
2416 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07,
2417 chip->sd30_drive_sel_1v8);
2418
2419 retval = sd_set_init_para(chip);
2420 if (retval != STATUS_SUCCESS)
2421 TRACE_RET(chip, STATUS_FAIL);
2422
2423 if (CHK_SD_DDR50(sd_card))
2424 retval = sd_ddr_tuning(chip);
2425 else
2426 retval = sd_sdr_tuning(chip);
2427
2428 if (retval != STATUS_SUCCESS) {
2429 if (sd20_mode) {
2430 TRACE_RET(chip, STATUS_FAIL);
2431 } else {
2432 retval = sd_init_power(chip);
2433 if (retval != STATUS_SUCCESS)
2434 TRACE_RET(chip, STATUS_FAIL);
2435
2436 try_sdio = 0;
2437 sd20_mode = 1;
2438 goto Switch_Fail;
2439 }
2440 }
2441
2442 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2443 SD_RSP_TYPE_R1, NULL, 0);
2444
2445 if (CHK_SD_DDR50(sd_card)) {
2446 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2447 if (retval != STATUS_SUCCESS)
2448 read_lba0 = 0;
2449 }
2450
2451 if (read_lba0) {
2452 retval = sd_read_lba0(chip);
2453 if (retval != STATUS_SUCCESS) {
2454 if (sd20_mode) {
2455 TRACE_RET(chip, STATUS_FAIL);
2456 } else {
2457 retval = sd_init_power(chip);
2458 if (retval != STATUS_SUCCESS)
2459 TRACE_RET(chip, STATUS_FAIL);
2460
2461 try_sdio = 0;
2462 sd20_mode = 1;
2463 goto Switch_Fail;
2464 }
2465 }
2466 }
2467 }
2468
2469 retval = sd_check_wp_state(chip);
2470 if (retval != STATUS_SUCCESS)
2471 TRACE_RET(chip, STATUS_FAIL);
2472
2473 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2474
2475 #ifdef SUPPORT_SD_LOCK
2476 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2477 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2478 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2479 }
2480 #endif
2481
2482 return STATUS_SUCCESS;
2483 }
2484
2485
mmc_test_switch_bus(struct rtsx_chip * chip,u8 width)2486 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2487 {
2488 struct sd_info *sd_card = &(chip->sd_card);
2489 int retval;
2490 u8 buf[8] = {0}, bus_width, *ptr;
2491 u16 byte_cnt;
2492 int len;
2493
2494 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2495 0);
2496 if (retval != STATUS_SUCCESS)
2497 TRACE_RET(chip, SWITCH_FAIL);
2498
2499 if (width == MMC_8BIT_BUS) {
2500 buf[0] = 0x55;
2501 buf[1] = 0xAA;
2502 len = 8;
2503 byte_cnt = 8;
2504 bus_width = SD_BUS_WIDTH_8;
2505 } else {
2506 buf[0] = 0x5A;
2507 len = 4;
2508 byte_cnt = 4;
2509 bus_width = SD_BUS_WIDTH_4;
2510 }
2511
2512 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2513 if (retval != STATUS_SUCCESS)
2514 TRACE_RET(chip, SWITCH_ERR);
2515
2516 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2517 NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2518 if (retval != STATUS_SUCCESS) {
2519 rtsx_clear_sd_error(chip);
2520 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2521 TRACE_RET(chip, SWITCH_ERR);
2522 }
2523
2524 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2525 if (retval != STATUS_SUCCESS)
2526 TRACE_RET(chip, SWITCH_ERR);
2527
2528 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
2529
2530 rtsx_init_cmd(chip);
2531
2532 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2533
2534 if (width == MMC_8BIT_BUS)
2535 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2536 0xFF, 0x08);
2537 else
2538 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2539 0xFF, 0x04);
2540
2541 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2542 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2543
2544 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2545 SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
2546 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2547 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2548 PINGPONG_BUFFER);
2549 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2550 SD_TM_NORMAL_READ | SD_TRANSFER_START);
2551 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2552 SD_TRANSFER_END);
2553
2554 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2555 if (width == MMC_8BIT_BUS)
2556 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2557
2558 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2559 if (retval < 0) {
2560 rtsx_clear_sd_error(chip);
2561 TRACE_RET(chip, SWITCH_ERR);
2562 }
2563
2564 ptr = rtsx_get_cmd_data(chip) + 1;
2565
2566 if (width == MMC_8BIT_BUS) {
2567 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2568 ptr[0], ptr[1]);
2569 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2570 u8 rsp[5];
2571 u32 arg;
2572
2573 if (CHK_MMC_DDR52(sd_card))
2574 arg = 0x03B70600;
2575 else
2576 arg = 0x03B70200;
2577
2578 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2579 SD_RSP_TYPE_R1b, rsp, 5);
2580 if ((retval == STATUS_SUCCESS) &&
2581 !(rsp[4] & MMC_SWITCH_ERR))
2582 return SWITCH_SUCCESS;
2583 }
2584 } else {
2585 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2586 if (ptr[0] == 0xA5) {
2587 u8 rsp[5];
2588 u32 arg;
2589
2590 if (CHK_MMC_DDR52(sd_card))
2591 arg = 0x03B70500;
2592 else
2593 arg = 0x03B70100;
2594
2595 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2596 SD_RSP_TYPE_R1b, rsp, 5);
2597 if ((retval == STATUS_SUCCESS) &&
2598 !(rsp[4] & MMC_SWITCH_ERR))
2599 return SWITCH_SUCCESS;
2600 }
2601 }
2602
2603 TRACE_RET(chip, SWITCH_FAIL);
2604 }
2605
2606
mmc_switch_timing_bus(struct rtsx_chip * chip,int switch_ddr)2607 static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2608 {
2609 struct sd_info *sd_card = &(chip->sd_card);
2610 int retval;
2611 u8 *ptr, card_type, card_type_mask = 0;
2612
2613 CLR_MMC_HS(sd_card);
2614
2615 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
2616
2617 rtsx_init_cmd(chip);
2618
2619 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
2620 0x40 | SEND_EXT_CSD);
2621 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2622 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2623 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2624 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2625
2626 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2627 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2628 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2629 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2630
2631 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2632 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
2633 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2634 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2635 PINGPONG_BUFFER);
2636 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2637 SD_TM_NORMAL_READ | SD_TRANSFER_START);
2638 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2639 SD_TRANSFER_END);
2640
2641 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2642 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2643 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2644 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2645 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2646
2647 retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2648 if (retval < 0) {
2649 if (retval == -ETIMEDOUT) {
2650 rtsx_clear_sd_error(chip);
2651 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2652 SD_RSP_TYPE_R1, NULL, 0);
2653 }
2654 TRACE_RET(chip, STATUS_FAIL);
2655 }
2656
2657 ptr = rtsx_get_cmd_data(chip);
2658 if (ptr[0] & SD_TRANSFER_ERR) {
2659 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2660 SD_RSP_TYPE_R1, NULL, 0);
2661 TRACE_RET(chip, STATUS_FAIL);
2662 }
2663
2664 if (CHK_MMC_SECTOR_MODE(sd_card)) {
2665 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2666 ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2667 }
2668
2669 card_type_mask = 0x03;
2670 card_type = ptr[1] & card_type_mask;
2671 if (card_type) {
2672 u8 rsp[5];
2673
2674 if (card_type & 0x04) {
2675 if (switch_ddr)
2676 SET_MMC_DDR52(sd_card);
2677 else
2678 SET_MMC_52M(sd_card);
2679 } else if (card_type & 0x02) {
2680 SET_MMC_52M(sd_card);
2681 } else {
2682 SET_MMC_26M(sd_card);
2683 }
2684
2685 retval = sd_send_cmd_get_rsp(chip, SWITCH,
2686 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2687 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2688 CLR_MMC_HS(sd_card);
2689 }
2690
2691 sd_choose_proper_clock(chip);
2692 retval = switch_clock(chip, sd_card->sd_clock);
2693 if (retval != STATUS_SUCCESS)
2694 TRACE_RET(chip, STATUS_FAIL);
2695
2696 /* Test Bus Procedure */
2697 retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2698 if (retval == SWITCH_SUCCESS) {
2699 SET_MMC_8BIT(sd_card);
2700 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2701 #ifdef SUPPORT_SD_LOCK
2702 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2703 #endif
2704 } else if (retval == SWITCH_FAIL) {
2705 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2706 if (retval == SWITCH_SUCCESS) {
2707 SET_MMC_4BIT(sd_card);
2708 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2709 #ifdef SUPPORT_SD_LOCK
2710 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2711 #endif
2712 } else if (retval == SWITCH_FAIL) {
2713 CLR_MMC_8BIT(sd_card);
2714 CLR_MMC_4BIT(sd_card);
2715 } else {
2716 TRACE_RET(chip, STATUS_FAIL);
2717 }
2718 } else {
2719 TRACE_RET(chip, STATUS_FAIL);
2720 }
2721
2722 return STATUS_SUCCESS;
2723 }
2724
2725
reset_mmc(struct rtsx_chip * chip)2726 static int reset_mmc(struct rtsx_chip *chip)
2727 {
2728 struct sd_info *sd_card = &(chip->sd_card);
2729 int retval, i = 0, j = 0, k = 0;
2730 int switch_ddr = 1;
2731 u8 rsp[16];
2732 u8 spec_ver = 0;
2733 u32 temp;
2734
2735 #ifdef SUPPORT_SD_LOCK
2736 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2737 goto MMC_UNLOCK_ENTRY;
2738 #endif
2739
2740 Switch_Fail:
2741 retval = sd_prepare_reset(chip);
2742 if (retval != STATUS_SUCCESS)
2743 TRACE_RET(chip, retval);
2744
2745 SET_MMC(sd_card);
2746
2747 RTY_MMC_RST:
2748 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2749 NULL, 0);
2750 if (retval != STATUS_SUCCESS)
2751 TRACE_RET(chip, STATUS_FAIL);
2752
2753 do {
2754 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2755 sd_set_err_code(chip, SD_NO_CARD);
2756 TRACE_RET(chip, STATUS_FAIL);
2757 }
2758
2759 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2760 (SUPPORT_VOLTAGE | 0x40000000),
2761 SD_RSP_TYPE_R3, rsp, 5);
2762 if (retval != STATUS_SUCCESS) {
2763 if (sd_check_err_code(chip, SD_BUSY) ||
2764 sd_check_err_code(chip, SD_TO_ERR)) {
2765 k++;
2766 if (k < 20) {
2767 sd_clr_err_code(chip);
2768 goto RTY_MMC_RST;
2769 } else {
2770 TRACE_RET(chip, STATUS_FAIL);
2771 }
2772 } else {
2773 j++;
2774 if (j < 100) {
2775 sd_clr_err_code(chip);
2776 goto RTY_MMC_RST;
2777 } else {
2778 TRACE_RET(chip, STATUS_FAIL);
2779 }
2780 }
2781 }
2782
2783 wait_timeout(20);
2784 i++;
2785 } while (!(rsp[1] & 0x80) && (i < 255));
2786
2787 if (i == 255)
2788 TRACE_RET(chip, STATUS_FAIL);
2789
2790 if ((rsp[1] & 0x60) == 0x40)
2791 SET_MMC_SECTOR_MODE(sd_card);
2792 else
2793 CLR_MMC_SECTOR_MODE(sd_card);
2794
2795 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2796 NULL, 0);
2797 if (retval != STATUS_SUCCESS)
2798 TRACE_RET(chip, STATUS_FAIL);
2799
2800 sd_card->sd_addr = 0x00100000;
2801 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2802 SD_RSP_TYPE_R6, rsp, 5);
2803 if (retval != STATUS_SUCCESS)
2804 TRACE_RET(chip, STATUS_FAIL);
2805
2806 retval = sd_check_csd(chip, 1);
2807 if (retval != STATUS_SUCCESS)
2808 TRACE_RET(chip, STATUS_FAIL);
2809
2810 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2811
2812 retval = sd_select_card(chip, 1);
2813 if (retval != STATUS_SUCCESS)
2814 TRACE_RET(chip, STATUS_FAIL);
2815
2816 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2817 NULL, 0);
2818 if (retval != STATUS_SUCCESS)
2819 TRACE_RET(chip, STATUS_FAIL);
2820
2821 #ifdef SUPPORT_SD_LOCK
2822 MMC_UNLOCK_ENTRY:
2823 retval = sd_update_lock_status(chip);
2824 if (retval != STATUS_SUCCESS)
2825 TRACE_RET(chip, STATUS_FAIL);
2826 #endif
2827
2828 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2829 if (retval != STATUS_SUCCESS)
2830 TRACE_RET(chip, STATUS_FAIL);
2831
2832 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2833
2834 if (!sd_card->mmc_dont_switch_bus) {
2835 if (spec_ver == 4) {
2836 /* MMC 4.x Cards */
2837 retval = mmc_switch_timing_bus(chip, switch_ddr);
2838 if (retval != STATUS_SUCCESS) {
2839 retval = sd_init_power(chip);
2840 if (retval != STATUS_SUCCESS)
2841 TRACE_RET(chip, STATUS_FAIL);
2842 sd_card->mmc_dont_switch_bus = 1;
2843 TRACE_GOTO(chip, Switch_Fail);
2844 }
2845 }
2846
2847 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
2848 TRACE_RET(chip, STATUS_FAIL);
2849
2850 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
2851 retval = sd_set_init_para(chip);
2852 if (retval != STATUS_SUCCESS)
2853 TRACE_RET(chip, STATUS_FAIL);
2854
2855 retval = mmc_ddr_tuning(chip);
2856 if (retval != STATUS_SUCCESS) {
2857 retval = sd_init_power(chip);
2858 if (retval != STATUS_SUCCESS)
2859 TRACE_RET(chip, STATUS_FAIL);
2860
2861 switch_ddr = 0;
2862 TRACE_GOTO(chip, Switch_Fail);
2863 }
2864
2865 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2866 if (retval == STATUS_SUCCESS) {
2867 retval = sd_read_lba0(chip);
2868 if (retval != STATUS_SUCCESS) {
2869 retval = sd_init_power(chip);
2870 if (retval != STATUS_SUCCESS)
2871 TRACE_RET(chip, STATUS_FAIL);
2872
2873 switch_ddr = 0;
2874 TRACE_GOTO(chip, Switch_Fail);
2875 }
2876 }
2877 }
2878 }
2879
2880 #ifdef SUPPORT_SD_LOCK
2881 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2882 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2883 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2884 }
2885 #endif
2886
2887 temp = rtsx_readl(chip, RTSX_BIPR);
2888 if (temp & SD_WRITE_PROTECT)
2889 chip->card_wp |= SD_CARD;
2890
2891 return STATUS_SUCCESS;
2892 }
2893
reset_sd_card(struct rtsx_chip * chip)2894 int reset_sd_card(struct rtsx_chip *chip)
2895 {
2896 struct sd_info *sd_card = &(chip->sd_card);
2897 int retval;
2898
2899 sd_init_reg_addr(chip);
2900
2901 memset(sd_card, 0, sizeof(struct sd_info));
2902 chip->capacity[chip->card2lun[SD_CARD]] = 0;
2903
2904 retval = enable_card_clock(chip, SD_CARD);
2905 if (retval != STATUS_SUCCESS)
2906 TRACE_RET(chip, STATUS_FAIL);
2907
2908 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
2909 !CHK_SDIO_IGNORED(chip)) {
2910 if (chip->asic_code) {
2911 retval = sd_pull_ctl_enable(chip);
2912 if (retval != STATUS_SUCCESS)
2913 TRACE_RET(chip, STATUS_FAIL);
2914 } else {
2915 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2916 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2917 if (retval != STATUS_SUCCESS)
2918 TRACE_RET(chip, STATUS_FAIL);
2919 }
2920 retval = card_share_mode(chip, SD_CARD);
2921 if (retval != STATUS_SUCCESS)
2922 TRACE_RET(chip, STATUS_FAIL);
2923
2924 chip->sd_io = 1;
2925 TRACE_RET(chip, STATUS_FAIL);
2926 }
2927
2928 retval = sd_init_power(chip);
2929 if (retval != STATUS_SUCCESS)
2930 TRACE_RET(chip, STATUS_FAIL);
2931
2932 if (chip->sd_ctl & RESET_MMC_FIRST) {
2933 retval = reset_mmc(chip);
2934 if (retval != STATUS_SUCCESS) {
2935 if (sd_check_err_code(chip, SD_NO_CARD))
2936 TRACE_RET(chip, STATUS_FAIL);
2937
2938 retval = reset_sd(chip);
2939 if (retval != STATUS_SUCCESS)
2940 TRACE_RET(chip, STATUS_FAIL);
2941 }
2942 } else {
2943 retval = reset_sd(chip);
2944 if (retval != STATUS_SUCCESS) {
2945 if (sd_check_err_code(chip, SD_NO_CARD))
2946 TRACE_RET(chip, STATUS_FAIL);
2947
2948 if (chip->sd_io) {
2949 TRACE_RET(chip, STATUS_FAIL);
2950 } else {
2951 retval = reset_mmc(chip);
2952 if (retval != STATUS_SUCCESS)
2953 TRACE_RET(chip, STATUS_FAIL);
2954 }
2955 }
2956 }
2957
2958 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2959 if (retval != STATUS_SUCCESS)
2960 TRACE_RET(chip, STATUS_FAIL);
2961
2962 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
2963 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
2964
2965 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
2966
2967 retval = sd_set_init_para(chip);
2968 if (retval != STATUS_SUCCESS)
2969 TRACE_RET(chip, STATUS_FAIL);
2970
2971 dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
2972
2973 return STATUS_SUCCESS;
2974 }
2975
reset_mmc_only(struct rtsx_chip * chip)2976 static int reset_mmc_only(struct rtsx_chip *chip)
2977 {
2978 struct sd_info *sd_card = &(chip->sd_card);
2979 int retval;
2980
2981 sd_card->sd_type = 0;
2982 sd_card->seq_mode = 0;
2983 sd_card->sd_data_buf_ready = 0;
2984 sd_card->capacity = 0;
2985 sd_card->sd_switch_fail = 0;
2986
2987 #ifdef SUPPORT_SD_LOCK
2988 sd_card->sd_lock_status = 0;
2989 sd_card->sd_erase_status = 0;
2990 #endif
2991
2992 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
2993
2994 retval = enable_card_clock(chip, SD_CARD);
2995 if (retval != STATUS_SUCCESS)
2996 TRACE_RET(chip, STATUS_FAIL);
2997
2998 retval = sd_init_power(chip);
2999 if (retval != STATUS_SUCCESS)
3000 TRACE_RET(chip, STATUS_FAIL);
3001
3002 retval = reset_mmc(chip);
3003 if (retval != STATUS_SUCCESS)
3004 TRACE_RET(chip, STATUS_FAIL);
3005
3006 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3007 if (retval != STATUS_SUCCESS)
3008 TRACE_RET(chip, STATUS_FAIL);
3009
3010 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3011 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3012
3013 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3014
3015 retval = sd_set_init_para(chip);
3016 if (retval != STATUS_SUCCESS)
3017 TRACE_RET(chip, STATUS_FAIL);
3018
3019 dev_dbg(rtsx_dev(chip), "In reset_mmc_only, sd_card->sd_type = 0x%x\n",
3020 sd_card->sd_type);
3021
3022 return STATUS_SUCCESS;
3023 }
3024
3025 #define WAIT_DATA_READY_RTY_CNT 255
3026
wait_data_buf_ready(struct rtsx_chip * chip)3027 static int wait_data_buf_ready(struct rtsx_chip *chip)
3028 {
3029 struct sd_info *sd_card = &(chip->sd_card);
3030 int i, retval;
3031
3032 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3033 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3034 sd_set_err_code(chip, SD_NO_CARD);
3035 TRACE_RET(chip, STATUS_FAIL);
3036 }
3037
3038 sd_card->sd_data_buf_ready = 0;
3039
3040 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3041 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3042 if (retval != STATUS_SUCCESS)
3043 TRACE_RET(chip, STATUS_FAIL);
3044
3045 if (sd_card->sd_data_buf_ready) {
3046 return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3047 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3048 }
3049 }
3050
3051 sd_set_err_code(chip, SD_TO_ERR);
3052
3053 TRACE_RET(chip, STATUS_FAIL);
3054 }
3055
sd_stop_seq_mode(struct rtsx_chip * chip)3056 void sd_stop_seq_mode(struct rtsx_chip *chip)
3057 {
3058 struct sd_info *sd_card = &(chip->sd_card);
3059 int retval;
3060
3061 if (sd_card->seq_mode) {
3062 retval = sd_switch_clock(chip);
3063 if (retval != STATUS_SUCCESS)
3064 return;
3065
3066 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3067 SD_RSP_TYPE_R1b, NULL, 0);
3068 if (retval != STATUS_SUCCESS)
3069 sd_set_err_code(chip, SD_STS_ERR);
3070
3071 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3072 if (retval != STATUS_SUCCESS)
3073 sd_set_err_code(chip, SD_STS_ERR);
3074
3075 sd_card->seq_mode = 0;
3076
3077 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3078 }
3079 }
3080
sd_auto_tune_clock(struct rtsx_chip * chip)3081 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3082 {
3083 struct sd_info *sd_card = &(chip->sd_card);
3084 int retval;
3085
3086 if (chip->asic_code) {
3087 if (sd_card->sd_clock > 30)
3088 sd_card->sd_clock -= 20;
3089 } else {
3090 switch (sd_card->sd_clock) {
3091 case CLK_200:
3092 sd_card->sd_clock = CLK_150;
3093 break;
3094
3095 case CLK_150:
3096 sd_card->sd_clock = CLK_120;
3097 break;
3098
3099 case CLK_120:
3100 sd_card->sd_clock = CLK_100;
3101 break;
3102
3103 case CLK_100:
3104 sd_card->sd_clock = CLK_80;
3105 break;
3106
3107 case CLK_80:
3108 sd_card->sd_clock = CLK_60;
3109 break;
3110
3111 case CLK_60:
3112 sd_card->sd_clock = CLK_50;
3113 break;
3114
3115 default:
3116 break;
3117 }
3118 }
3119
3120 retval = sd_switch_clock(chip);
3121 if (retval != STATUS_SUCCESS)
3122 TRACE_RET(chip, STATUS_FAIL);
3123
3124 return STATUS_SUCCESS;
3125 }
3126
sd_rw(struct scsi_cmnd * srb,struct rtsx_chip * chip,u32 start_sector,u16 sector_cnt)3127 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3128 u16 sector_cnt)
3129 {
3130 struct sd_info *sd_card = &(chip->sd_card);
3131 u32 data_addr;
3132 u8 cfg2;
3133 int retval;
3134
3135 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3136 dev_dbg(rtsx_dev(chip), "sd_rw: Read %d %s from 0x%x\n",
3137 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3138 start_sector);
3139 } else {
3140 dev_dbg(rtsx_dev(chip), "sd_rw: Write %d %s to 0x%x\n",
3141 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3142 start_sector);
3143 }
3144
3145 sd_card->cleanup_counter = 0;
3146
3147 if (!(chip->card_ready & SD_CARD)) {
3148 sd_card->seq_mode = 0;
3149
3150 retval = reset_sd_card(chip);
3151 if (retval == STATUS_SUCCESS) {
3152 chip->card_ready |= SD_CARD;
3153 chip->card_fail &= ~SD_CARD;
3154 } else {
3155 chip->card_ready &= ~SD_CARD;
3156 chip->card_fail |= SD_CARD;
3157 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3158 chip->rw_need_retry = 1;
3159 TRACE_RET(chip, STATUS_FAIL);
3160 }
3161 }
3162
3163 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3164 data_addr = start_sector << 9;
3165 else
3166 data_addr = start_sector;
3167
3168 sd_clr_err_code(chip);
3169
3170 retval = sd_switch_clock(chip);
3171 if (retval != STATUS_SUCCESS) {
3172 sd_set_err_code(chip, SD_IO_ERR);
3173 TRACE_GOTO(chip, RW_FAIL);
3174 }
3175
3176 if (sd_card->seq_mode &&
3177 ((sd_card->pre_dir != srb->sc_data_direction) ||
3178 ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3179 start_sector))) {
3180 if ((sd_card->pre_sec_cnt < 0x80)
3181 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3182 && !CHK_SD30_SPEED(sd_card)
3183 && !CHK_SD_HS(sd_card)
3184 && !CHK_MMC_HS(sd_card)) {
3185 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3186 SD_RSP_TYPE_R1, NULL, 0);
3187 }
3188
3189 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3190 0, SD_RSP_TYPE_R1b, NULL, 0);
3191 if (retval != STATUS_SUCCESS) {
3192 chip->rw_need_retry = 1;
3193 sd_set_err_code(chip, SD_STS_ERR);
3194 TRACE_GOTO(chip, RW_FAIL);
3195 }
3196
3197 sd_card->seq_mode = 0;
3198
3199 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3200 if (retval != STATUS_SUCCESS) {
3201 sd_set_err_code(chip, SD_IO_ERR);
3202 TRACE_GOTO(chip, RW_FAIL);
3203 }
3204
3205 if ((sd_card->pre_sec_cnt < 0x80)
3206 && !CHK_SD30_SPEED(sd_card)
3207 && !CHK_SD_HS(sd_card)
3208 && !CHK_MMC_HS(sd_card)) {
3209 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3210 SD_RSP_TYPE_R1, NULL, 0);
3211 }
3212 }
3213
3214 rtsx_init_cmd(chip);
3215
3216 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3217 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3218 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3219 (u8)sector_cnt);
3220 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3221 (u8)(sector_cnt >> 8));
3222
3223 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3224
3225 if (CHK_MMC_8BIT(sd_card))
3226 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3227 0x03, SD_BUS_WIDTH_8);
3228 else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3229 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3230 0x03, SD_BUS_WIDTH_4);
3231 else
3232 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3233 0x03, SD_BUS_WIDTH_1);
3234
3235 if (sd_card->seq_mode) {
3236 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16|
3237 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3238 SD_RSP_LEN_0;
3239 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3240
3241 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3242 DMA_512);
3243
3244 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3245 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3246 SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3247 } else {
3248 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3249 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3250 }
3251
3252 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3253 SD_TRANSFER_END, SD_TRANSFER_END);
3254
3255 rtsx_send_cmd_no_wait(chip);
3256 } else {
3257 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3258 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3259 READ_MULTIPLE_BLOCK);
3260 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3261 0x40 | READ_MULTIPLE_BLOCK);
3262 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3263 (u8)(data_addr >> 24));
3264 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3265 (u8)(data_addr >> 16));
3266 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3267 (u8)(data_addr >> 8));
3268 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3269 (u8)data_addr);
3270
3271 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3272 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3273 SD_RSP_LEN_6;
3274 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3275 cfg2);
3276
3277 trans_dma_enable(srb->sc_data_direction, chip,
3278 sector_cnt * 512, DMA_512);
3279
3280 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3281 SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3282 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3283 SD_TRANSFER_END, SD_TRANSFER_END);
3284
3285 rtsx_send_cmd_no_wait(chip);
3286 } else {
3287 retval = rtsx_send_cmd(chip, SD_CARD, 50);
3288 if (retval < 0) {
3289 rtsx_clear_sd_error(chip);
3290
3291 chip->rw_need_retry = 1;
3292 sd_set_err_code(chip, SD_TO_ERR);
3293 TRACE_GOTO(chip, RW_FAIL);
3294 }
3295
3296 retval = wait_data_buf_ready(chip);
3297 if (retval != STATUS_SUCCESS) {
3298 chip->rw_need_retry = 1;
3299 sd_set_err_code(chip, SD_TO_ERR);
3300 TRACE_GOTO(chip, RW_FAIL);
3301 }
3302
3303 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3304 data_addr, SD_RSP_TYPE_R1, NULL, 0);
3305 if (retval != STATUS_SUCCESS) {
3306 chip->rw_need_retry = 1;
3307 TRACE_GOTO(chip, RW_FAIL);
3308 }
3309
3310 rtsx_init_cmd(chip);
3311
3312 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3313 SD_NO_WAIT_BUSY_END |
3314 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3315 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3316 cfg2);
3317
3318 trans_dma_enable(srb->sc_data_direction, chip,
3319 sector_cnt * 512, DMA_512);
3320
3321 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3322 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3323 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3324 SD_TRANSFER_END, SD_TRANSFER_END);
3325
3326 rtsx_send_cmd_no_wait(chip);
3327 }
3328
3329 sd_card->seq_mode = 1;
3330 }
3331
3332 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3333 scsi_bufflen(srb), scsi_sg_count(srb),
3334 srb->sc_data_direction, chip->sd_timeout);
3335 if (retval < 0) {
3336 u8 stat = 0;
3337 int err;
3338
3339 sd_card->seq_mode = 0;
3340
3341 if (retval == -ETIMEDOUT)
3342 err = STATUS_TIMEDOUT;
3343 else
3344 err = STATUS_FAIL;
3345
3346 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3347 rtsx_clear_sd_error(chip);
3348 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3349 chip->rw_need_retry = 0;
3350 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n");
3351 TRACE_RET(chip, STATUS_FAIL);
3352 }
3353
3354 chip->rw_need_retry = 1;
3355
3356 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3357 SD_RSP_TYPE_R1b, NULL, 0);
3358 if (retval != STATUS_SUCCESS) {
3359 sd_set_err_code(chip, SD_STS_ERR);
3360 TRACE_GOTO(chip, RW_FAIL);
3361 }
3362
3363 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3364 dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3365 sd_set_err_code(chip, SD_CRC_ERR);
3366 TRACE_GOTO(chip, RW_FAIL);
3367 }
3368
3369 if (err == STATUS_TIMEDOUT) {
3370 sd_set_err_code(chip, SD_TO_ERR);
3371 TRACE_GOTO(chip, RW_FAIL);
3372 }
3373
3374 TRACE_RET(chip, err);
3375 }
3376
3377 sd_card->pre_sec_addr = start_sector;
3378 sd_card->pre_sec_cnt = sector_cnt;
3379 sd_card->pre_dir = srb->sc_data_direction;
3380
3381 return STATUS_SUCCESS;
3382
3383 RW_FAIL:
3384 sd_card->seq_mode = 0;
3385
3386 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3387 chip->rw_need_retry = 0;
3388 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n");
3389 TRACE_RET(chip, STATUS_FAIL);
3390 }
3391
3392 if (sd_check_err_code(chip, SD_CRC_ERR)) {
3393 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3394 sd_card->mmc_dont_switch_bus = 1;
3395 reset_mmc_only(chip);
3396 sd_card->mmc_dont_switch_bus = 0;
3397 } else {
3398 sd_card->need_retune = 1;
3399 sd_auto_tune_clock(chip);
3400 }
3401 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3402 retval = reset_sd_card(chip);
3403 if (retval != STATUS_SUCCESS) {
3404 chip->card_ready &= ~SD_CARD;
3405 chip->card_fail |= SD_CARD;
3406 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3407 }
3408 }
3409
3410 TRACE_RET(chip, STATUS_FAIL);
3411 }
3412
3413 #ifdef SUPPORT_CPRM
soft_reset_sd_card(struct rtsx_chip * chip)3414 int soft_reset_sd_card(struct rtsx_chip *chip)
3415 {
3416 return reset_sd(chip);
3417 }
3418
ext_sd_send_cmd_get_rsp(struct rtsx_chip * chip,u8 cmd_idx,u32 arg,u8 rsp_type,u8 * rsp,int rsp_len,int special_check)3419 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3420 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3421 {
3422 int retval;
3423 int timeout = 100;
3424 u16 reg_addr;
3425 u8 *ptr;
3426 int stat_idx = 0;
3427 int rty_cnt = 0;
3428
3429 dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
3430
3431 if (rsp_type == SD_RSP_TYPE_R1b)
3432 timeout = 3000;
3433
3434 RTY_SEND_CMD:
3435
3436 rtsx_init_cmd(chip);
3437
3438 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3439 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3440 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3441 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3442 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3443
3444 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3445 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3446 0x01, PINGPONG_BUFFER);
3447 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3448 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3449 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3450 SD_TRANSFER_END);
3451
3452 if (rsp_type == SD_RSP_TYPE_R2) {
3453 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3454 reg_addr++)
3455 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3456
3457 stat_idx = 17;
3458 } else if (rsp_type != SD_RSP_TYPE_R0) {
3459 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3460 reg_addr++)
3461 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3462
3463 stat_idx = 6;
3464 }
3465 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3466
3467 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3468
3469 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3470 if (retval < 0) {
3471 if (retval == -ETIMEDOUT) {
3472 rtsx_clear_sd_error(chip);
3473
3474 if (rsp_type & SD_WAIT_BUSY_END) {
3475 retval = sd_check_data0_status(chip);
3476 if (retval != STATUS_SUCCESS)
3477 TRACE_RET(chip, retval);
3478 } else {
3479 sd_set_err_code(chip, SD_TO_ERR);
3480 }
3481 }
3482 TRACE_RET(chip, STATUS_FAIL);
3483 }
3484
3485 if (rsp_type == SD_RSP_TYPE_R0)
3486 return STATUS_SUCCESS;
3487
3488 ptr = rtsx_get_cmd_data(chip) + 1;
3489
3490 if ((ptr[0] & 0xC0) != 0) {
3491 sd_set_err_code(chip, SD_STS_ERR);
3492 TRACE_RET(chip, STATUS_FAIL);
3493 }
3494
3495 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3496 if (ptr[stat_idx] & SD_CRC7_ERR) {
3497 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3498 sd_set_err_code(chip, SD_CRC_ERR);
3499 TRACE_RET(chip, STATUS_FAIL);
3500 }
3501 if (rty_cnt < SD_MAX_RETRY_COUNT) {
3502 wait_timeout(20);
3503 rty_cnt++;
3504 goto RTY_SEND_CMD;
3505 } else {
3506 sd_set_err_code(chip, SD_CRC_ERR);
3507 TRACE_RET(chip, STATUS_FAIL);
3508 }
3509 }
3510 }
3511
3512 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3513 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3514 if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3515 if (ptr[1] & 0x80)
3516 TRACE_RET(chip, STATUS_FAIL);
3517 }
3518 #ifdef SUPPORT_SD_LOCK
3519 if (ptr[1] & 0x7D)
3520 #else
3521 if (ptr[1] & 0x7F)
3522 #endif
3523 {
3524 TRACE_RET(chip, STATUS_FAIL);
3525 }
3526 if (ptr[2] & 0xF8)
3527 TRACE_RET(chip, STATUS_FAIL);
3528
3529 if (cmd_idx == SELECT_CARD) {
3530 if (rsp_type == SD_RSP_TYPE_R2) {
3531 if ((ptr[3] & 0x1E) != 0x04)
3532 TRACE_RET(chip, STATUS_FAIL);
3533
3534 } else if (rsp_type == SD_RSP_TYPE_R0) {
3535 if ((ptr[3] & 0x1E) != 0x03)
3536 TRACE_RET(chip, STATUS_FAIL);
3537 }
3538 }
3539 }
3540
3541 if (rsp && rsp_len)
3542 memcpy(rsp, ptr, rsp_len);
3543
3544 return STATUS_SUCCESS;
3545 }
3546
ext_sd_get_rsp(struct rtsx_chip * chip,int len,u8 * rsp,u8 rsp_type)3547 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3548 {
3549 int retval, rsp_len;
3550 u16 reg_addr;
3551
3552 if (rsp_type == SD_RSP_TYPE_R0)
3553 return STATUS_SUCCESS;
3554
3555 rtsx_init_cmd(chip);
3556
3557 if (rsp_type == SD_RSP_TYPE_R2) {
3558 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3559 reg_addr++)
3560 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3561
3562 rsp_len = 17;
3563 } else if (rsp_type != SD_RSP_TYPE_R0) {
3564 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3565 reg_addr++)
3566 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3567
3568 rsp_len = 6;
3569 }
3570 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3571
3572 retval = rtsx_send_cmd(chip, SD_CARD, 100);
3573 if (retval != STATUS_SUCCESS)
3574 TRACE_RET(chip, STATUS_FAIL);
3575
3576 if (rsp) {
3577 int min_len = (rsp_len < len) ? rsp_len : len;
3578
3579 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3580
3581 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
3582 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3583 rsp[0], rsp[1], rsp[2], rsp[3]);
3584 }
3585
3586 return STATUS_SUCCESS;
3587 }
3588
sd_pass_thru_mode(struct scsi_cmnd * srb,struct rtsx_chip * chip)3589 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3590 {
3591 struct sd_info *sd_card = &(chip->sd_card);
3592 unsigned int lun = SCSI_LUN(srb);
3593 int len;
3594 u8 buf[18] = {
3595 0x00,
3596 0x00,
3597 0x00,
3598 0x0E,
3599 0x00,
3600 0x00,
3601 0x00,
3602 0x00,
3603 0x53,
3604 0x44,
3605 0x20,
3606 0x43,
3607 0x61,
3608 0x72,
3609 0x64,
3610 0x00,
3611 0x00,
3612 0x00,
3613 };
3614
3615 sd_card->pre_cmd_err = 0;
3616
3617 if (!(CHK_BIT(chip->lun_mc, lun))) {
3618 SET_BIT(chip->lun_mc, lun);
3619 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3620 TRACE_RET(chip, TRANSPORT_FAILED);
3621 }
3622
3623 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) ||
3624 (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) ||
3625 (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) ||
3626 (0x64 != srb->cmnd[8])) {
3627 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3628 TRACE_RET(chip, TRANSPORT_FAILED);
3629 }
3630
3631 switch (srb->cmnd[1] & 0x0F) {
3632 case 0:
3633 sd_card->sd_pass_thru_en = 0;
3634 break;
3635
3636 case 1:
3637 sd_card->sd_pass_thru_en = 1;
3638 break;
3639
3640 default:
3641 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3642 TRACE_RET(chip, TRANSPORT_FAILED);
3643 }
3644
3645 buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02;
3646 if (chip->card_wp & SD_CARD)
3647 buf[5] |= 0x80;
3648
3649 buf[6] = (u8)(sd_card->sd_addr >> 16);
3650 buf[7] = (u8)(sd_card->sd_addr >> 24);
3651
3652 buf[15] = chip->max_lun;
3653
3654 len = min_t(int, 18, scsi_bufflen(srb));
3655 rtsx_stor_set_xfer_buf(buf, len, srb);
3656
3657 return TRANSPORT_GOOD;
3658 }
3659
get_rsp_type(struct scsi_cmnd * srb,u8 * rsp_type,int * rsp_len)3660 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
3661 int *rsp_len)
3662 {
3663 if (!rsp_type || !rsp_len)
3664 return STATUS_FAIL;
3665
3666 switch (srb->cmnd[10]) {
3667 case 0x03:
3668 *rsp_type = SD_RSP_TYPE_R0;
3669 *rsp_len = 0;
3670 break;
3671
3672 case 0x04:
3673 *rsp_type = SD_RSP_TYPE_R1;
3674 *rsp_len = 6;
3675 break;
3676
3677 case 0x05:
3678 *rsp_type = SD_RSP_TYPE_R1b;
3679 *rsp_len = 6;
3680 break;
3681
3682 case 0x06:
3683 *rsp_type = SD_RSP_TYPE_R2;
3684 *rsp_len = 17;
3685 break;
3686
3687 case 0x07:
3688 *rsp_type = SD_RSP_TYPE_R3;
3689 *rsp_len = 6;
3690 break;
3691
3692 default:
3693 return STATUS_FAIL;
3694 }
3695
3696 return STATUS_SUCCESS;
3697 }
3698
sd_execute_no_data(struct scsi_cmnd * srb,struct rtsx_chip * chip)3699 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3700 {
3701 struct sd_info *sd_card = &(chip->sd_card);
3702 unsigned int lun = SCSI_LUN(srb);
3703 int retval, rsp_len;
3704 u8 cmd_idx, rsp_type;
3705 u8 standby = 0, acmd = 0;
3706 u32 arg;
3707
3708 if (!sd_card->sd_pass_thru_en) {
3709 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3710 TRACE_RET(chip, TRANSPORT_FAILED);
3711 }
3712
3713 retval = sd_switch_clock(chip);
3714 if (retval != STATUS_SUCCESS)
3715 TRACE_RET(chip, TRANSPORT_FAILED);
3716
3717 if (sd_card->pre_cmd_err) {
3718 sd_card->pre_cmd_err = 0;
3719 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3720 TRACE_RET(chip, TRANSPORT_FAILED);
3721 }
3722
3723 cmd_idx = srb->cmnd[2] & 0x3F;
3724 if (srb->cmnd[1] & 0x02)
3725 standby = 1;
3726
3727 if (srb->cmnd[1] & 0x01)
3728 acmd = 1;
3729
3730 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3731 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3732
3733 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3734 if (retval != STATUS_SUCCESS) {
3735 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3736 TRACE_RET(chip, TRANSPORT_FAILED);
3737 }
3738 sd_card->last_rsp_type = rsp_type;
3739
3740 retval = sd_switch_clock(chip);
3741 if (retval != STATUS_SUCCESS)
3742 TRACE_RET(chip, TRANSPORT_FAILED);
3743
3744 #ifdef SUPPORT_SD_LOCK
3745 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3746 if (CHK_MMC_8BIT(sd_card)) {
3747 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3748 SD_BUS_WIDTH_8);
3749 if (retval != STATUS_SUCCESS)
3750 TRACE_RET(chip, TRANSPORT_FAILED);
3751
3752 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3753 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3754 SD_BUS_WIDTH_4);
3755 if (retval != STATUS_SUCCESS)
3756 TRACE_RET(chip, TRANSPORT_FAILED);
3757 }
3758 }
3759 #else
3760 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3761 if (retval != STATUS_SUCCESS)
3762 TRACE_RET(chip, TRANSPORT_FAILED);
3763 #endif
3764
3765 if (standby) {
3766 retval = sd_select_card(chip, 0);
3767 if (retval != STATUS_SUCCESS)
3768 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3769 }
3770
3771 if (acmd) {
3772 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3773 sd_card->sd_addr,
3774 SD_RSP_TYPE_R1, NULL, 0, 0);
3775 if (retval != STATUS_SUCCESS)
3776 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3777 }
3778
3779 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3780 sd_card->rsp, rsp_len, 0);
3781 if (retval != STATUS_SUCCESS)
3782 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3783
3784 if (standby) {
3785 retval = sd_select_card(chip, 1);
3786 if (retval != STATUS_SUCCESS)
3787 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3788 }
3789
3790 #ifdef SUPPORT_SD_LOCK
3791 retval = sd_update_lock_status(chip);
3792 if (retval != STATUS_SUCCESS)
3793 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3794 #endif
3795
3796 scsi_set_resid(srb, 0);
3797 return TRANSPORT_GOOD;
3798
3799 SD_Execute_Cmd_Failed:
3800 sd_card->pre_cmd_err = 1;
3801 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3802 release_sd_card(chip);
3803 do_reset_sd_card(chip);
3804 if (!(chip->card_ready & SD_CARD))
3805 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3806
3807 TRACE_RET(chip, TRANSPORT_FAILED);
3808 }
3809
sd_execute_read_data(struct scsi_cmnd * srb,struct rtsx_chip * chip)3810 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3811 {
3812 struct sd_info *sd_card = &(chip->sd_card);
3813 unsigned int lun = SCSI_LUN(srb);
3814 int retval, rsp_len, i;
3815 int cmd13_checkbit = 0, read_err = 0;
3816 u8 cmd_idx, rsp_type, bus_width;
3817 u8 send_cmd12 = 0, standby = 0, acmd = 0;
3818 u32 data_len;
3819
3820 if (!sd_card->sd_pass_thru_en) {
3821 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3822 TRACE_RET(chip, TRANSPORT_FAILED);
3823 }
3824
3825 if (sd_card->pre_cmd_err) {
3826 sd_card->pre_cmd_err = 0;
3827 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3828 TRACE_RET(chip, TRANSPORT_FAILED);
3829 }
3830
3831 retval = sd_switch_clock(chip);
3832 if (retval != STATUS_SUCCESS)
3833 TRACE_RET(chip, TRANSPORT_FAILED);
3834
3835 cmd_idx = srb->cmnd[2] & 0x3F;
3836 if (srb->cmnd[1] & 0x04)
3837 send_cmd12 = 1;
3838
3839 if (srb->cmnd[1] & 0x02)
3840 standby = 1;
3841
3842 if (srb->cmnd[1] & 0x01)
3843 acmd = 1;
3844
3845 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
3846 << 8) | srb->cmnd[9];
3847
3848 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3849 if (retval != STATUS_SUCCESS) {
3850 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3851 TRACE_RET(chip, TRANSPORT_FAILED);
3852 }
3853 sd_card->last_rsp_type = rsp_type;
3854
3855 retval = sd_switch_clock(chip);
3856 if (retval != STATUS_SUCCESS)
3857 TRACE_RET(chip, TRANSPORT_FAILED);
3858
3859 #ifdef SUPPORT_SD_LOCK
3860 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3861 if (CHK_MMC_8BIT(sd_card))
3862 bus_width = SD_BUS_WIDTH_8;
3863 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
3864 bus_width = SD_BUS_WIDTH_4;
3865 else
3866 bus_width = SD_BUS_WIDTH_1;
3867 } else {
3868 bus_width = SD_BUS_WIDTH_4;
3869 }
3870 dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
3871 #else
3872 bus_width = SD_BUS_WIDTH_4;
3873 #endif
3874
3875 if (data_len < 512) {
3876 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
3877 SD_RSP_TYPE_R1, NULL, 0, 0);
3878 if (retval != STATUS_SUCCESS)
3879 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3880 }
3881
3882 if (standby) {
3883 retval = sd_select_card(chip, 0);
3884 if (retval != STATUS_SUCCESS)
3885 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3886 }
3887
3888 if (acmd) {
3889 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3890 sd_card->sd_addr,
3891 SD_RSP_TYPE_R1, NULL, 0, 0);
3892 if (retval != STATUS_SUCCESS)
3893 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3894 }
3895
3896 if (data_len <= 512) {
3897 int min_len;
3898 u8 *buf;
3899 u16 byte_cnt, blk_cnt;
3900 u8 cmd[5];
3901
3902 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
3903 blk_cnt = 1;
3904
3905 cmd[0] = 0x40 | cmd_idx;
3906 cmd[1] = srb->cmnd[3];
3907 cmd[2] = srb->cmnd[4];
3908 cmd[3] = srb->cmnd[5];
3909 cmd[4] = srb->cmnd[6];
3910
3911 buf = kmalloc(data_len, GFP_KERNEL);
3912 if (buf == NULL)
3913 TRACE_RET(chip, TRANSPORT_ERROR);
3914
3915 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
3916 blk_cnt, bus_width, buf, data_len, 2000);
3917 if (retval != STATUS_SUCCESS) {
3918 read_err = 1;
3919 kfree(buf);
3920 rtsx_clear_sd_error(chip);
3921 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3922 }
3923
3924 min_len = min(data_len, scsi_bufflen(srb));
3925 rtsx_stor_set_xfer_buf(buf, min_len, srb);
3926
3927 kfree(buf);
3928 } else if (!(data_len & 0x1FF)) {
3929 rtsx_init_cmd(chip);
3930
3931 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
3932
3933 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
3934 0x02);
3935 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
3936 0x00);
3937 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
3938 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
3939 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
3940 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
3941
3942 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3943 0x40 | cmd_idx);
3944 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3945 srb->cmnd[3]);
3946 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3947 srb->cmnd[4]);
3948 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3949 srb->cmnd[5]);
3950 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3951 srb->cmnd[6]);
3952
3953 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
3954 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3955
3956 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3957 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3958 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3959 SD_TRANSFER_END, SD_TRANSFER_END);
3960
3961 rtsx_send_cmd_no_wait(chip);
3962
3963 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3964 scsi_bufflen(srb), scsi_sg_count(srb),
3965 DMA_FROM_DEVICE, 10000);
3966 if (retval < 0) {
3967 read_err = 1;
3968 rtsx_clear_sd_error(chip);
3969 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3970 }
3971
3972 } else {
3973 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3974 }
3975
3976 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
3977 if (retval != STATUS_SUCCESS)
3978 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3979
3980 if (standby) {
3981 retval = sd_select_card(chip, 1);
3982 if (retval != STATUS_SUCCESS)
3983 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3984 }
3985
3986 if (send_cmd12) {
3987 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3988 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
3989 if (retval != STATUS_SUCCESS)
3990 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3991 }
3992
3993 if (data_len < 512) {
3994 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
3995 SD_RSP_TYPE_R1, NULL, 0, 0);
3996 if (retval != STATUS_SUCCESS)
3997 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3998
3999 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4000 if (retval != STATUS_SUCCESS)
4001 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4002
4003 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4004 if (retval != STATUS_SUCCESS)
4005 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4006 }
4007
4008 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4009 cmd13_checkbit = 1;
4010
4011 for (i = 0; i < 3; i++) {
4012 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4013 sd_card->sd_addr,
4014 SD_RSP_TYPE_R1, NULL, 0,
4015 cmd13_checkbit);
4016 if (retval == STATUS_SUCCESS)
4017 break;
4018 }
4019 if (retval != STATUS_SUCCESS)
4020 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4021
4022 scsi_set_resid(srb, 0);
4023 return TRANSPORT_GOOD;
4024
4025 SD_Execute_Read_Cmd_Failed:
4026 sd_card->pre_cmd_err = 1;
4027 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4028 if (read_err)
4029 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4030
4031 release_sd_card(chip);
4032 do_reset_sd_card(chip);
4033 if (!(chip->card_ready & SD_CARD))
4034 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4035
4036 TRACE_RET(chip, TRANSPORT_FAILED);
4037 }
4038
sd_execute_write_data(struct scsi_cmnd * srb,struct rtsx_chip * chip)4039 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4040 {
4041 struct sd_info *sd_card = &(chip->sd_card);
4042 unsigned int lun = SCSI_LUN(srb);
4043 int retval, rsp_len, i;
4044 int cmd13_checkbit = 0, write_err = 0;
4045 u8 cmd_idx, rsp_type;
4046 u8 send_cmd12 = 0, standby = 0, acmd = 0;
4047 u32 data_len, arg;
4048 #ifdef SUPPORT_SD_LOCK
4049 int lock_cmd_fail = 0;
4050 u8 sd_lock_state = 0;
4051 u8 lock_cmd_type = 0;
4052 #endif
4053
4054 if (!sd_card->sd_pass_thru_en) {
4055 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4056 TRACE_RET(chip, TRANSPORT_FAILED);
4057 }
4058
4059 if (sd_card->pre_cmd_err) {
4060 sd_card->pre_cmd_err = 0;
4061 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4062 TRACE_RET(chip, TRANSPORT_FAILED);
4063 }
4064
4065 retval = sd_switch_clock(chip);
4066 if (retval != STATUS_SUCCESS)
4067 TRACE_RET(chip, TRANSPORT_FAILED);
4068
4069 cmd_idx = srb->cmnd[2] & 0x3F;
4070 if (srb->cmnd[1] & 0x04)
4071 send_cmd12 = 1;
4072
4073 if (srb->cmnd[1] & 0x02)
4074 standby = 1;
4075
4076 if (srb->cmnd[1] & 0x01)
4077 acmd = 1;
4078
4079 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4080 << 8) | srb->cmnd[9];
4081 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4082 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4083
4084 #ifdef SUPPORT_SD_LOCK
4085 if (cmd_idx == LOCK_UNLOCK) {
4086 sd_lock_state = sd_card->sd_lock_status;
4087 sd_lock_state &= SD_LOCKED;
4088 }
4089 #endif
4090
4091 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4092 if (retval != STATUS_SUCCESS) {
4093 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4094 TRACE_RET(chip, TRANSPORT_FAILED);
4095 }
4096 sd_card->last_rsp_type = rsp_type;
4097
4098 retval = sd_switch_clock(chip);
4099 if (retval != STATUS_SUCCESS)
4100 TRACE_RET(chip, TRANSPORT_FAILED);
4101
4102 #ifdef SUPPORT_SD_LOCK
4103 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4104 if (CHK_MMC_8BIT(sd_card)) {
4105 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4106 SD_BUS_WIDTH_8);
4107 if (retval != STATUS_SUCCESS)
4108 TRACE_RET(chip, TRANSPORT_FAILED);
4109
4110 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4111 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4112 SD_BUS_WIDTH_4);
4113 if (retval != STATUS_SUCCESS)
4114 TRACE_RET(chip, TRANSPORT_FAILED);
4115 }
4116 }
4117 #else
4118 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4119 if (retval != STATUS_SUCCESS)
4120 TRACE_RET(chip, TRANSPORT_FAILED);
4121 #endif
4122
4123 if (data_len < 512) {
4124 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4125 SD_RSP_TYPE_R1, NULL, 0, 0);
4126 if (retval != STATUS_SUCCESS)
4127 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4128 }
4129
4130 if (standby) {
4131 retval = sd_select_card(chip, 0);
4132 if (retval != STATUS_SUCCESS)
4133 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4134 }
4135
4136 if (acmd) {
4137 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4138 sd_card->sd_addr,
4139 SD_RSP_TYPE_R1, NULL, 0, 0);
4140 if (retval != STATUS_SUCCESS)
4141 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4142 }
4143
4144 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4145 sd_card->rsp, rsp_len, 0);
4146 if (retval != STATUS_SUCCESS)
4147 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4148
4149 if (data_len <= 512) {
4150 u16 i;
4151 u8 *buf;
4152
4153 buf = kmalloc(data_len, GFP_KERNEL);
4154 if (buf == NULL)
4155 TRACE_RET(chip, TRANSPORT_ERROR);
4156
4157 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4158
4159 #ifdef SUPPORT_SD_LOCK
4160 if (cmd_idx == LOCK_UNLOCK)
4161 lock_cmd_type = buf[0] & 0x0F;
4162 #endif
4163
4164 if (data_len > 256) {
4165 rtsx_init_cmd(chip);
4166 for (i = 0; i < 256; i++) {
4167 rtsx_add_cmd(chip, WRITE_REG_CMD,
4168 PPBUF_BASE2 + i, 0xFF, buf[i]);
4169 }
4170 retval = rtsx_send_cmd(chip, 0, 250);
4171 if (retval != STATUS_SUCCESS) {
4172 kfree(buf);
4173 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4174 }
4175
4176 rtsx_init_cmd(chip);
4177 for (i = 256; i < data_len; i++) {
4178 rtsx_add_cmd(chip, WRITE_REG_CMD,
4179 PPBUF_BASE2 + i, 0xFF, buf[i]);
4180 }
4181 retval = rtsx_send_cmd(chip, 0, 250);
4182 if (retval != STATUS_SUCCESS) {
4183 kfree(buf);
4184 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4185 }
4186 } else {
4187 rtsx_init_cmd(chip);
4188 for (i = 0; i < data_len; i++) {
4189 rtsx_add_cmd(chip, WRITE_REG_CMD,
4190 PPBUF_BASE2 + i, 0xFF, buf[i]);
4191 }
4192 retval = rtsx_send_cmd(chip, 0, 250);
4193 if (retval != STATUS_SUCCESS) {
4194 kfree(buf);
4195 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4196 }
4197 }
4198
4199 kfree(buf);
4200
4201 rtsx_init_cmd(chip);
4202
4203 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4204 srb->cmnd[8] & 0x03);
4205 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4206 srb->cmnd[9]);
4207 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4208 0x00);
4209 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4210 0x01);
4211 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4212 PINGPONG_BUFFER);
4213
4214 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4215 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4216 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4217 SD_TRANSFER_END, SD_TRANSFER_END);
4218
4219 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4220 } else if (!(data_len & 0x1FF)) {
4221 rtsx_init_cmd(chip);
4222
4223 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4224
4225 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4226 0x02);
4227 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4228 0x00);
4229 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4230 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4231 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4232 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4233
4234 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4235 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4236 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4237 SD_TRANSFER_END, SD_TRANSFER_END);
4238
4239 rtsx_send_cmd_no_wait(chip);
4240
4241 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4242 scsi_bufflen(srb), scsi_sg_count(srb),
4243 DMA_TO_DEVICE, 10000);
4244
4245 } else {
4246 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4247 }
4248
4249 if (retval < 0) {
4250 write_err = 1;
4251 rtsx_clear_sd_error(chip);
4252 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4253 }
4254
4255 #ifdef SUPPORT_SD_LOCK
4256 if (cmd_idx == LOCK_UNLOCK) {
4257 if (lock_cmd_type == SD_ERASE) {
4258 sd_card->sd_erase_status = SD_UNDER_ERASING;
4259 scsi_set_resid(srb, 0);
4260 return TRANSPORT_GOOD;
4261 }
4262
4263 rtsx_init_cmd(chip);
4264 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4265
4266 rtsx_send_cmd(chip, SD_CARD, 250);
4267
4268 retval = sd_update_lock_status(chip);
4269 if (retval != STATUS_SUCCESS) {
4270 dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
4271 lock_cmd_fail = 1;
4272 }
4273 }
4274 #endif /* SUPPORT_SD_LOCK */
4275
4276 if (standby) {
4277 retval = sd_select_card(chip, 1);
4278 if (retval != STATUS_SUCCESS)
4279 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4280 }
4281
4282 if (send_cmd12) {
4283 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4284 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4285 if (retval != STATUS_SUCCESS)
4286 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4287 }
4288
4289 if (data_len < 512) {
4290 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4291 SD_RSP_TYPE_R1, NULL, 0, 0);
4292 if (retval != STATUS_SUCCESS)
4293 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4294
4295 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4296 if (retval != STATUS_SUCCESS)
4297 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4298
4299 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4300 if (retval != STATUS_SUCCESS)
4301 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4302 }
4303
4304 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4305 cmd13_checkbit = 1;
4306
4307 for (i = 0; i < 3; i++) {
4308 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4309 sd_card->sd_addr,
4310 SD_RSP_TYPE_R1, NULL, 0,
4311 cmd13_checkbit);
4312 if (retval == STATUS_SUCCESS)
4313 break;
4314 }
4315 if (retval != STATUS_SUCCESS)
4316 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4317
4318 #ifdef SUPPORT_SD_LOCK
4319 if (cmd_idx == LOCK_UNLOCK) {
4320 if (!lock_cmd_fail) {
4321 dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
4322 lock_cmd_type);
4323 if (lock_cmd_type & SD_CLR_PWD)
4324 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4325
4326 if (lock_cmd_type & SD_SET_PWD)
4327 sd_card->sd_lock_status |= SD_PWD_EXIST;
4328 }
4329
4330 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4331 sd_lock_state, sd_card->sd_lock_status);
4332 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4333 sd_card->sd_lock_notify = 1;
4334 if (sd_lock_state) {
4335 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4336 sd_card->sd_lock_status |= (
4337 SD_UNLOCK_POW_ON | SD_SDR_RST);
4338 if (CHK_SD(sd_card)) {
4339 retval = reset_sd(chip);
4340 if (retval != STATUS_SUCCESS) {
4341 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4342 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4343 }
4344 }
4345
4346 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4347 }
4348 }
4349 }
4350 }
4351
4352 if (lock_cmd_fail) {
4353 scsi_set_resid(srb, 0);
4354 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4355 TRACE_RET(chip, TRANSPORT_FAILED);
4356 }
4357 #endif /* SUPPORT_SD_LOCK */
4358
4359 scsi_set_resid(srb, 0);
4360 return TRANSPORT_GOOD;
4361
4362 SD_Execute_Write_Cmd_Failed:
4363 sd_card->pre_cmd_err = 1;
4364 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4365 if (write_err)
4366 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4367
4368 release_sd_card(chip);
4369 do_reset_sd_card(chip);
4370 if (!(chip->card_ready & SD_CARD))
4371 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4372
4373 TRACE_RET(chip, TRANSPORT_FAILED);
4374 }
4375
sd_get_cmd_rsp(struct scsi_cmnd * srb,struct rtsx_chip * chip)4376 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4377 {
4378 struct sd_info *sd_card = &(chip->sd_card);
4379 unsigned int lun = SCSI_LUN(srb);
4380 int count;
4381 u16 data_len;
4382
4383 if (!sd_card->sd_pass_thru_en) {
4384 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4385 TRACE_RET(chip, TRANSPORT_FAILED);
4386 }
4387
4388 if (sd_card->pre_cmd_err) {
4389 sd_card->pre_cmd_err = 0;
4390 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4391 TRACE_RET(chip, TRANSPORT_FAILED);
4392 }
4393
4394 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4395
4396 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4397 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4398 TRACE_RET(chip, TRANSPORT_FAILED);
4399 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4400 count = (data_len < 17) ? data_len : 17;
4401 } else {
4402 count = (data_len < 6) ? data_len : 6;
4403 }
4404 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4405
4406 dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
4407 dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
4408 sd_card->rsp[0], sd_card->rsp[1],
4409 sd_card->rsp[2], sd_card->rsp[3]);
4410
4411 scsi_set_resid(srb, 0);
4412 return TRANSPORT_GOOD;
4413 }
4414
sd_hw_rst(struct scsi_cmnd * srb,struct rtsx_chip * chip)4415 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4416 {
4417 struct sd_info *sd_card = &(chip->sd_card);
4418 unsigned int lun = SCSI_LUN(srb);
4419 int retval;
4420
4421 if (!sd_card->sd_pass_thru_en) {
4422 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4423 TRACE_RET(chip, TRANSPORT_FAILED);
4424 }
4425
4426 if (sd_card->pre_cmd_err) {
4427 sd_card->pre_cmd_err = 0;
4428 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4429 TRACE_RET(chip, TRANSPORT_FAILED);
4430 }
4431
4432 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) ||
4433 (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) ||
4434 (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) ||
4435 (0x64 != srb->cmnd[8])) {
4436 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4437 TRACE_RET(chip, TRANSPORT_FAILED);
4438 }
4439
4440 switch (srb->cmnd[1] & 0x0F) {
4441 case 0:
4442 #ifdef SUPPORT_SD_LOCK
4443 if (0x64 == srb->cmnd[9])
4444 sd_card->sd_lock_status |= SD_SDR_RST;
4445 #endif
4446 retval = reset_sd_card(chip);
4447 if (retval != STATUS_SUCCESS) {
4448 #ifdef SUPPORT_SD_LOCK
4449 sd_card->sd_lock_status &= ~SD_SDR_RST;
4450 #endif
4451 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4452 sd_card->pre_cmd_err = 1;
4453 TRACE_RET(chip, TRANSPORT_FAILED);
4454 }
4455 #ifdef SUPPORT_SD_LOCK
4456 sd_card->sd_lock_status &= ~SD_SDR_RST;
4457 #endif
4458 break;
4459
4460 case 1:
4461 retval = soft_reset_sd_card(chip);
4462 if (retval != STATUS_SUCCESS) {
4463 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4464 sd_card->pre_cmd_err = 1;
4465 TRACE_RET(chip, TRANSPORT_FAILED);
4466 }
4467 break;
4468
4469 default:
4470 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4471 TRACE_RET(chip, TRANSPORT_FAILED);
4472 }
4473
4474 scsi_set_resid(srb, 0);
4475 return TRANSPORT_GOOD;
4476 }
4477 #endif
4478
sd_cleanup_work(struct rtsx_chip * chip)4479 void sd_cleanup_work(struct rtsx_chip *chip)
4480 {
4481 struct sd_info *sd_card = &(chip->sd_card);
4482
4483 if (sd_card->seq_mode) {
4484 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
4485 sd_stop_seq_mode(chip);
4486 sd_card->cleanup_counter = 0;
4487 }
4488 }
4489
sd_power_off_card3v3(struct rtsx_chip * chip)4490 int sd_power_off_card3v3(struct rtsx_chip *chip)
4491 {
4492 int retval;
4493
4494 retval = disable_card_clock(chip, SD_CARD);
4495 if (retval != STATUS_SUCCESS)
4496 TRACE_RET(chip, STATUS_FAIL);
4497
4498 RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4499
4500 if (!chip->ft2_fast_mode) {
4501 retval = card_power_off(chip, SD_CARD);
4502 if (retval != STATUS_SUCCESS)
4503 TRACE_RET(chip, STATUS_FAIL);
4504
4505 wait_timeout(50);
4506 }
4507
4508 if (chip->asic_code) {
4509 retval = sd_pull_ctl_disable(chip);
4510 if (retval != STATUS_SUCCESS)
4511 TRACE_RET(chip, STATUS_FAIL);
4512 } else {
4513 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4514 FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4515 }
4516
4517 return STATUS_SUCCESS;
4518 }
4519
release_sd_card(struct rtsx_chip * chip)4520 int release_sd_card(struct rtsx_chip *chip)
4521 {
4522 struct sd_info *sd_card = &(chip->sd_card);
4523 int retval;
4524
4525 chip->card_ready &= ~SD_CARD;
4526 chip->card_fail &= ~SD_CARD;
4527 chip->card_wp &= ~SD_CARD;
4528
4529 chip->sd_io = 0;
4530 chip->sd_int = 0;
4531
4532 #ifdef SUPPORT_SD_LOCK
4533 sd_card->sd_lock_status = 0;
4534 sd_card->sd_erase_status = 0;
4535 #endif
4536
4537 memset(sd_card->raw_csd, 0, 16);
4538 memset(sd_card->raw_scr, 0, 8);
4539
4540 retval = sd_power_off_card3v3(chip);
4541 if (retval != STATUS_SUCCESS)
4542 TRACE_RET(chip, STATUS_FAIL);
4543
4544 return STATUS_SUCCESS;
4545 }
4546