1 /*
2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include "s5p_mfc_cmd.h"
19 #include "s5p_mfc_common.h"
20 #include "s5p_mfc_debug.h"
21 #include "s5p_mfc_intr.h"
22 #include "s5p_mfc_opr.h"
23 #include "s5p_mfc_pm.h"
24 #include "s5p_mfc_ctrl.h"
25
26 /* Allocate memory for firmware */
s5p_mfc_alloc_firmware(struct s5p_mfc_dev * dev)27 int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
28 {
29 void *bank2_virt;
30 dma_addr_t bank2_dma_addr;
31
32 dev->fw_size = dev->variant->buf_size->fw;
33
34 if (dev->fw_virt_addr) {
35 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
36 return -ENOMEM;
37 }
38
39 dev->fw_virt_addr = dma_alloc_coherent(dev->mem_dev_l, dev->fw_size,
40 &dev->bank1, GFP_KERNEL);
41
42 if (!dev->fw_virt_addr) {
43 mfc_err("Allocating bitprocessor buffer failed\n");
44 return -ENOMEM;
45 }
46
47 if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) {
48 bank2_virt = dma_alloc_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER,
49 &bank2_dma_addr, GFP_KERNEL);
50
51 if (!bank2_virt) {
52 mfc_err("Allocating bank2 base failed\n");
53 dma_free_coherent(dev->mem_dev_l, dev->fw_size,
54 dev->fw_virt_addr, dev->bank1);
55 dev->fw_virt_addr = NULL;
56 return -ENOMEM;
57 }
58
59 /* Valid buffers passed to MFC encoder with LAST_FRAME command
60 * should not have address of bank2 - MFC will treat it as a null frame.
61 * To avoid such situation we set bank2 address below the pool address.
62 */
63 dev->bank2 = bank2_dma_addr - (1 << MFC_BASE_ALIGN_ORDER);
64
65 dma_free_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER,
66 bank2_virt, bank2_dma_addr);
67
68 } else {
69 /* In this case bank2 can point to the same address as bank1.
70 * Firmware will always occupy the beginning of this area so it is
71 * impossible having a video frame buffer with zero address. */
72 dev->bank2 = dev->bank1;
73 }
74 return 0;
75 }
76
77 /* Load firmware */
s5p_mfc_load_firmware(struct s5p_mfc_dev * dev)78 int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
79 {
80 struct firmware *fw_blob;
81 int i, err = -EINVAL;
82
83 /* Firmare has to be present as a separate file or compiled
84 * into kernel. */
85 mfc_debug_enter();
86
87 for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
88 if (!dev->variant->fw_name[i])
89 continue;
90 err = request_firmware((const struct firmware **)&fw_blob,
91 dev->variant->fw_name[i], dev->v4l2_dev.dev);
92 if (!err) {
93 dev->fw_ver = (enum s5p_mfc_fw_ver) i;
94 break;
95 }
96 }
97
98 if (err != 0) {
99 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
100 return -EINVAL;
101 }
102 if (fw_blob->size > dev->fw_size) {
103 mfc_err("MFC firmware is too big to be loaded\n");
104 release_firmware(fw_blob);
105 return -ENOMEM;
106 }
107 if (!dev->fw_virt_addr) {
108 mfc_err("MFC firmware is not allocated\n");
109 release_firmware(fw_blob);
110 return -EINVAL;
111 }
112 memcpy(dev->fw_virt_addr, fw_blob->data, fw_blob->size);
113 wmb();
114 release_firmware(fw_blob);
115 mfc_debug_leave();
116 return 0;
117 }
118
119 /* Release firmware memory */
s5p_mfc_release_firmware(struct s5p_mfc_dev * dev)120 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
121 {
122 /* Before calling this function one has to make sure
123 * that MFC is no longer processing */
124 if (!dev->fw_virt_addr)
125 return -EINVAL;
126 dma_free_coherent(dev->mem_dev_l, dev->fw_size, dev->fw_virt_addr,
127 dev->bank1);
128 dev->fw_virt_addr = NULL;
129 return 0;
130 }
131
132 /* Reset the device */
s5p_mfc_reset(struct s5p_mfc_dev * dev)133 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
134 {
135 unsigned int mc_status;
136 unsigned long timeout;
137 int i;
138
139 mfc_debug_enter();
140
141 if (IS_MFCV6_PLUS(dev)) {
142 /* Reset IP */
143 /* except RISC, reset */
144 mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6);
145 /* reset release */
146 mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6);
147
148 /* Zero Initialization of MFC registers */
149 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
150 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
151 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
152
153 for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
154 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
155
156 /* Reset */
157 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
158 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
159 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
160 } else {
161 /* Stop procedure */
162 /* reset RISC */
163 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
164 /* All reset except for MC */
165 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
166 mdelay(10);
167
168 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
169 /* Check MC status */
170 do {
171 if (time_after(jiffies, timeout)) {
172 mfc_err("Timeout while resetting MFC\n");
173 return -EIO;
174 }
175
176 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
177
178 } while (mc_status & 0x3);
179
180 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
181 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
182 }
183
184 mfc_debug_leave();
185 return 0;
186 }
187
s5p_mfc_init_memctrl(struct s5p_mfc_dev * dev)188 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
189 {
190 if (IS_MFCV6_PLUS(dev)) {
191 mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6);
192 mfc_debug(2, "Base Address : %pad\n", &dev->bank1);
193 } else {
194 mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
195 mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
196 mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
197 &dev->bank1, &dev->bank2);
198 }
199 }
200
s5p_mfc_clear_cmds(struct s5p_mfc_dev * dev)201 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
202 {
203 if (IS_MFCV6_PLUS(dev)) {
204 /* Zero initialization should be done before RESET.
205 * Nothing to do here. */
206 } else {
207 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
208 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
209 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
210 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
211 }
212 }
213
214 /* Initialize hardware */
s5p_mfc_init_hw(struct s5p_mfc_dev * dev)215 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
216 {
217 unsigned int ver;
218 int ret;
219
220 mfc_debug_enter();
221 if (!dev->fw_virt_addr) {
222 mfc_err("Firmware memory is not allocated.\n");
223 return -EINVAL;
224 }
225
226 /* 0. MFC reset */
227 mfc_debug(2, "MFC reset..\n");
228 s5p_mfc_clock_on();
229 ret = s5p_mfc_reset(dev);
230 if (ret) {
231 mfc_err("Failed to reset MFC - timeout\n");
232 return ret;
233 }
234 mfc_debug(2, "Done MFC reset..\n");
235 /* 1. Set DRAM base Addr */
236 s5p_mfc_init_memctrl(dev);
237 /* 2. Initialize registers of channel I/F */
238 s5p_mfc_clear_cmds(dev);
239 /* 3. Release reset signal to the RISC */
240 s5p_mfc_clean_dev_int_flags(dev);
241 if (IS_MFCV6_PLUS(dev))
242 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
243 else
244 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
245 mfc_debug(2, "Will now wait for completion of firmware transfer\n");
246 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
247 mfc_err("Failed to load firmware\n");
248 s5p_mfc_reset(dev);
249 s5p_mfc_clock_off();
250 return -EIO;
251 }
252 s5p_mfc_clean_dev_int_flags(dev);
253 /* 4. Initialize firmware */
254 ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
255 if (ret) {
256 mfc_err("Failed to send command to MFC - timeout\n");
257 s5p_mfc_reset(dev);
258 s5p_mfc_clock_off();
259 return ret;
260 }
261 mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
262 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
263 mfc_err("Failed to init hardware\n");
264 s5p_mfc_reset(dev);
265 s5p_mfc_clock_off();
266 return -EIO;
267 }
268 dev->int_cond = 0;
269 if (dev->int_err != 0 || dev->int_type !=
270 S5P_MFC_R2H_CMD_SYS_INIT_RET) {
271 /* Failure. */
272 mfc_err("Failed to init firmware - error: %d int: %d\n",
273 dev->int_err, dev->int_type);
274 s5p_mfc_reset(dev);
275 s5p_mfc_clock_off();
276 return -EIO;
277 }
278 if (IS_MFCV6_PLUS(dev))
279 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
280 else
281 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
282
283 mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
284 (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
285 s5p_mfc_clock_off();
286 mfc_debug_leave();
287 return 0;
288 }
289
290
291 /* Deinitialize hardware */
s5p_mfc_deinit_hw(struct s5p_mfc_dev * dev)292 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
293 {
294 s5p_mfc_clock_on();
295
296 s5p_mfc_reset(dev);
297 s5p_mfc_hw_call_void(dev->mfc_ops, release_dev_context_buffer, dev);
298
299 s5p_mfc_clock_off();
300 }
301
s5p_mfc_sleep(struct s5p_mfc_dev * dev)302 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
303 {
304 int ret;
305
306 mfc_debug_enter();
307 s5p_mfc_clock_on();
308 s5p_mfc_clean_dev_int_flags(dev);
309 ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
310 if (ret) {
311 mfc_err("Failed to send command to MFC - timeout\n");
312 return ret;
313 }
314 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
315 mfc_err("Failed to sleep\n");
316 return -EIO;
317 }
318 s5p_mfc_clock_off();
319 dev->int_cond = 0;
320 if (dev->int_err != 0 || dev->int_type !=
321 S5P_MFC_R2H_CMD_SLEEP_RET) {
322 /* Failure. */
323 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
324 dev->int_type);
325 return -EIO;
326 }
327 mfc_debug_leave();
328 return ret;
329 }
330
s5p_mfc_wakeup(struct s5p_mfc_dev * dev)331 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
332 {
333 int ret;
334
335 mfc_debug_enter();
336 /* 0. MFC reset */
337 mfc_debug(2, "MFC reset..\n");
338 s5p_mfc_clock_on();
339 ret = s5p_mfc_reset(dev);
340 if (ret) {
341 mfc_err("Failed to reset MFC - timeout\n");
342 return ret;
343 }
344 mfc_debug(2, "Done MFC reset..\n");
345 /* 1. Set DRAM base Addr */
346 s5p_mfc_init_memctrl(dev);
347 /* 2. Initialize registers of channel I/F */
348 s5p_mfc_clear_cmds(dev);
349 s5p_mfc_clean_dev_int_flags(dev);
350 /* 3. Initialize firmware */
351 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
352 if (ret) {
353 mfc_err("Failed to send command to MFC - timeout\n");
354 return ret;
355 }
356 /* 4. Release reset signal to the RISC */
357 if (IS_MFCV6_PLUS(dev))
358 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
359 else
360 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
361 mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
362 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
363 mfc_err("Failed to load firmware\n");
364 return -EIO;
365 }
366 s5p_mfc_clock_off();
367 dev->int_cond = 0;
368 if (dev->int_err != 0 || dev->int_type !=
369 S5P_MFC_R2H_CMD_WAKEUP_RET) {
370 /* Failure. */
371 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
372 dev->int_type);
373 return -EIO;
374 }
375 mfc_debug_leave();
376 return 0;
377 }
378
s5p_mfc_open_mfc_inst(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx)379 int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
380 {
381 int ret = 0;
382
383 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
384 if (ret) {
385 mfc_err("Failed allocating instance buffer\n");
386 goto err;
387 }
388
389 if (ctx->type == MFCINST_DECODER) {
390 ret = s5p_mfc_hw_call(dev->mfc_ops,
391 alloc_dec_temp_buffers, ctx);
392 if (ret) {
393 mfc_err("Failed allocating temporary buffers\n");
394 goto err_free_inst_buf;
395 }
396 }
397
398 set_work_bit_irqsave(ctx);
399 s5p_mfc_clean_ctx_int_flags(ctx);
400 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
401 if (s5p_mfc_wait_for_done_ctx(ctx,
402 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
403 /* Error or timeout */
404 mfc_err("Error getting instance from hardware\n");
405 ret = -EIO;
406 goto err_free_desc_buf;
407 }
408
409 mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
410 return ret;
411
412 err_free_desc_buf:
413 if (ctx->type == MFCINST_DECODER)
414 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
415 err_free_inst_buf:
416 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
417 err:
418 return ret;
419 }
420
s5p_mfc_close_mfc_inst(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx)421 void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
422 {
423 ctx->state = MFCINST_RETURN_INST;
424 set_work_bit_irqsave(ctx);
425 s5p_mfc_clean_ctx_int_flags(ctx);
426 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
427 /* Wait until instance is returned or timeout occurred */
428 if (s5p_mfc_wait_for_done_ctx(ctx,
429 S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
430 mfc_err("Err returning instance\n");
431
432 /* Free resources */
433 s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx);
434 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
435 if (ctx->type == MFCINST_DECODER)
436 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
437
438 ctx->inst_no = MFC_NO_INSTANCE_SET;
439 ctx->state = MFCINST_FREE;
440 }
441