1 /*
2 * linux/arch/arm/mach-sa1100/generic.c
3 *
4 * Author: Nicolas Pitre
5 *
6 * Code common to all SA11x0 machines.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/gpio.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/pm.h>
19 #include <linux/cpufreq.h>
20 #include <linux/ioport.h>
21 #include <linux/platform_device.h>
22 #include <linux/reboot.h>
23
24 #include <video/sa1100fb.h>
25
26 #include <asm/div64.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/flash.h>
29 #include <asm/irq.h>
30 #include <asm/system_misc.h>
31
32 #include <mach/hardware.h>
33 #include <mach/irqs.h>
34
35 #include "generic.h"
36
37 unsigned int reset_status;
38 EXPORT_SYMBOL(reset_status);
39
40 #define NR_FREQS 16
41
42 /*
43 * This table is setup for a 3.6864MHz Crystal.
44 */
45 struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
46 { .frequency = 59000, /* 59.0 MHz */},
47 { .frequency = 73700, /* 73.7 MHz */},
48 { .frequency = 88500, /* 88.5 MHz */},
49 { .frequency = 103200, /* 103.2 MHz */},
50 { .frequency = 118000, /* 118.0 MHz */},
51 { .frequency = 132700, /* 132.7 MHz */},
52 { .frequency = 147500, /* 147.5 MHz */},
53 { .frequency = 162200, /* 162.2 MHz */},
54 { .frequency = 176900, /* 176.9 MHz */},
55 { .frequency = 191700, /* 191.7 MHz */},
56 { .frequency = 206400, /* 206.4 MHz */},
57 { .frequency = 221200, /* 221.2 MHz */},
58 { .frequency = 235900, /* 235.9 MHz */},
59 { .frequency = 250700, /* 250.7 MHz */},
60 { .frequency = 265400, /* 265.4 MHz */},
61 { .frequency = 280200, /* 280.2 MHz */},
62 { .frequency = CPUFREQ_TABLE_END, },
63 };
64
sa11x0_getspeed(unsigned int cpu)65 unsigned int sa11x0_getspeed(unsigned int cpu)
66 {
67 if (cpu)
68 return 0;
69 return sa11x0_freq_table[PPCR & 0xf].frequency;
70 }
71
72 /*
73 * Default power-off for SA1100
74 */
sa1100_power_off(void)75 static void sa1100_power_off(void)
76 {
77 mdelay(100);
78 local_irq_disable();
79 /* disable internal oscillator, float CS lines */
80 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
81 /* enable wake-up on GPIO0 (Assabet...) */
82 PWER = GFER = GRER = 1;
83 /*
84 * set scratchpad to zero, just in case it is used as a
85 * restart address by the bootloader.
86 */
87 PSPR = 0;
88 /* enter sleep mode */
89 PMCR = PMCR_SF;
90 }
91
sa11x0_restart(enum reboot_mode mode,const char * cmd)92 void sa11x0_restart(enum reboot_mode mode, const char *cmd)
93 {
94 if (mode == REBOOT_SOFT) {
95 /* Jump into ROM at address 0 */
96 soft_restart(0);
97 } else {
98 /* Use on-chip reset capability */
99 RSRR = RSRR_SWR;
100 }
101 }
102
sa11x0_register_device(struct platform_device * dev,void * data)103 static void sa11x0_register_device(struct platform_device *dev, void *data)
104 {
105 int err;
106 dev->dev.platform_data = data;
107 err = platform_device_register(dev);
108 if (err)
109 printk(KERN_ERR "Unable to register device %s: %d\n",
110 dev->name, err);
111 }
112
113
114 static struct resource sa11x0udc_resources[] = {
115 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
116 [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
117 };
118
119 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
120
121 static struct platform_device sa11x0udc_device = {
122 .name = "sa11x0-udc",
123 .id = -1,
124 .dev = {
125 .dma_mask = &sa11x0udc_dma_mask,
126 .coherent_dma_mask = 0xffffffff,
127 },
128 .num_resources = ARRAY_SIZE(sa11x0udc_resources),
129 .resource = sa11x0udc_resources,
130 };
131
132 static struct resource sa11x0uart1_resources[] = {
133 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
134 [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
135 };
136
137 static struct platform_device sa11x0uart1_device = {
138 .name = "sa11x0-uart",
139 .id = 1,
140 .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
141 .resource = sa11x0uart1_resources,
142 };
143
144 static struct resource sa11x0uart3_resources[] = {
145 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
146 [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
147 };
148
149 static struct platform_device sa11x0uart3_device = {
150 .name = "sa11x0-uart",
151 .id = 3,
152 .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
153 .resource = sa11x0uart3_resources,
154 };
155
156 static struct resource sa11x0mcp_resources[] = {
157 [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
158 [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
159 [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
160 };
161
162 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
163
164 static struct platform_device sa11x0mcp_device = {
165 .name = "sa11x0-mcp",
166 .id = -1,
167 .dev = {
168 .dma_mask = &sa11x0mcp_dma_mask,
169 .coherent_dma_mask = 0xffffffff,
170 },
171 .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
172 .resource = sa11x0mcp_resources,
173 };
174
sa11x0_ppc_configure_mcp(void)175 void __init sa11x0_ppc_configure_mcp(void)
176 {
177 /* Setup the PPC unit for the MCP */
178 PPDR &= ~PPC_RXD4;
179 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
180 PSDR |= PPC_RXD4;
181 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
182 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
183 }
184
sa11x0_register_mcp(struct mcp_plat_data * data)185 void sa11x0_register_mcp(struct mcp_plat_data *data)
186 {
187 sa11x0_register_device(&sa11x0mcp_device, data);
188 }
189
190 static struct resource sa11x0ssp_resources[] = {
191 [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
192 [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
193 };
194
195 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
196
197 static struct platform_device sa11x0ssp_device = {
198 .name = "sa11x0-ssp",
199 .id = -1,
200 .dev = {
201 .dma_mask = &sa11x0ssp_dma_mask,
202 .coherent_dma_mask = 0xffffffff,
203 },
204 .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
205 .resource = sa11x0ssp_resources,
206 };
207
208 static struct resource sa11x0fb_resources[] = {
209 [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
210 [1] = DEFINE_RES_IRQ(IRQ_LCD),
211 };
212
213 static struct platform_device sa11x0fb_device = {
214 .name = "sa11x0-fb",
215 .id = -1,
216 .dev = {
217 .coherent_dma_mask = 0xffffffff,
218 },
219 .num_resources = ARRAY_SIZE(sa11x0fb_resources),
220 .resource = sa11x0fb_resources,
221 };
222
sa11x0_register_lcd(struct sa1100fb_mach_info * inf)223 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
224 {
225 sa11x0_register_device(&sa11x0fb_device, inf);
226 }
227
228 static struct platform_device sa11x0pcmcia_device = {
229 .name = "sa11x0-pcmcia",
230 .id = -1,
231 };
232
233 static struct platform_device sa11x0mtd_device = {
234 .name = "sa1100-mtd",
235 .id = -1,
236 };
237
sa11x0_register_mtd(struct flash_platform_data * flash,struct resource * res,int nr)238 void sa11x0_register_mtd(struct flash_platform_data *flash,
239 struct resource *res, int nr)
240 {
241 flash->name = "sa1100";
242 sa11x0mtd_device.resource = res;
243 sa11x0mtd_device.num_resources = nr;
244 sa11x0_register_device(&sa11x0mtd_device, flash);
245 }
246
247 static struct resource sa11x0ir_resources[] = {
248 DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
249 DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
250 DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
251 DEFINE_RES_IRQ(IRQ_Ser2ICP),
252 };
253
254 static struct platform_device sa11x0ir_device = {
255 .name = "sa11x0-ir",
256 .id = -1,
257 .num_resources = ARRAY_SIZE(sa11x0ir_resources),
258 .resource = sa11x0ir_resources,
259 };
260
sa11x0_register_irda(struct irda_platform_data * irda)261 void sa11x0_register_irda(struct irda_platform_data *irda)
262 {
263 sa11x0_register_device(&sa11x0ir_device, irda);
264 }
265
266 static struct resource sa1100_rtc_resources[] = {
267 DEFINE_RES_MEM(0x90010000, 0x40),
268 DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
269 DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
270 };
271
272 static struct platform_device sa11x0rtc_device = {
273 .name = "sa1100-rtc",
274 .id = -1,
275 .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
276 .resource = sa1100_rtc_resources,
277 };
278
279 static struct resource sa11x0dma_resources[] = {
280 DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
281 DEFINE_RES_IRQ(IRQ_DMA0),
282 DEFINE_RES_IRQ(IRQ_DMA1),
283 DEFINE_RES_IRQ(IRQ_DMA2),
284 DEFINE_RES_IRQ(IRQ_DMA3),
285 DEFINE_RES_IRQ(IRQ_DMA4),
286 DEFINE_RES_IRQ(IRQ_DMA5),
287 };
288
289 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
290
291 static struct platform_device sa11x0dma_device = {
292 .name = "sa11x0-dma",
293 .id = -1,
294 .dev = {
295 .dma_mask = &sa11x0dma_dma_mask,
296 .coherent_dma_mask = 0xffffffff,
297 },
298 .num_resources = ARRAY_SIZE(sa11x0dma_resources),
299 .resource = sa11x0dma_resources,
300 };
301
302 static struct platform_device *sa11x0_devices[] __initdata = {
303 &sa11x0udc_device,
304 &sa11x0uart1_device,
305 &sa11x0uart3_device,
306 &sa11x0ssp_device,
307 &sa11x0pcmcia_device,
308 &sa11x0rtc_device,
309 &sa11x0dma_device,
310 };
311
sa1100_init(void)312 static int __init sa1100_init(void)
313 {
314 pm_power_off = sa1100_power_off;
315 return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
316 }
317
318 arch_initcall(sa1100_init);
319
sa11x0_init_late(void)320 void __init sa11x0_init_late(void)
321 {
322 sa11x0_pm_init();
323 }
324
325 /*
326 * Common I/O mapping:
327 *
328 * Typically, static virtual address mappings are as follow:
329 *
330 * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
331 * 0xf4000000-0xf4ffffff: SA-1111
332 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
333 * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
334 * 0xffff0000-0xffff0fff: SA1100 exception vectors
335 * 0xffff2000-0xffff2fff: Minicache copy_user_page area
336 *
337 * Below 0xe8000000 is reserved for vm allocation.
338 *
339 * The machine specific code must provide the extra mapping beside the
340 * default mapping provided here.
341 */
342
343 static struct map_desc standard_io_desc[] __initdata = {
344 { /* PCM */
345 .virtual = 0xf8000000,
346 .pfn = __phys_to_pfn(0x80000000),
347 .length = 0x00100000,
348 .type = MT_DEVICE
349 }, { /* SCM */
350 .virtual = 0xfa000000,
351 .pfn = __phys_to_pfn(0x90000000),
352 .length = 0x00100000,
353 .type = MT_DEVICE
354 }, { /* MER */
355 .virtual = 0xfc000000,
356 .pfn = __phys_to_pfn(0xa0000000),
357 .length = 0x00100000,
358 .type = MT_DEVICE
359 }, { /* LCD + DMA */
360 .virtual = 0xfe000000,
361 .pfn = __phys_to_pfn(0xb0000000),
362 .length = 0x00200000,
363 .type = MT_DEVICE
364 },
365 };
366
sa1100_map_io(void)367 void __init sa1100_map_io(void)
368 {
369 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
370 }
371
372 /*
373 * Disable the memory bus request/grant signals on the SA1110 to
374 * ensure that we don't receive spurious memory requests. We set
375 * the MBGNT signal false to ensure the SA1111 doesn't own the
376 * SDRAM bus.
377 */
sa1110_mb_disable(void)378 void sa1110_mb_disable(void)
379 {
380 unsigned long flags;
381
382 local_irq_save(flags);
383
384 PGSR &= ~GPIO_MBGNT;
385 GPCR = GPIO_MBGNT;
386 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
387
388 GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
389
390 local_irq_restore(flags);
391 }
392
393 /*
394 * If the system is going to use the SA-1111 DMA engines, set up
395 * the memory bus request/grant pins.
396 */
sa1110_mb_enable(void)397 void sa1110_mb_enable(void)
398 {
399 unsigned long flags;
400
401 local_irq_save(flags);
402
403 PGSR &= ~GPIO_MBGNT;
404 GPCR = GPIO_MBGNT;
405 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
406
407 GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
408 TUCR |= TUCR_MR;
409
410 local_irq_restore(flags);
411 }
412
413