1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
52
53 /* General customization:
54 */
55
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20140905"
59
60 enum pipe {
61 INVALID_PIPE = -1,
62 PIPE_A = 0,
63 PIPE_B,
64 PIPE_C,
65 _PIPE_EDP,
66 I915_MAX_PIPES = _PIPE_EDP
67 };
68 #define pipe_name(p) ((p) + 'A')
69
70 enum transcoder {
71 TRANSCODER_A = 0,
72 TRANSCODER_B,
73 TRANSCODER_C,
74 TRANSCODER_EDP,
75 I915_MAX_TRANSCODERS
76 };
77 #define transcoder_name(t) ((t) + 'A')
78
79 enum plane {
80 PLANE_A = 0,
81 PLANE_B,
82 PLANE_C,
83 };
84 #define plane_name(p) ((p) + 'A')
85
86 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
87
88 enum port {
89 PORT_A = 0,
90 PORT_B,
91 PORT_C,
92 PORT_D,
93 PORT_E,
94 I915_MAX_PORTS
95 };
96 #define port_name(p) ((p) + 'A')
97
98 #define I915_NUM_PHYS_VLV 2
99
100 enum dpio_channel {
101 DPIO_CH0,
102 DPIO_CH1
103 };
104
105 enum dpio_phy {
106 DPIO_PHY0,
107 DPIO_PHY1
108 };
109
110 enum intel_display_power_domain {
111 POWER_DOMAIN_PIPE_A,
112 POWER_DOMAIN_PIPE_B,
113 POWER_DOMAIN_PIPE_C,
114 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
115 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
116 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
117 POWER_DOMAIN_TRANSCODER_A,
118 POWER_DOMAIN_TRANSCODER_B,
119 POWER_DOMAIN_TRANSCODER_C,
120 POWER_DOMAIN_TRANSCODER_EDP,
121 POWER_DOMAIN_PORT_DDI_A_2_LANES,
122 POWER_DOMAIN_PORT_DDI_A_4_LANES,
123 POWER_DOMAIN_PORT_DDI_B_2_LANES,
124 POWER_DOMAIN_PORT_DDI_B_4_LANES,
125 POWER_DOMAIN_PORT_DDI_C_2_LANES,
126 POWER_DOMAIN_PORT_DDI_C_4_LANES,
127 POWER_DOMAIN_PORT_DDI_D_2_LANES,
128 POWER_DOMAIN_PORT_DDI_D_4_LANES,
129 POWER_DOMAIN_PORT_DSI,
130 POWER_DOMAIN_PORT_CRT,
131 POWER_DOMAIN_PORT_OTHER,
132 POWER_DOMAIN_VGA,
133 POWER_DOMAIN_AUDIO,
134 POWER_DOMAIN_PLLS,
135 POWER_DOMAIN_INIT,
136
137 POWER_DOMAIN_NUM,
138 };
139
140 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
141 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
142 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
143 #define POWER_DOMAIN_TRANSCODER(tran) \
144 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
145 (tran) + POWER_DOMAIN_TRANSCODER_A)
146
147 enum hpd_pin {
148 HPD_NONE = 0,
149 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
150 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
151 HPD_CRT,
152 HPD_SDVO_B,
153 HPD_SDVO_C,
154 HPD_PORT_B,
155 HPD_PORT_C,
156 HPD_PORT_D,
157 HPD_NUM_PINS
158 };
159
160 #define I915_GEM_GPU_DOMAINS \
161 (I915_GEM_DOMAIN_RENDER | \
162 I915_GEM_DOMAIN_SAMPLER | \
163 I915_GEM_DOMAIN_COMMAND | \
164 I915_GEM_DOMAIN_INSTRUCTION | \
165 I915_GEM_DOMAIN_VERTEX)
166
167 #define for_each_pipe(__dev_priv, __p) \
168 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
169 #define for_each_plane(pipe, p) \
170 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
171 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
172
173 #define for_each_crtc(dev, crtc) \
174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
175
176 #define for_each_intel_crtc(dev, intel_crtc) \
177 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
178
179 #define for_each_intel_encoder(dev, intel_encoder) \
180 list_for_each_entry(intel_encoder, \
181 &(dev)->mode_config.encoder_list, \
182 base.head)
183
184 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
185 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
186 if ((intel_encoder)->base.crtc == (__crtc))
187
188 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
189 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
190 if ((intel_connector)->base.encoder == (__encoder))
191
192 #define for_each_power_domain(domain, mask) \
193 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
194 if ((1 << (domain)) & (mask))
195
196 struct drm_i915_private;
197 struct i915_mm_struct;
198 struct i915_mmu_object;
199
200 enum intel_dpll_id {
201 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
202 /* real shared dpll ids must be >= 0 */
203 DPLL_ID_PCH_PLL_A = 0,
204 DPLL_ID_PCH_PLL_B = 1,
205 DPLL_ID_WRPLL1 = 0,
206 DPLL_ID_WRPLL2 = 1,
207 };
208 #define I915_NUM_PLLS 2
209
210 struct intel_dpll_hw_state {
211 /* i9xx, pch plls */
212 uint32_t dpll;
213 uint32_t dpll_md;
214 uint32_t fp0;
215 uint32_t fp1;
216
217 /* hsw, bdw */
218 uint32_t wrpll;
219 };
220
221 struct intel_shared_dpll {
222 int refcount; /* count of number of CRTCs sharing this PLL */
223 int active; /* count of number of active CRTCs (i.e. DPMS on) */
224 bool on; /* is the PLL actually active? Disabled during modeset */
225 const char *name;
226 /* should match the index in the dev_priv->shared_dplls array */
227 enum intel_dpll_id id;
228 struct intel_dpll_hw_state hw_state;
229 /* The mode_set hook is optional and should be used together with the
230 * intel_prepare_shared_dpll function. */
231 void (*mode_set)(struct drm_i915_private *dev_priv,
232 struct intel_shared_dpll *pll);
233 void (*enable)(struct drm_i915_private *dev_priv,
234 struct intel_shared_dpll *pll);
235 void (*disable)(struct drm_i915_private *dev_priv,
236 struct intel_shared_dpll *pll);
237 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
238 struct intel_shared_dpll *pll,
239 struct intel_dpll_hw_state *hw_state);
240 };
241
242 /* Used by dp and fdi links */
243 struct intel_link_m_n {
244 uint32_t tu;
245 uint32_t gmch_m;
246 uint32_t gmch_n;
247 uint32_t link_m;
248 uint32_t link_n;
249 };
250
251 void intel_link_compute_m_n(int bpp, int nlanes,
252 int pixel_clock, int link_clock,
253 struct intel_link_m_n *m_n);
254
255 /* Interface history:
256 *
257 * 1.1: Original.
258 * 1.2: Add Power Management
259 * 1.3: Add vblank support
260 * 1.4: Fix cmdbuffer path, add heap destroy
261 * 1.5: Add vblank pipe configuration
262 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
263 * - Support vertical blank on secondary display pipe
264 */
265 #define DRIVER_MAJOR 1
266 #define DRIVER_MINOR 6
267 #define DRIVER_PATCHLEVEL 0
268
269 #define WATCH_LISTS 0
270 #define WATCH_GTT 0
271
272 struct opregion_header;
273 struct opregion_acpi;
274 struct opregion_swsci;
275 struct opregion_asle;
276
277 struct intel_opregion {
278 struct opregion_header __iomem *header;
279 struct opregion_acpi __iomem *acpi;
280 struct opregion_swsci __iomem *swsci;
281 u32 swsci_gbda_sub_functions;
282 u32 swsci_sbcb_sub_functions;
283 struct opregion_asle __iomem *asle;
284 void __iomem *vbt;
285 u32 __iomem *lid_state;
286 struct work_struct asle_work;
287 };
288 #define OPREGION_SIZE (8*1024)
289
290 struct intel_overlay;
291 struct intel_overlay_error_state;
292
293 struct drm_local_map;
294
295 struct drm_i915_master_private {
296 struct drm_local_map *sarea;
297 struct _drm_i915_sarea *sarea_priv;
298 };
299 #define I915_FENCE_REG_NONE -1
300 #define I915_MAX_NUM_FENCES 32
301 /* 32 fences + sign bit for FENCE_REG_NONE */
302 #define I915_MAX_NUM_FENCE_BITS 6
303
304 struct drm_i915_fence_reg {
305 struct list_head lru_list;
306 struct drm_i915_gem_object *obj;
307 int pin_count;
308 };
309
310 struct sdvo_device_mapping {
311 u8 initialized;
312 u8 dvo_port;
313 u8 slave_addr;
314 u8 dvo_wiring;
315 u8 i2c_pin;
316 u8 ddc_pin;
317 };
318
319 struct intel_display_error_state;
320
321 struct drm_i915_error_state {
322 struct kref ref;
323 struct timeval time;
324
325 char error_msg[128];
326 u32 reset_count;
327 u32 suspend_count;
328
329 /* Generic register state */
330 u32 eir;
331 u32 pgtbl_er;
332 u32 ier;
333 u32 gtier[4];
334 u32 ccid;
335 u32 derrmr;
336 u32 forcewake;
337 u32 error; /* gen6+ */
338 u32 err_int; /* gen7 */
339 u32 done_reg;
340 u32 gac_eco;
341 u32 gam_ecochk;
342 u32 gab_ctl;
343 u32 gfx_mode;
344 u32 extra_instdone[I915_NUM_INSTDONE_REG];
345 u64 fence[I915_MAX_NUM_FENCES];
346 struct intel_overlay_error_state *overlay;
347 struct intel_display_error_state *display;
348 struct drm_i915_error_object *semaphore_obj;
349
350 struct drm_i915_error_ring {
351 bool valid;
352 /* Software tracked state */
353 bool waiting;
354 int hangcheck_score;
355 enum intel_ring_hangcheck_action hangcheck_action;
356 int num_requests;
357
358 /* our own tracking of ring head and tail */
359 u32 cpu_ring_head;
360 u32 cpu_ring_tail;
361
362 u32 semaphore_seqno[I915_NUM_RINGS - 1];
363
364 /* Register state */
365 u32 tail;
366 u32 head;
367 u32 ctl;
368 u32 hws;
369 u32 ipeir;
370 u32 ipehr;
371 u32 instdone;
372 u32 bbstate;
373 u32 instpm;
374 u32 instps;
375 u32 seqno;
376 u64 bbaddr;
377 u64 acthd;
378 u32 fault_reg;
379 u64 faddr;
380 u32 rc_psmi; /* sleep state */
381 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
382
383 struct drm_i915_error_object {
384 int page_count;
385 u32 gtt_offset;
386 u32 *pages[0];
387 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
388
389 struct drm_i915_error_request {
390 long jiffies;
391 u32 seqno;
392 u32 tail;
393 } *requests;
394
395 struct {
396 u32 gfx_mode;
397 union {
398 u64 pdp[4];
399 u32 pp_dir_base;
400 };
401 } vm_info;
402
403 pid_t pid;
404 char comm[TASK_COMM_LEN];
405 } ring[I915_NUM_RINGS];
406
407 struct drm_i915_error_buffer {
408 u32 size;
409 u32 name;
410 u32 rseqno, wseqno;
411 u32 gtt_offset;
412 u32 read_domains;
413 u32 write_domain;
414 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
415 s32 pinned:2;
416 u32 tiling:2;
417 u32 dirty:1;
418 u32 purgeable:1;
419 u32 userptr:1;
420 s32 ring:4;
421 u32 cache_level:3;
422 } **active_bo, **pinned_bo;
423
424 u32 *active_bo_count, *pinned_bo_count;
425 u32 vm_count;
426 };
427
428 struct intel_connector;
429 struct intel_crtc_config;
430 struct intel_plane_config;
431 struct intel_crtc;
432 struct intel_limit;
433 struct dpll;
434
435 struct drm_i915_display_funcs {
436 bool (*fbc_enabled)(struct drm_device *dev);
437 void (*enable_fbc)(struct drm_crtc *crtc);
438 void (*disable_fbc)(struct drm_device *dev);
439 int (*get_display_clock_speed)(struct drm_device *dev);
440 int (*get_fifo_size)(struct drm_device *dev, int plane);
441 /**
442 * find_dpll() - Find the best values for the PLL
443 * @limit: limits for the PLL
444 * @crtc: current CRTC
445 * @target: target frequency in kHz
446 * @refclk: reference clock frequency in kHz
447 * @match_clock: if provided, @best_clock P divider must
448 * match the P divider from @match_clock
449 * used for LVDS downclocking
450 * @best_clock: best PLL values found
451 *
452 * Returns true on success, false on failure.
453 */
454 bool (*find_dpll)(const struct intel_limit *limit,
455 struct drm_crtc *crtc,
456 int target, int refclk,
457 struct dpll *match_clock,
458 struct dpll *best_clock);
459 void (*update_wm)(struct drm_crtc *crtc);
460 void (*update_sprite_wm)(struct drm_plane *plane,
461 struct drm_crtc *crtc,
462 uint32_t sprite_width, uint32_t sprite_height,
463 int pixel_size, bool enable, bool scaled);
464 void (*modeset_global_resources)(struct drm_device *dev);
465 /* Returns the active state of the crtc, and if the crtc is active,
466 * fills out the pipe-config with the hw state. */
467 bool (*get_pipe_config)(struct intel_crtc *,
468 struct intel_crtc_config *);
469 void (*get_plane_config)(struct intel_crtc *,
470 struct intel_plane_config *);
471 int (*crtc_mode_set)(struct drm_crtc *crtc,
472 int x, int y,
473 struct drm_framebuffer *old_fb);
474 void (*crtc_enable)(struct drm_crtc *crtc);
475 void (*crtc_disable)(struct drm_crtc *crtc);
476 void (*off)(struct drm_crtc *crtc);
477 void (*write_eld)(struct drm_connector *connector,
478 struct drm_crtc *crtc,
479 struct drm_display_mode *mode);
480 void (*fdi_link_train)(struct drm_crtc *crtc);
481 void (*init_clock_gating)(struct drm_device *dev);
482 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
483 struct drm_framebuffer *fb,
484 struct drm_i915_gem_object *obj,
485 struct intel_engine_cs *ring,
486 uint32_t flags);
487 void (*update_primary_plane)(struct drm_crtc *crtc,
488 struct drm_framebuffer *fb,
489 int x, int y);
490 void (*hpd_irq_setup)(struct drm_device *dev);
491 /* clock updates for mode set */
492 /* cursor updates */
493 /* render clock increase/decrease */
494 /* display clock increase/decrease */
495 /* pll clock increase/decrease */
496
497 int (*setup_backlight)(struct intel_connector *connector);
498 uint32_t (*get_backlight)(struct intel_connector *connector);
499 void (*set_backlight)(struct intel_connector *connector,
500 uint32_t level);
501 void (*disable_backlight)(struct intel_connector *connector);
502 void (*enable_backlight)(struct intel_connector *connector);
503 };
504
505 struct intel_uncore_funcs {
506 void (*force_wake_get)(struct drm_i915_private *dev_priv,
507 int fw_engine);
508 void (*force_wake_put)(struct drm_i915_private *dev_priv,
509 int fw_engine);
510
511 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
512 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
513 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
514 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
515
516 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
517 uint8_t val, bool trace);
518 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
519 uint16_t val, bool trace);
520 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
521 uint32_t val, bool trace);
522 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
523 uint64_t val, bool trace);
524 };
525
526 struct intel_uncore {
527 spinlock_t lock; /** lock is also taken in irq contexts. */
528
529 struct intel_uncore_funcs funcs;
530
531 unsigned fifo_count;
532 unsigned forcewake_count;
533
534 unsigned fw_rendercount;
535 unsigned fw_mediacount;
536
537 struct timer_list force_wake_timer;
538 };
539
540 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
541 func(is_mobile) sep \
542 func(is_i85x) sep \
543 func(is_i915g) sep \
544 func(is_i945gm) sep \
545 func(is_g33) sep \
546 func(need_gfx_hws) sep \
547 func(is_g4x) sep \
548 func(is_pineview) sep \
549 func(is_broadwater) sep \
550 func(is_crestline) sep \
551 func(is_ivybridge) sep \
552 func(is_valleyview) sep \
553 func(is_haswell) sep \
554 func(is_preliminary) sep \
555 func(has_fbc) sep \
556 func(has_pipe_cxsr) sep \
557 func(has_hotplug) sep \
558 func(cursor_needs_physical) sep \
559 func(has_overlay) sep \
560 func(overlay_needs_physical) sep \
561 func(supports_tv) sep \
562 func(has_llc) sep \
563 func(has_ddi) sep \
564 func(has_fpga_dbg)
565
566 #define DEFINE_FLAG(name) u8 name:1
567 #define SEP_SEMICOLON ;
568
569 struct intel_device_info {
570 u32 display_mmio_offset;
571 u16 device_id;
572 u8 num_pipes:3;
573 u8 num_sprites[I915_MAX_PIPES];
574 u8 gen;
575 u8 ring_mask; /* Rings supported by the HW */
576 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
577 /* Register offsets for the various display pipes and transcoders */
578 int pipe_offsets[I915_MAX_TRANSCODERS];
579 int trans_offsets[I915_MAX_TRANSCODERS];
580 int palette_offsets[I915_MAX_PIPES];
581 int cursor_offsets[I915_MAX_PIPES];
582 };
583
584 #undef DEFINE_FLAG
585 #undef SEP_SEMICOLON
586
587 enum i915_cache_level {
588 I915_CACHE_NONE = 0,
589 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
590 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
591 caches, eg sampler/render caches, and the
592 large Last-Level-Cache. LLC is coherent with
593 the CPU, but L3 is only visible to the GPU. */
594 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
595 };
596
597 struct i915_ctx_hang_stats {
598 /* This context had batch pending when hang was declared */
599 unsigned batch_pending;
600
601 /* This context had batch active when hang was declared */
602 unsigned batch_active;
603
604 /* Time when this context was last blamed for a GPU reset */
605 unsigned long guilty_ts;
606
607 /* This context is banned to submit more work */
608 bool banned;
609 };
610
611 /* This must match up with the value previously used for execbuf2.rsvd1. */
612 #define DEFAULT_CONTEXT_HANDLE 0
613 /**
614 * struct intel_context - as the name implies, represents a context.
615 * @ref: reference count.
616 * @user_handle: userspace tracking identity for this context.
617 * @remap_slice: l3 row remapping information.
618 * @file_priv: filp associated with this context (NULL for global default
619 * context).
620 * @hang_stats: information about the role of this context in possible GPU
621 * hangs.
622 * @vm: virtual memory space used by this context.
623 * @legacy_hw_ctx: render context backing object and whether it is correctly
624 * initialized (legacy ring submission mechanism only).
625 * @link: link in the global list of contexts.
626 *
627 * Contexts are memory images used by the hardware to store copies of their
628 * internal state.
629 */
630 struct intel_context {
631 struct kref ref;
632 int user_handle;
633 uint8_t remap_slice;
634 struct drm_i915_file_private *file_priv;
635 struct i915_ctx_hang_stats hang_stats;
636 struct i915_hw_ppgtt *ppgtt;
637
638 /* Legacy ring buffer submission */
639 struct {
640 struct drm_i915_gem_object *rcs_state;
641 bool initialized;
642 } legacy_hw_ctx;
643
644 /* Execlists */
645 bool rcs_initialized;
646 struct {
647 struct drm_i915_gem_object *state;
648 struct intel_ringbuffer *ringbuf;
649 } engine[I915_NUM_RINGS];
650
651 struct list_head link;
652 };
653
654 struct i915_fbc {
655 unsigned long size;
656 unsigned threshold;
657 unsigned int fb_id;
658 enum plane plane;
659 int y;
660
661 struct drm_mm_node compressed_fb;
662 struct drm_mm_node *compressed_llb;
663
664 bool false_color;
665
666 struct intel_fbc_work {
667 struct delayed_work work;
668 struct drm_crtc *crtc;
669 struct drm_framebuffer *fb;
670 } *fbc_work;
671
672 enum no_fbc_reason {
673 FBC_OK, /* FBC is enabled */
674 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
675 FBC_NO_OUTPUT, /* no outputs enabled to compress */
676 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
677 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
678 FBC_MODE_TOO_LARGE, /* mode too large for compression */
679 FBC_BAD_PLANE, /* fbc not supported on plane */
680 FBC_NOT_TILED, /* buffer not tiled */
681 FBC_MULTIPLE_PIPES, /* more than one pipe active */
682 FBC_MODULE_PARAM,
683 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
684 } no_fbc_reason;
685 };
686
687 struct i915_drrs {
688 struct intel_connector *connector;
689 };
690
691 struct intel_dp;
692 struct i915_psr {
693 struct mutex lock;
694 bool sink_support;
695 bool source_ok;
696 struct intel_dp *enabled;
697 bool active;
698 struct delayed_work work;
699 unsigned busy_frontbuffer_bits;
700 };
701
702 enum intel_pch {
703 PCH_NONE = 0, /* No PCH present */
704 PCH_IBX, /* Ibexpeak PCH */
705 PCH_CPT, /* Cougarpoint PCH */
706 PCH_LPT, /* Lynxpoint PCH */
707 PCH_NOP,
708 };
709
710 enum intel_sbi_destination {
711 SBI_ICLK,
712 SBI_MPHY,
713 };
714
715 #define QUIRK_PIPEA_FORCE (1<<0)
716 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
717 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
718 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
719 #define QUIRK_PIPEB_FORCE (1<<4)
720
721 struct intel_fbdev;
722 struct intel_fbc_work;
723
724 struct intel_gmbus {
725 struct i2c_adapter adapter;
726 u32 force_bit;
727 u32 reg0;
728 u32 gpio_reg;
729 struct i2c_algo_bit_data bit_algo;
730 struct drm_i915_private *dev_priv;
731 };
732
733 struct i915_suspend_saved_registers {
734 u8 saveLBB;
735 u32 saveDSPACNTR;
736 u32 saveDSPBCNTR;
737 u32 saveDSPARB;
738 u32 savePIPEACONF;
739 u32 savePIPEBCONF;
740 u32 savePIPEASRC;
741 u32 savePIPEBSRC;
742 u32 saveFPA0;
743 u32 saveFPA1;
744 u32 saveDPLL_A;
745 u32 saveDPLL_A_MD;
746 u32 saveHTOTAL_A;
747 u32 saveHBLANK_A;
748 u32 saveHSYNC_A;
749 u32 saveVTOTAL_A;
750 u32 saveVBLANK_A;
751 u32 saveVSYNC_A;
752 u32 saveBCLRPAT_A;
753 u32 saveTRANSACONF;
754 u32 saveTRANS_HTOTAL_A;
755 u32 saveTRANS_HBLANK_A;
756 u32 saveTRANS_HSYNC_A;
757 u32 saveTRANS_VTOTAL_A;
758 u32 saveTRANS_VBLANK_A;
759 u32 saveTRANS_VSYNC_A;
760 u32 savePIPEASTAT;
761 u32 saveDSPASTRIDE;
762 u32 saveDSPASIZE;
763 u32 saveDSPAPOS;
764 u32 saveDSPAADDR;
765 u32 saveDSPASURF;
766 u32 saveDSPATILEOFF;
767 u32 savePFIT_PGM_RATIOS;
768 u32 saveBLC_HIST_CTL;
769 u32 saveBLC_PWM_CTL;
770 u32 saveBLC_PWM_CTL2;
771 u32 saveBLC_HIST_CTL_B;
772 u32 saveBLC_CPU_PWM_CTL;
773 u32 saveBLC_CPU_PWM_CTL2;
774 u32 saveFPB0;
775 u32 saveFPB1;
776 u32 saveDPLL_B;
777 u32 saveDPLL_B_MD;
778 u32 saveHTOTAL_B;
779 u32 saveHBLANK_B;
780 u32 saveHSYNC_B;
781 u32 saveVTOTAL_B;
782 u32 saveVBLANK_B;
783 u32 saveVSYNC_B;
784 u32 saveBCLRPAT_B;
785 u32 saveTRANSBCONF;
786 u32 saveTRANS_HTOTAL_B;
787 u32 saveTRANS_HBLANK_B;
788 u32 saveTRANS_HSYNC_B;
789 u32 saveTRANS_VTOTAL_B;
790 u32 saveTRANS_VBLANK_B;
791 u32 saveTRANS_VSYNC_B;
792 u32 savePIPEBSTAT;
793 u32 saveDSPBSTRIDE;
794 u32 saveDSPBSIZE;
795 u32 saveDSPBPOS;
796 u32 saveDSPBADDR;
797 u32 saveDSPBSURF;
798 u32 saveDSPBTILEOFF;
799 u32 saveVGA0;
800 u32 saveVGA1;
801 u32 saveVGA_PD;
802 u32 saveVGACNTRL;
803 u32 saveADPA;
804 u32 saveLVDS;
805 u32 savePP_ON_DELAYS;
806 u32 savePP_OFF_DELAYS;
807 u32 saveDVOA;
808 u32 saveDVOB;
809 u32 saveDVOC;
810 u32 savePP_ON;
811 u32 savePP_OFF;
812 u32 savePP_CONTROL;
813 u32 savePP_DIVISOR;
814 u32 savePFIT_CONTROL;
815 u32 save_palette_a[256];
816 u32 save_palette_b[256];
817 u32 saveFBC_CONTROL;
818 u32 saveIER;
819 u32 saveIIR;
820 u32 saveIMR;
821 u32 saveDEIER;
822 u32 saveDEIMR;
823 u32 saveGTIER;
824 u32 saveGTIMR;
825 u32 saveFDI_RXA_IMR;
826 u32 saveFDI_RXB_IMR;
827 u32 saveCACHE_MODE_0;
828 u32 saveMI_ARB_STATE;
829 u32 saveSWF0[16];
830 u32 saveSWF1[16];
831 u32 saveSWF2[3];
832 u8 saveMSR;
833 u8 saveSR[8];
834 u8 saveGR[25];
835 u8 saveAR_INDEX;
836 u8 saveAR[21];
837 u8 saveDACMASK;
838 u8 saveCR[37];
839 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
840 u32 saveCURACNTR;
841 u32 saveCURAPOS;
842 u32 saveCURABASE;
843 u32 saveCURBCNTR;
844 u32 saveCURBPOS;
845 u32 saveCURBBASE;
846 u32 saveCURSIZE;
847 u32 saveDP_B;
848 u32 saveDP_C;
849 u32 saveDP_D;
850 u32 savePIPEA_GMCH_DATA_M;
851 u32 savePIPEB_GMCH_DATA_M;
852 u32 savePIPEA_GMCH_DATA_N;
853 u32 savePIPEB_GMCH_DATA_N;
854 u32 savePIPEA_DP_LINK_M;
855 u32 savePIPEB_DP_LINK_M;
856 u32 savePIPEA_DP_LINK_N;
857 u32 savePIPEB_DP_LINK_N;
858 u32 saveFDI_RXA_CTL;
859 u32 saveFDI_TXA_CTL;
860 u32 saveFDI_RXB_CTL;
861 u32 saveFDI_TXB_CTL;
862 u32 savePFA_CTL_1;
863 u32 savePFB_CTL_1;
864 u32 savePFA_WIN_SZ;
865 u32 savePFB_WIN_SZ;
866 u32 savePFA_WIN_POS;
867 u32 savePFB_WIN_POS;
868 u32 savePCH_DREF_CONTROL;
869 u32 saveDISP_ARB_CTL;
870 u32 savePIPEA_DATA_M1;
871 u32 savePIPEA_DATA_N1;
872 u32 savePIPEA_LINK_M1;
873 u32 savePIPEA_LINK_N1;
874 u32 savePIPEB_DATA_M1;
875 u32 savePIPEB_DATA_N1;
876 u32 savePIPEB_LINK_M1;
877 u32 savePIPEB_LINK_N1;
878 u32 saveMCHBAR_RENDER_STANDBY;
879 u32 savePCH_PORT_HOTPLUG;
880 u16 saveGCDGMBUS;
881 };
882
883 struct vlv_s0ix_state {
884 /* GAM */
885 u32 wr_watermark;
886 u32 gfx_prio_ctrl;
887 u32 arb_mode;
888 u32 gfx_pend_tlb0;
889 u32 gfx_pend_tlb1;
890 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
891 u32 media_max_req_count;
892 u32 gfx_max_req_count;
893 u32 render_hwsp;
894 u32 ecochk;
895 u32 bsd_hwsp;
896 u32 blt_hwsp;
897 u32 tlb_rd_addr;
898
899 /* MBC */
900 u32 g3dctl;
901 u32 gsckgctl;
902 u32 mbctl;
903
904 /* GCP */
905 u32 ucgctl1;
906 u32 ucgctl3;
907 u32 rcgctl1;
908 u32 rcgctl2;
909 u32 rstctl;
910 u32 misccpctl;
911
912 /* GPM */
913 u32 gfxpause;
914 u32 rpdeuhwtc;
915 u32 rpdeuc;
916 u32 ecobus;
917 u32 pwrdwnupctl;
918 u32 rp_down_timeout;
919 u32 rp_deucsw;
920 u32 rcubmabdtmr;
921 u32 rcedata;
922 u32 spare2gh;
923
924 /* Display 1 CZ domain */
925 u32 gt_imr;
926 u32 gt_ier;
927 u32 pm_imr;
928 u32 pm_ier;
929 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
930
931 /* GT SA CZ domain */
932 u32 tilectl;
933 u32 gt_fifoctl;
934 u32 gtlc_wake_ctrl;
935 u32 gtlc_survive;
936 u32 pmwgicz;
937
938 /* Display 2 CZ domain */
939 u32 gu_ctl0;
940 u32 gu_ctl1;
941 u32 pcbr;
942 u32 clock_gate_dis2;
943 };
944
945 struct intel_rps_ei {
946 u32 cz_clock;
947 u32 render_c0;
948 u32 media_c0;
949 };
950
951 struct intel_gen6_power_mgmt {
952 /* work and pm_iir are protected by dev_priv->irq_lock */
953 struct work_struct work;
954 u32 pm_iir;
955
956 /* Frequencies are stored in potentially platform dependent multiples.
957 * In other words, *_freq needs to be multiplied by X to be interesting.
958 * Soft limits are those which are used for the dynamic reclocking done
959 * by the driver (raise frequencies under heavy loads, and lower for
960 * lighter loads). Hard limits are those imposed by the hardware.
961 *
962 * A distinction is made for overclocking, which is never enabled by
963 * default, and is considered to be above the hard limit if it's
964 * possible at all.
965 */
966 u8 cur_freq; /* Current frequency (cached, may not == HW) */
967 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
968 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
969 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
970 u8 min_freq; /* AKA RPn. Minimum frequency */
971 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
972 u8 rp1_freq; /* "less than" RP0 power/freqency */
973 u8 rp0_freq; /* Non-overclocked max frequency. */
974 u32 cz_freq;
975
976 u32 ei_interrupt_count;
977
978 int last_adj;
979 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
980
981 bool enabled;
982 struct delayed_work delayed_resume_work;
983
984 /* manual wa residency calculations */
985 struct intel_rps_ei up_ei, down_ei;
986
987 /*
988 * Protects RPS/RC6 register access and PCU communication.
989 * Must be taken after struct_mutex if nested.
990 */
991 struct mutex hw_lock;
992 };
993
994 /* defined intel_pm.c */
995 extern spinlock_t mchdev_lock;
996
997 struct intel_ilk_power_mgmt {
998 u8 cur_delay;
999 u8 min_delay;
1000 u8 max_delay;
1001 u8 fmax;
1002 u8 fstart;
1003
1004 u64 last_count1;
1005 unsigned long last_time1;
1006 unsigned long chipset_power;
1007 u64 last_count2;
1008 u64 last_time2;
1009 unsigned long gfx_power;
1010 u8 corr;
1011
1012 int c_m;
1013 int r_t;
1014
1015 struct drm_i915_gem_object *pwrctx;
1016 struct drm_i915_gem_object *renderctx;
1017 };
1018
1019 struct drm_i915_private;
1020 struct i915_power_well;
1021
1022 struct i915_power_well_ops {
1023 /*
1024 * Synchronize the well's hw state to match the current sw state, for
1025 * example enable/disable it based on the current refcount. Called
1026 * during driver init and resume time, possibly after first calling
1027 * the enable/disable handlers.
1028 */
1029 void (*sync_hw)(struct drm_i915_private *dev_priv,
1030 struct i915_power_well *power_well);
1031 /*
1032 * Enable the well and resources that depend on it (for example
1033 * interrupts located on the well). Called after the 0->1 refcount
1034 * transition.
1035 */
1036 void (*enable)(struct drm_i915_private *dev_priv,
1037 struct i915_power_well *power_well);
1038 /*
1039 * Disable the well and resources that depend on it. Called after
1040 * the 1->0 refcount transition.
1041 */
1042 void (*disable)(struct drm_i915_private *dev_priv,
1043 struct i915_power_well *power_well);
1044 /* Returns the hw enabled state. */
1045 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1046 struct i915_power_well *power_well);
1047 };
1048
1049 /* Power well structure for haswell */
1050 struct i915_power_well {
1051 const char *name;
1052 bool always_on;
1053 /* power well enable/disable usage count */
1054 int count;
1055 /* cached hw enabled state */
1056 bool hw_enabled;
1057 unsigned long domains;
1058 unsigned long data;
1059 const struct i915_power_well_ops *ops;
1060 };
1061
1062 struct i915_power_domains {
1063 /*
1064 * Power wells needed for initialization at driver init and suspend
1065 * time are on. They are kept on until after the first modeset.
1066 */
1067 bool init_power_on;
1068 bool initializing;
1069 int power_well_count;
1070
1071 struct mutex lock;
1072 int domain_use_count[POWER_DOMAIN_NUM];
1073 struct i915_power_well *power_wells;
1074 };
1075
1076 struct i915_dri1_state {
1077 unsigned allow_batchbuffer : 1;
1078 u32 __iomem *gfx_hws_cpu_addr;
1079
1080 unsigned int cpp;
1081 int back_offset;
1082 int front_offset;
1083 int current_page;
1084 int page_flipping;
1085
1086 uint32_t counter;
1087 };
1088
1089 struct i915_ums_state {
1090 /**
1091 * Flag if the X Server, and thus DRM, is not currently in
1092 * control of the device.
1093 *
1094 * This is set between LeaveVT and EnterVT. It needs to be
1095 * replaced with a semaphore. It also needs to be
1096 * transitioned away from for kernel modesetting.
1097 */
1098 int mm_suspended;
1099 };
1100
1101 #define MAX_L3_SLICES 2
1102 struct intel_l3_parity {
1103 u32 *remap_info[MAX_L3_SLICES];
1104 struct work_struct error_work;
1105 int which_slice;
1106 };
1107
1108 struct i915_gem_mm {
1109 /** Memory allocator for GTT stolen memory */
1110 struct drm_mm stolen;
1111 /** List of all objects in gtt_space. Used to restore gtt
1112 * mappings on resume */
1113 struct list_head bound_list;
1114 /**
1115 * List of objects which are not bound to the GTT (thus
1116 * are idle and not used by the GPU) but still have
1117 * (presumably uncached) pages still attached.
1118 */
1119 struct list_head unbound_list;
1120
1121 /** Usable portion of the GTT for GEM */
1122 unsigned long stolen_base; /* limited to low memory (32-bit) */
1123
1124 /** PPGTT used for aliasing the PPGTT with the GTT */
1125 struct i915_hw_ppgtt *aliasing_ppgtt;
1126
1127 struct notifier_block oom_notifier;
1128 struct shrinker shrinker;
1129 bool shrinker_no_lock_stealing;
1130
1131 /** LRU list of objects with fence regs on them. */
1132 struct list_head fence_list;
1133
1134 /**
1135 * We leave the user IRQ off as much as possible,
1136 * but this means that requests will finish and never
1137 * be retired once the system goes idle. Set a timer to
1138 * fire periodically while the ring is running. When it
1139 * fires, go retire requests.
1140 */
1141 struct delayed_work retire_work;
1142
1143 /**
1144 * When we detect an idle GPU, we want to turn on
1145 * powersaving features. So once we see that there
1146 * are no more requests outstanding and no more
1147 * arrive within a small period of time, we fire
1148 * off the idle_work.
1149 */
1150 struct delayed_work idle_work;
1151
1152 /**
1153 * Are we in a non-interruptible section of code like
1154 * modesetting?
1155 */
1156 bool interruptible;
1157
1158 /**
1159 * Is the GPU currently considered idle, or busy executing userspace
1160 * requests? Whilst idle, we attempt to power down the hardware and
1161 * display clocks. In order to reduce the effect on performance, there
1162 * is a slight delay before we do so.
1163 */
1164 bool busy;
1165
1166 /* the indicator for dispatch video commands on two BSD rings */
1167 int bsd_ring_dispatch_index;
1168
1169 /** Bit 6 swizzling required for X tiling */
1170 uint32_t bit_6_swizzle_x;
1171 /** Bit 6 swizzling required for Y tiling */
1172 uint32_t bit_6_swizzle_y;
1173
1174 /* accounting, useful for userland debugging */
1175 spinlock_t object_stat_lock;
1176 size_t object_memory;
1177 u32 object_count;
1178 };
1179
1180 struct drm_i915_error_state_buf {
1181 struct drm_i915_private *i915;
1182 unsigned bytes;
1183 unsigned size;
1184 int err;
1185 u8 *buf;
1186 loff_t start;
1187 loff_t pos;
1188 };
1189
1190 struct i915_error_state_file_priv {
1191 struct drm_device *dev;
1192 struct drm_i915_error_state *error;
1193 };
1194
1195 struct i915_gpu_error {
1196 /* For hangcheck timer */
1197 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1198 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1199 /* Hang gpu twice in this window and your context gets banned */
1200 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1201
1202 struct timer_list hangcheck_timer;
1203
1204 /* For reset and error_state handling. */
1205 spinlock_t lock;
1206 /* Protected by the above dev->gpu_error.lock. */
1207 struct drm_i915_error_state *first_error;
1208 struct work_struct work;
1209
1210
1211 unsigned long missed_irq_rings;
1212
1213 /**
1214 * State variable controlling the reset flow and count
1215 *
1216 * This is a counter which gets incremented when reset is triggered,
1217 * and again when reset has been handled. So odd values (lowest bit set)
1218 * means that reset is in progress and even values that
1219 * (reset_counter >> 1):th reset was successfully completed.
1220 *
1221 * If reset is not completed succesfully, the I915_WEDGE bit is
1222 * set meaning that hardware is terminally sour and there is no
1223 * recovery. All waiters on the reset_queue will be woken when
1224 * that happens.
1225 *
1226 * This counter is used by the wait_seqno code to notice that reset
1227 * event happened and it needs to restart the entire ioctl (since most
1228 * likely the seqno it waited for won't ever signal anytime soon).
1229 *
1230 * This is important for lock-free wait paths, where no contended lock
1231 * naturally enforces the correct ordering between the bail-out of the
1232 * waiter and the gpu reset work code.
1233 */
1234 atomic_t reset_counter;
1235
1236 #define I915_RESET_IN_PROGRESS_FLAG 1
1237 #define I915_WEDGED (1 << 31)
1238
1239 /**
1240 * Waitqueue to signal when the reset has completed. Used by clients
1241 * that wait for dev_priv->mm.wedged to settle.
1242 */
1243 wait_queue_head_t reset_queue;
1244
1245 /* Userspace knobs for gpu hang simulation;
1246 * combines both a ring mask, and extra flags
1247 */
1248 u32 stop_rings;
1249 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1250 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1251
1252 /* For missed irq/seqno simulation. */
1253 unsigned int test_irq_rings;
1254
1255 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1256 bool reload_in_reset;
1257 };
1258
1259 enum modeset_restore {
1260 MODESET_ON_LID_OPEN,
1261 MODESET_DONE,
1262 MODESET_SUSPENDED,
1263 };
1264
1265 struct ddi_vbt_port_info {
1266 /*
1267 * This is an index in the HDMI/DVI DDI buffer translation table.
1268 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1269 * populate this field.
1270 */
1271 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1272 uint8_t hdmi_level_shift;
1273
1274 uint8_t supports_dvi:1;
1275 uint8_t supports_hdmi:1;
1276 uint8_t supports_dp:1;
1277 };
1278
1279 enum drrs_support_type {
1280 DRRS_NOT_SUPPORTED = 0,
1281 STATIC_DRRS_SUPPORT = 1,
1282 SEAMLESS_DRRS_SUPPORT = 2
1283 };
1284
1285 struct intel_vbt_data {
1286 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1287 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1288
1289 /* Feature bits */
1290 unsigned int int_tv_support:1;
1291 unsigned int lvds_dither:1;
1292 unsigned int lvds_vbt:1;
1293 unsigned int int_crt_support:1;
1294 unsigned int lvds_use_ssc:1;
1295 unsigned int display_clock_mode:1;
1296 unsigned int fdi_rx_polarity_inverted:1;
1297 unsigned int has_mipi:1;
1298 int lvds_ssc_freq;
1299 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1300
1301 enum drrs_support_type drrs_type;
1302
1303 /* eDP */
1304 int edp_rate;
1305 int edp_lanes;
1306 int edp_preemphasis;
1307 int edp_vswing;
1308 bool edp_initialized;
1309 bool edp_support;
1310 int edp_bpp;
1311 struct edp_power_seq edp_pps;
1312
1313 struct {
1314 u16 pwm_freq_hz;
1315 bool present;
1316 bool active_low_pwm;
1317 u8 min_brightness; /* min_brightness/255 of max */
1318 } backlight;
1319
1320 /* MIPI DSI */
1321 struct {
1322 u16 port;
1323 u16 panel_id;
1324 struct mipi_config *config;
1325 struct mipi_pps_data *pps;
1326 u8 seq_version;
1327 u32 size;
1328 u8 *data;
1329 u8 *sequence[MIPI_SEQ_MAX];
1330 } dsi;
1331
1332 int crt_ddc_pin;
1333
1334 int child_dev_num;
1335 union child_device_config *child_dev;
1336
1337 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1338 };
1339
1340 enum intel_ddb_partitioning {
1341 INTEL_DDB_PART_1_2,
1342 INTEL_DDB_PART_5_6, /* IVB+ */
1343 };
1344
1345 struct intel_wm_level {
1346 bool enable;
1347 uint32_t pri_val;
1348 uint32_t spr_val;
1349 uint32_t cur_val;
1350 uint32_t fbc_val;
1351 };
1352
1353 struct ilk_wm_values {
1354 uint32_t wm_pipe[3];
1355 uint32_t wm_lp[3];
1356 uint32_t wm_lp_spr[3];
1357 uint32_t wm_linetime[3];
1358 bool enable_fbc_wm;
1359 enum intel_ddb_partitioning partitioning;
1360 };
1361
1362 /*
1363 * This struct helps tracking the state needed for runtime PM, which puts the
1364 * device in PCI D3 state. Notice that when this happens, nothing on the
1365 * graphics device works, even register access, so we don't get interrupts nor
1366 * anything else.
1367 *
1368 * Every piece of our code that needs to actually touch the hardware needs to
1369 * either call intel_runtime_pm_get or call intel_display_power_get with the
1370 * appropriate power domain.
1371 *
1372 * Our driver uses the autosuspend delay feature, which means we'll only really
1373 * suspend if we stay with zero refcount for a certain amount of time. The
1374 * default value is currently very conservative (see intel_init_runtime_pm), but
1375 * it can be changed with the standard runtime PM files from sysfs.
1376 *
1377 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1378 * goes back to false exactly before we reenable the IRQs. We use this variable
1379 * to check if someone is trying to enable/disable IRQs while they're supposed
1380 * to be disabled. This shouldn't happen and we'll print some error messages in
1381 * case it happens.
1382 *
1383 * For more, read the Documentation/power/runtime_pm.txt.
1384 */
1385 struct i915_runtime_pm {
1386 bool suspended;
1387 bool _irqs_disabled;
1388 };
1389
1390 enum intel_pipe_crc_source {
1391 INTEL_PIPE_CRC_SOURCE_NONE,
1392 INTEL_PIPE_CRC_SOURCE_PLANE1,
1393 INTEL_PIPE_CRC_SOURCE_PLANE2,
1394 INTEL_PIPE_CRC_SOURCE_PF,
1395 INTEL_PIPE_CRC_SOURCE_PIPE,
1396 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1397 INTEL_PIPE_CRC_SOURCE_TV,
1398 INTEL_PIPE_CRC_SOURCE_DP_B,
1399 INTEL_PIPE_CRC_SOURCE_DP_C,
1400 INTEL_PIPE_CRC_SOURCE_DP_D,
1401 INTEL_PIPE_CRC_SOURCE_AUTO,
1402 INTEL_PIPE_CRC_SOURCE_MAX,
1403 };
1404
1405 struct intel_pipe_crc_entry {
1406 uint32_t frame;
1407 uint32_t crc[5];
1408 };
1409
1410 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1411 struct intel_pipe_crc {
1412 spinlock_t lock;
1413 bool opened; /* exclusive access to the result file */
1414 struct intel_pipe_crc_entry *entries;
1415 enum intel_pipe_crc_source source;
1416 int head, tail;
1417 wait_queue_head_t wq;
1418 };
1419
1420 struct i915_frontbuffer_tracking {
1421 struct mutex lock;
1422
1423 /*
1424 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1425 * scheduled flips.
1426 */
1427 unsigned busy_bits;
1428 unsigned flip_bits;
1429 };
1430
1431 struct drm_i915_private {
1432 struct drm_device *dev;
1433 struct kmem_cache *slab;
1434
1435 const struct intel_device_info info;
1436
1437 int relative_constants_mode;
1438
1439 void __iomem *regs;
1440
1441 struct intel_uncore uncore;
1442
1443 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1444
1445
1446 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1447 * controller on different i2c buses. */
1448 struct mutex gmbus_mutex;
1449
1450 /**
1451 * Base address of the gmbus and gpio block.
1452 */
1453 uint32_t gpio_mmio_base;
1454
1455 /* MMIO base address for MIPI regs */
1456 uint32_t mipi_mmio_base;
1457
1458 wait_queue_head_t gmbus_wait_queue;
1459
1460 struct pci_dev *bridge_dev;
1461 struct intel_engine_cs ring[I915_NUM_RINGS];
1462 struct drm_i915_gem_object *semaphore_obj;
1463 uint32_t last_seqno, next_seqno;
1464
1465 struct drm_dma_handle *status_page_dmah;
1466 struct resource mch_res;
1467
1468 /* protects the irq masks */
1469 spinlock_t irq_lock;
1470
1471 /* protects the mmio flip data */
1472 spinlock_t mmio_flip_lock;
1473
1474 bool display_irqs_enabled;
1475
1476 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1477 struct pm_qos_request pm_qos;
1478
1479 /* DPIO indirect register protection */
1480 struct mutex dpio_lock;
1481
1482 /** Cached value of IMR to avoid reads in updating the bitfield */
1483 union {
1484 u32 irq_mask;
1485 u32 de_irq_mask[I915_MAX_PIPES];
1486 };
1487 u32 gt_irq_mask;
1488 u32 pm_irq_mask;
1489 u32 pm_rps_events;
1490 u32 pipestat_irq_mask[I915_MAX_PIPES];
1491
1492 struct work_struct hotplug_work;
1493 struct {
1494 unsigned long hpd_last_jiffies;
1495 int hpd_cnt;
1496 enum {
1497 HPD_ENABLED = 0,
1498 HPD_DISABLED = 1,
1499 HPD_MARK_DISABLED = 2
1500 } hpd_mark;
1501 } hpd_stats[HPD_NUM_PINS];
1502 u32 hpd_event_bits;
1503 struct delayed_work hotplug_reenable_work;
1504
1505 struct i915_fbc fbc;
1506 struct i915_drrs drrs;
1507 struct intel_opregion opregion;
1508 struct intel_vbt_data vbt;
1509
1510 /* overlay */
1511 struct intel_overlay *overlay;
1512
1513 /* backlight registers and fields in struct intel_panel */
1514 spinlock_t backlight_lock;
1515
1516 /* LVDS info */
1517 bool no_aux_handshake;
1518
1519 /* protects panel power sequencer state */
1520 struct mutex pps_mutex;
1521
1522 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1523 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1524 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1525
1526 unsigned int fsb_freq, mem_freq, is_ddr3;
1527 unsigned int vlv_cdclk_freq;
1528
1529 /**
1530 * wq - Driver workqueue for GEM.
1531 *
1532 * NOTE: Work items scheduled here are not allowed to grab any modeset
1533 * locks, for otherwise the flushing done in the pageflip code will
1534 * result in deadlocks.
1535 */
1536 struct workqueue_struct *wq;
1537
1538 /* Display functions */
1539 struct drm_i915_display_funcs display;
1540
1541 /* PCH chipset type */
1542 enum intel_pch pch_type;
1543 unsigned short pch_id;
1544
1545 unsigned long quirks;
1546
1547 enum modeset_restore modeset_restore;
1548 struct mutex modeset_restore_lock;
1549
1550 struct list_head vm_list; /* Global list of all address spaces */
1551 struct i915_gtt gtt; /* VM representing the global address space */
1552
1553 struct i915_gem_mm mm;
1554 DECLARE_HASHTABLE(mm_structs, 7);
1555 struct mutex mm_lock;
1556
1557 /* Kernel Modesetting */
1558
1559 struct sdvo_device_mapping sdvo_mappings[2];
1560
1561 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1562 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1563 wait_queue_head_t pending_flip_queue;
1564
1565 #ifdef CONFIG_DEBUG_FS
1566 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1567 #endif
1568
1569 int num_shared_dpll;
1570 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1571 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1572
1573 /*
1574 * workarounds are currently applied at different places and
1575 * changes are being done to consolidate them so exact count is
1576 * not clear at this point, use a max value for now.
1577 */
1578 #define I915_MAX_WA_REGS 16
1579 struct {
1580 u32 addr;
1581 u32 value;
1582 /* bitmask representing WA bits */
1583 u32 mask;
1584 } intel_wa_regs[I915_MAX_WA_REGS];
1585 u32 num_wa_regs;
1586
1587 /* Reclocking support */
1588 bool render_reclock_avail;
1589 bool lvds_downclock_avail;
1590 /* indicates the reduced downclock for LVDS*/
1591 int lvds_downclock;
1592
1593 struct i915_frontbuffer_tracking fb_tracking;
1594
1595 u16 orig_clock;
1596
1597 bool mchbar_need_disable;
1598
1599 struct intel_l3_parity l3_parity;
1600
1601 /* Cannot be determined by PCIID. You must always read a register. */
1602 size_t ellc_size;
1603
1604 /* gen6+ rps state */
1605 struct intel_gen6_power_mgmt rps;
1606
1607 /* ilk-only ips/rps state. Everything in here is protected by the global
1608 * mchdev_lock in intel_pm.c */
1609 struct intel_ilk_power_mgmt ips;
1610
1611 struct i915_power_domains power_domains;
1612
1613 struct i915_psr psr;
1614
1615 struct i915_gpu_error gpu_error;
1616
1617 struct drm_i915_gem_object *vlv_pctx;
1618
1619 #ifdef CONFIG_DRM_I915_FBDEV
1620 /* list of fbdev register on this device */
1621 struct intel_fbdev *fbdev;
1622 struct work_struct fbdev_suspend_work;
1623 #endif
1624
1625 struct drm_property *broadcast_rgb_property;
1626 struct drm_property *force_audio_property;
1627
1628 uint32_t hw_context_size;
1629 struct list_head context_list;
1630
1631 u32 fdi_rx_config;
1632
1633 u32 suspend_count;
1634 struct i915_suspend_saved_registers regfile;
1635 struct vlv_s0ix_state vlv_s0ix_state;
1636
1637 struct {
1638 /*
1639 * Raw watermark latency values:
1640 * in 0.1us units for WM0,
1641 * in 0.5us units for WM1+.
1642 */
1643 /* primary */
1644 uint16_t pri_latency[5];
1645 /* sprite */
1646 uint16_t spr_latency[5];
1647 /* cursor */
1648 uint16_t cur_latency[5];
1649
1650 /* current hardware state */
1651 struct ilk_wm_values hw;
1652 } wm;
1653
1654 struct i915_runtime_pm pm;
1655
1656 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1657 u32 long_hpd_port_mask;
1658 u32 short_hpd_port_mask;
1659 struct work_struct dig_port_work;
1660
1661 /*
1662 * if we get a HPD irq from DP and a HPD irq from non-DP
1663 * the non-DP HPD could block the workqueue on a mode config
1664 * mutex getting, that userspace may have taken. However
1665 * userspace is waiting on the DP workqueue to run which is
1666 * blocked behind the non-DP one.
1667 */
1668 struct workqueue_struct *dp_wq;
1669
1670 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1671 * here! */
1672 struct i915_dri1_state dri1;
1673 /* Old ums support infrastructure, same warning applies. */
1674 struct i915_ums_state ums;
1675
1676 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1677 struct {
1678 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1679 struct intel_engine_cs *ring,
1680 struct intel_context *ctx,
1681 struct drm_i915_gem_execbuffer2 *args,
1682 struct list_head *vmas,
1683 struct drm_i915_gem_object *batch_obj,
1684 u64 exec_start, u32 flags);
1685 int (*init_rings)(struct drm_device *dev);
1686 void (*cleanup_ring)(struct intel_engine_cs *ring);
1687 void (*stop_ring)(struct intel_engine_cs *ring);
1688 } gt;
1689
1690 /*
1691 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1692 * will be rejected. Instead look for a better place.
1693 */
1694 };
1695
to_i915(const struct drm_device * dev)1696 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1697 {
1698 return dev->dev_private;
1699 }
1700
1701 /* Iterate over initialised rings */
1702 #define for_each_ring(ring__, dev_priv__, i__) \
1703 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1704 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1705
1706 enum hdmi_force_audio {
1707 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1708 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1709 HDMI_AUDIO_AUTO, /* trust EDID */
1710 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1711 };
1712
1713 #define I915_GTT_OFFSET_NONE ((u32)-1)
1714
1715 struct drm_i915_gem_object_ops {
1716 /* Interface between the GEM object and its backing storage.
1717 * get_pages() is called once prior to the use of the associated set
1718 * of pages before to binding them into the GTT, and put_pages() is
1719 * called after we no longer need them. As we expect there to be
1720 * associated cost with migrating pages between the backing storage
1721 * and making them available for the GPU (e.g. clflush), we may hold
1722 * onto the pages after they are no longer referenced by the GPU
1723 * in case they may be used again shortly (for example migrating the
1724 * pages to a different memory domain within the GTT). put_pages()
1725 * will therefore most likely be called when the object itself is
1726 * being released or under memory pressure (where we attempt to
1727 * reap pages for the shrinker).
1728 */
1729 int (*get_pages)(struct drm_i915_gem_object *);
1730 void (*put_pages)(struct drm_i915_gem_object *);
1731 int (*dmabuf_export)(struct drm_i915_gem_object *);
1732 void (*release)(struct drm_i915_gem_object *);
1733 };
1734
1735 /*
1736 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1737 * considered to be the frontbuffer for the given plane interface-vise. This
1738 * doesn't mean that the hw necessarily already scans it out, but that any
1739 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1740 *
1741 * We have one bit per pipe and per scanout plane type.
1742 */
1743 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1744 #define INTEL_FRONTBUFFER_BITS \
1745 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1746 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1747 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1748 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1749 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1750 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1751 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1752 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1753 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1754 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1755 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1756
1757 struct drm_i915_gem_object {
1758 struct drm_gem_object base;
1759
1760 const struct drm_i915_gem_object_ops *ops;
1761
1762 /** List of VMAs backed by this object */
1763 struct list_head vma_list;
1764
1765 /** Stolen memory for this object, instead of being backed by shmem. */
1766 struct drm_mm_node *stolen;
1767 struct list_head global_list;
1768
1769 struct list_head ring_list;
1770 /** Used in execbuf to temporarily hold a ref */
1771 struct list_head obj_exec_link;
1772
1773 /**
1774 * This is set if the object is on the active lists (has pending
1775 * rendering and so a non-zero seqno), and is not set if it i s on
1776 * inactive (ready to be unbound) list.
1777 */
1778 unsigned int active:1;
1779
1780 /**
1781 * This is set if the object has been written to since last bound
1782 * to the GTT
1783 */
1784 unsigned int dirty:1;
1785
1786 /**
1787 * Fence register bits (if any) for this object. Will be set
1788 * as needed when mapped into the GTT.
1789 * Protected by dev->struct_mutex.
1790 */
1791 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1792
1793 /**
1794 * Advice: are the backing pages purgeable?
1795 */
1796 unsigned int madv:2;
1797
1798 /**
1799 * Current tiling mode for the object.
1800 */
1801 unsigned int tiling_mode:2;
1802 /**
1803 * Whether the tiling parameters for the currently associated fence
1804 * register have changed. Note that for the purposes of tracking
1805 * tiling changes we also treat the unfenced register, the register
1806 * slot that the object occupies whilst it executes a fenced
1807 * command (such as BLT on gen2/3), as a "fence".
1808 */
1809 unsigned int fence_dirty:1;
1810
1811 /**
1812 * Is the object at the current location in the gtt mappable and
1813 * fenceable? Used to avoid costly recalculations.
1814 */
1815 unsigned int map_and_fenceable:1;
1816
1817 /**
1818 * Whether the current gtt mapping needs to be mappable (and isn't just
1819 * mappable by accident). Track pin and fault separate for a more
1820 * accurate mappable working set.
1821 */
1822 unsigned int fault_mappable:1;
1823 unsigned int pin_mappable:1;
1824 unsigned int pin_display:1;
1825
1826 /*
1827 * Is the object to be mapped as read-only to the GPU
1828 * Only honoured if hardware has relevant pte bit
1829 */
1830 unsigned long gt_ro:1;
1831 unsigned int cache_level:3;
1832
1833 unsigned int has_aliasing_ppgtt_mapping:1;
1834 unsigned int has_global_gtt_mapping:1;
1835 unsigned int has_dma_mapping:1;
1836
1837 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1838
1839 struct sg_table *pages;
1840 int pages_pin_count;
1841
1842 /* prime dma-buf support */
1843 void *dma_buf_vmapping;
1844 int vmapping_count;
1845
1846 struct intel_engine_cs *ring;
1847
1848 /** Breadcrumb of last rendering to the buffer. */
1849 uint32_t last_read_seqno;
1850 uint32_t last_write_seqno;
1851 /** Breadcrumb of last fenced GPU access to the buffer. */
1852 uint32_t last_fenced_seqno;
1853
1854 /** Current tiling stride for the object, if it's tiled. */
1855 uint32_t stride;
1856
1857 /** References from framebuffers, locks out tiling changes. */
1858 unsigned long framebuffer_references;
1859
1860 /** Record of address bit 17 of each page at last unbind. */
1861 unsigned long *bit_17;
1862
1863 /** User space pin count and filp owning the pin */
1864 unsigned long user_pin_count;
1865 struct drm_file *pin_filp;
1866
1867 /** for phy allocated objects */
1868 struct drm_dma_handle *phys_handle;
1869
1870 union {
1871 struct i915_gem_userptr {
1872 uintptr_t ptr;
1873 unsigned read_only :1;
1874 unsigned workers :4;
1875 #define I915_GEM_USERPTR_MAX_WORKERS 15
1876
1877 struct i915_mm_struct *mm;
1878 struct i915_mmu_object *mmu_object;
1879 struct work_struct *work;
1880 } userptr;
1881 };
1882 };
1883 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1884
1885 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1886 struct drm_i915_gem_object *new,
1887 unsigned frontbuffer_bits);
1888
1889 /**
1890 * Request queue structure.
1891 *
1892 * The request queue allows us to note sequence numbers that have been emitted
1893 * and may be associated with active buffers to be retired.
1894 *
1895 * By keeping this list, we can avoid having to do questionable
1896 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1897 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1898 */
1899 struct drm_i915_gem_request {
1900 /** On Which ring this request was generated */
1901 struct intel_engine_cs *ring;
1902
1903 /** GEM sequence number associated with this request. */
1904 uint32_t seqno;
1905
1906 /** Position in the ringbuffer of the start of the request */
1907 u32 head;
1908
1909 /** Position in the ringbuffer of the end of the request */
1910 u32 tail;
1911
1912 /** Context related to this request */
1913 struct intel_context *ctx;
1914
1915 /** Batch buffer related to this request if any */
1916 struct drm_i915_gem_object *batch_obj;
1917
1918 /** Time at which this request was emitted, in jiffies. */
1919 unsigned long emitted_jiffies;
1920
1921 /** global list entry for this request */
1922 struct list_head list;
1923
1924 struct drm_i915_file_private *file_priv;
1925 /** file_priv list entry for this request */
1926 struct list_head client_list;
1927 };
1928
1929 struct drm_i915_file_private {
1930 struct drm_i915_private *dev_priv;
1931 struct drm_file *file;
1932
1933 struct {
1934 spinlock_t lock;
1935 struct list_head request_list;
1936 struct delayed_work idle_work;
1937 } mm;
1938 struct idr context_idr;
1939
1940 atomic_t rps_wait_boost;
1941 struct intel_engine_cs *bsd_ring;
1942 };
1943
1944 /*
1945 * A command that requires special handling by the command parser.
1946 */
1947 struct drm_i915_cmd_descriptor {
1948 /*
1949 * Flags describing how the command parser processes the command.
1950 *
1951 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1952 * a length mask if not set
1953 * CMD_DESC_SKIP: The command is allowed but does not follow the
1954 * standard length encoding for the opcode range in
1955 * which it falls
1956 * CMD_DESC_REJECT: The command is never allowed
1957 * CMD_DESC_REGISTER: The command should be checked against the
1958 * register whitelist for the appropriate ring
1959 * CMD_DESC_MASTER: The command is allowed if the submitting process
1960 * is the DRM master
1961 */
1962 u32 flags;
1963 #define CMD_DESC_FIXED (1<<0)
1964 #define CMD_DESC_SKIP (1<<1)
1965 #define CMD_DESC_REJECT (1<<2)
1966 #define CMD_DESC_REGISTER (1<<3)
1967 #define CMD_DESC_BITMASK (1<<4)
1968 #define CMD_DESC_MASTER (1<<5)
1969
1970 /*
1971 * The command's unique identification bits and the bitmask to get them.
1972 * This isn't strictly the opcode field as defined in the spec and may
1973 * also include type, subtype, and/or subop fields.
1974 */
1975 struct {
1976 u32 value;
1977 u32 mask;
1978 } cmd;
1979
1980 /*
1981 * The command's length. The command is either fixed length (i.e. does
1982 * not include a length field) or has a length field mask. The flag
1983 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1984 * a length mask. All command entries in a command table must include
1985 * length information.
1986 */
1987 union {
1988 u32 fixed;
1989 u32 mask;
1990 } length;
1991
1992 /*
1993 * Describes where to find a register address in the command to check
1994 * against the ring's register whitelist. Only valid if flags has the
1995 * CMD_DESC_REGISTER bit set.
1996 */
1997 struct {
1998 u32 offset;
1999 u32 mask;
2000 } reg;
2001
2002 #define MAX_CMD_DESC_BITMASKS 3
2003 /*
2004 * Describes command checks where a particular dword is masked and
2005 * compared against an expected value. If the command does not match
2006 * the expected value, the parser rejects it. Only valid if flags has
2007 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2008 * are valid.
2009 *
2010 * If the check specifies a non-zero condition_mask then the parser
2011 * only performs the check when the bits specified by condition_mask
2012 * are non-zero.
2013 */
2014 struct {
2015 u32 offset;
2016 u32 mask;
2017 u32 expected;
2018 u32 condition_offset;
2019 u32 condition_mask;
2020 } bits[MAX_CMD_DESC_BITMASKS];
2021 };
2022
2023 /*
2024 * A table of commands requiring special handling by the command parser.
2025 *
2026 * Each ring has an array of tables. Each table consists of an array of command
2027 * descriptors, which must be sorted with command opcodes in ascending order.
2028 */
2029 struct drm_i915_cmd_table {
2030 const struct drm_i915_cmd_descriptor *table;
2031 int count;
2032 };
2033
2034 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2035 #define __I915__(p) ({ \
2036 struct drm_i915_private *__p; \
2037 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2038 __p = (struct drm_i915_private *)p; \
2039 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2040 __p = to_i915((struct drm_device *)p); \
2041 else \
2042 BUILD_BUG(); \
2043 __p; \
2044 })
2045 #define INTEL_INFO(p) (&__I915__(p)->info)
2046 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2047
2048 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2049 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2050 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2051 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2052 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2053 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2054 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2055 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2056 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2057 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2058 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2059 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2060 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2061 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2062 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2063 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2064 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2065 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2066 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2067 INTEL_DEVID(dev) == 0x0152 || \
2068 INTEL_DEVID(dev) == 0x015a)
2069 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2070 INTEL_DEVID(dev) == 0x0106 || \
2071 INTEL_DEVID(dev) == 0x010A)
2072 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2073 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2074 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2075 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2076 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2077 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2078 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2079 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2080 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2081 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2082 (INTEL_DEVID(dev) & 0xf) == 0xe))
2083 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2084 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2085 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
2086 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2087 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2088 /* ULX machines are also considered ULT. */
2089 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2090 INTEL_DEVID(dev) == 0x0A1E)
2091 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2092
2093 /*
2094 * The genX designation typically refers to the render engine, so render
2095 * capability related checks should use IS_GEN, while display and other checks
2096 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2097 * chips, etc.).
2098 */
2099 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2100 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2101 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2102 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2103 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2104 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2105 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2106
2107 #define RENDER_RING (1<<RCS)
2108 #define BSD_RING (1<<VCS)
2109 #define BLT_RING (1<<BCS)
2110 #define VEBOX_RING (1<<VECS)
2111 #define BSD2_RING (1<<VCS2)
2112 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2113 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2114 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2115 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2116 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2117 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2118 to_i915(dev)->ellc_size)
2119 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2120
2121 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2122 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2123 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2124 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2125 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2126 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2127
2128 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2129 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2130
2131 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2132 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2133 /*
2134 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2135 * even when in MSI mode. This results in spurious interrupt warnings if the
2136 * legacy irq no. is shared with another device. The kernel then disables that
2137 * interrupt source and so prevents the other device from working properly.
2138 */
2139 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2140 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2141
2142 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2143 * rows, which changed the alignment requirements and fence programming.
2144 */
2145 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2146 IS_I915GM(dev)))
2147 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2148 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2149 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2150 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2151 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2152
2153 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2154 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2155 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2156
2157 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2158
2159 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2160 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2161 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2162 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2163 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2164
2165 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2166 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2167 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2168 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2169 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2170 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2171
2172 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2173 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2174 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2175 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2176 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2177 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2178
2179 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2180
2181 /* DPF == dynamic parity feature */
2182 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2183 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2184
2185 #define GT_FREQUENCY_MULTIPLIER 50
2186
2187 #include "i915_trace.h"
2188
2189 extern const struct drm_ioctl_desc i915_ioctls[];
2190 extern int i915_max_ioctl;
2191
2192 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2193 extern int i915_resume(struct drm_device *dev);
2194 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2195 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2196
2197 /* i915_params.c */
2198 struct i915_params {
2199 int modeset;
2200 int panel_ignore_lid;
2201 unsigned int powersave;
2202 int semaphores;
2203 unsigned int lvds_downclock;
2204 int lvds_channel_mode;
2205 int panel_use_ssc;
2206 int vbt_sdvo_panel_type;
2207 int enable_rc6;
2208 int enable_fbc;
2209 int enable_ppgtt;
2210 int enable_execlists;
2211 int enable_psr;
2212 unsigned int preliminary_hw_support;
2213 int disable_power_well;
2214 int enable_ips;
2215 int invert_brightness;
2216 int enable_cmd_parser;
2217 /* leave bools at the end to not create holes */
2218 bool enable_hangcheck;
2219 bool fastboot;
2220 bool prefault_disable;
2221 bool reset;
2222 bool disable_display;
2223 bool disable_vtd_wa;
2224 int use_mmio_flip;
2225 bool mmio_debug;
2226 };
2227 extern struct i915_params i915 __read_mostly;
2228
2229 /* i915_dma.c */
2230 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2231 extern void i915_kernel_lost_context(struct drm_device * dev);
2232 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2233 extern int i915_driver_unload(struct drm_device *);
2234 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2235 extern void i915_driver_lastclose(struct drm_device * dev);
2236 extern void i915_driver_preclose(struct drm_device *dev,
2237 struct drm_file *file);
2238 extern void i915_driver_postclose(struct drm_device *dev,
2239 struct drm_file *file);
2240 extern int i915_driver_device_is_agp(struct drm_device * dev);
2241 #ifdef CONFIG_COMPAT
2242 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2243 unsigned long arg);
2244 #endif
2245 extern int i915_emit_box(struct drm_device *dev,
2246 struct drm_clip_rect *box,
2247 int DR1, int DR4);
2248 extern int intel_gpu_reset(struct drm_device *dev);
2249 extern int i915_reset(struct drm_device *dev);
2250 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2251 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2252 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2253 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2254 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2255 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2256
2257 /* i915_irq.c */
2258 void i915_queue_hangcheck(struct drm_device *dev);
2259 __printf(3, 4)
2260 void i915_handle_error(struct drm_device *dev, bool wedged,
2261 const char *fmt, ...);
2262
2263 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2264 int new_delay);
2265 extern void intel_irq_init(struct drm_device *dev);
2266 extern void intel_hpd_init(struct drm_device *dev);
2267
2268 extern void intel_uncore_sanitize(struct drm_device *dev);
2269 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2270 bool restore_forcewake);
2271 extern void intel_uncore_init(struct drm_device *dev);
2272 extern void intel_uncore_check_errors(struct drm_device *dev);
2273 extern void intel_uncore_fini(struct drm_device *dev);
2274 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2275
2276 void
2277 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2278 u32 status_mask);
2279
2280 void
2281 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2282 u32 status_mask);
2283
2284 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2285 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2286
2287 /* i915_gem.c */
2288 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2289 struct drm_file *file_priv);
2290 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2291 struct drm_file *file_priv);
2292 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2293 struct drm_file *file_priv);
2294 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2295 struct drm_file *file_priv);
2296 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2297 struct drm_file *file_priv);
2298 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2299 struct drm_file *file_priv);
2300 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2301 struct drm_file *file_priv);
2302 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2303 struct drm_file *file_priv);
2304 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2305 struct intel_engine_cs *ring);
2306 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2307 struct drm_file *file,
2308 struct intel_engine_cs *ring,
2309 struct drm_i915_gem_object *obj);
2310 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2311 struct drm_file *file,
2312 struct intel_engine_cs *ring,
2313 struct intel_context *ctx,
2314 struct drm_i915_gem_execbuffer2 *args,
2315 struct list_head *vmas,
2316 struct drm_i915_gem_object *batch_obj,
2317 u64 exec_start, u32 flags);
2318 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2319 struct drm_file *file_priv);
2320 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2321 struct drm_file *file_priv);
2322 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2323 struct drm_file *file_priv);
2324 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2325 struct drm_file *file_priv);
2326 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2327 struct drm_file *file_priv);
2328 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2329 struct drm_file *file);
2330 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2331 struct drm_file *file);
2332 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2333 struct drm_file *file_priv);
2334 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2335 struct drm_file *file_priv);
2336 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2337 struct drm_file *file_priv);
2338 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2339 struct drm_file *file_priv);
2340 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2341 struct drm_file *file_priv);
2342 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2343 struct drm_file *file_priv);
2344 int i915_gem_init_userptr(struct drm_device *dev);
2345 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2346 struct drm_file *file);
2347 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2348 struct drm_file *file_priv);
2349 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2350 struct drm_file *file_priv);
2351 void i915_gem_load(struct drm_device *dev);
2352 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2353 long target,
2354 unsigned flags);
2355 #define I915_SHRINK_PURGEABLE 0x1
2356 #define I915_SHRINK_UNBOUND 0x2
2357 #define I915_SHRINK_BOUND 0x4
2358 void *i915_gem_object_alloc(struct drm_device *dev);
2359 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2360 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2361 const struct drm_i915_gem_object_ops *ops);
2362 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2363 size_t size);
2364 void i915_init_vm(struct drm_i915_private *dev_priv,
2365 struct i915_address_space *vm);
2366 void i915_gem_free_object(struct drm_gem_object *obj);
2367 void i915_gem_vma_destroy(struct i915_vma *vma);
2368
2369 #define PIN_MAPPABLE 0x1
2370 #define PIN_NONBLOCK 0x2
2371 #define PIN_GLOBAL 0x4
2372 #define PIN_OFFSET_BIAS 0x8
2373 #define PIN_OFFSET_MASK (~4095)
2374 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2375 struct i915_address_space *vm,
2376 uint32_t alignment,
2377 uint64_t flags);
2378 int __must_check i915_vma_unbind(struct i915_vma *vma);
2379 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2380 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2381 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2382 void i915_gem_lastclose(struct drm_device *dev);
2383
2384 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2385 int *needs_clflush);
2386
2387 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
i915_gem_object_get_page(struct drm_i915_gem_object * obj,int n)2388 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2389 {
2390 struct sg_page_iter sg_iter;
2391
2392 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2393 return sg_page_iter_page(&sg_iter);
2394
2395 return NULL;
2396 }
i915_gem_object_pin_pages(struct drm_i915_gem_object * obj)2397 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2398 {
2399 BUG_ON(obj->pages == NULL);
2400 obj->pages_pin_count++;
2401 }
i915_gem_object_unpin_pages(struct drm_i915_gem_object * obj)2402 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2403 {
2404 BUG_ON(obj->pages_pin_count == 0);
2405 obj->pages_pin_count--;
2406 }
2407
2408 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2409 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2410 struct intel_engine_cs *to);
2411 void i915_vma_move_to_active(struct i915_vma *vma,
2412 struct intel_engine_cs *ring);
2413 int i915_gem_dumb_create(struct drm_file *file_priv,
2414 struct drm_device *dev,
2415 struct drm_mode_create_dumb *args);
2416 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2417 uint32_t handle, uint64_t *offset);
2418 /**
2419 * Returns true if seq1 is later than seq2.
2420 */
2421 static inline bool
i915_seqno_passed(uint32_t seq1,uint32_t seq2)2422 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2423 {
2424 return (int32_t)(seq1 - seq2) >= 0;
2425 }
2426
2427 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2428 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2429 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2430 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2431
2432 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2433 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2434
2435 struct drm_i915_gem_request *
2436 i915_gem_find_active_request(struct intel_engine_cs *ring);
2437
2438 bool i915_gem_retire_requests(struct drm_device *dev);
2439 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2440 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2441 bool interruptible);
2442 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2443
i915_reset_in_progress(struct i915_gpu_error * error)2444 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2445 {
2446 return unlikely(atomic_read(&error->reset_counter)
2447 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2448 }
2449
i915_terminally_wedged(struct i915_gpu_error * error)2450 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2451 {
2452 return atomic_read(&error->reset_counter) & I915_WEDGED;
2453 }
2454
i915_reset_count(struct i915_gpu_error * error)2455 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2456 {
2457 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2458 }
2459
i915_stop_ring_allow_ban(struct drm_i915_private * dev_priv)2460 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2461 {
2462 return dev_priv->gpu_error.stop_rings == 0 ||
2463 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2464 }
2465
i915_stop_ring_allow_warn(struct drm_i915_private * dev_priv)2466 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2467 {
2468 return dev_priv->gpu_error.stop_rings == 0 ||
2469 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2470 }
2471
2472 void i915_gem_reset(struct drm_device *dev);
2473 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2474 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2475 int __must_check i915_gem_init(struct drm_device *dev);
2476 int i915_gem_init_rings(struct drm_device *dev);
2477 int __must_check i915_gem_init_hw(struct drm_device *dev);
2478 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2479 void i915_gem_init_swizzling(struct drm_device *dev);
2480 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2481 int __must_check i915_gpu_idle(struct drm_device *dev);
2482 int __must_check i915_gem_suspend(struct drm_device *dev);
2483 int __i915_add_request(struct intel_engine_cs *ring,
2484 struct drm_file *file,
2485 struct drm_i915_gem_object *batch_obj,
2486 u32 *seqno);
2487 #define i915_add_request(ring, seqno) \
2488 __i915_add_request(ring, NULL, NULL, seqno)
2489 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2490 uint32_t seqno);
2491 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2492 int __must_check
2493 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2494 bool write);
2495 int __must_check
2496 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2497 int __must_check
2498 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2499 u32 alignment,
2500 struct intel_engine_cs *pipelined);
2501 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2502 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2503 int align);
2504 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2505 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2506
2507 uint32_t
2508 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2509 uint32_t
2510 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2511 int tiling_mode, bool fenced);
2512
2513 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2514 enum i915_cache_level cache_level);
2515
2516 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2517 struct dma_buf *dma_buf);
2518
2519 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2520 struct drm_gem_object *gem_obj, int flags);
2521
2522 void i915_gem_restore_fences(struct drm_device *dev);
2523
2524 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2525 struct i915_address_space *vm);
2526 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2527 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2528 struct i915_address_space *vm);
2529 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2530 struct i915_address_space *vm);
2531 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2532 struct i915_address_space *vm);
2533 struct i915_vma *
2534 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2535 struct i915_address_space *vm);
2536
2537 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
i915_gem_obj_is_pinned(struct drm_i915_gem_object * obj)2538 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2539 struct i915_vma *vma;
2540 list_for_each_entry(vma, &obj->vma_list, vma_link)
2541 if (vma->pin_count > 0)
2542 return true;
2543 return false;
2544 }
2545
2546 /* Some GGTT VM helpers */
2547 #define i915_obj_to_ggtt(obj) \
2548 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
i915_is_ggtt(struct i915_address_space * vm)2549 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2550 {
2551 struct i915_address_space *ggtt =
2552 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2553 return vm == ggtt;
2554 }
2555
2556 static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space * vm)2557 i915_vm_to_ppgtt(struct i915_address_space *vm)
2558 {
2559 WARN_ON(i915_is_ggtt(vm));
2560
2561 return container_of(vm, struct i915_hw_ppgtt, base);
2562 }
2563
2564
i915_gem_obj_ggtt_bound(struct drm_i915_gem_object * obj)2565 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2566 {
2567 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2568 }
2569
2570 static inline unsigned long
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object * obj)2571 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2572 {
2573 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2574 }
2575
2576 static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object * obj)2577 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2578 {
2579 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2580 }
2581
2582 static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object * obj,uint32_t alignment,unsigned flags)2583 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2584 uint32_t alignment,
2585 unsigned flags)
2586 {
2587 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2588 alignment, flags | PIN_GLOBAL);
2589 }
2590
2591 static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object * obj)2592 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2593 {
2594 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2595 }
2596
2597 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2598
2599 /* i915_gem_context.c */
2600 int __must_check i915_gem_context_init(struct drm_device *dev);
2601 void i915_gem_context_fini(struct drm_device *dev);
2602 void i915_gem_context_reset(struct drm_device *dev);
2603 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2604 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2605 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2606 int i915_switch_context(struct intel_engine_cs *ring,
2607 struct intel_context *to);
2608 struct intel_context *
2609 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2610 void i915_gem_context_free(struct kref *ctx_ref);
2611 struct drm_i915_gem_object *
2612 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
i915_gem_context_reference(struct intel_context * ctx)2613 static inline void i915_gem_context_reference(struct intel_context *ctx)
2614 {
2615 kref_get(&ctx->ref);
2616 }
2617
i915_gem_context_unreference(struct intel_context * ctx)2618 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2619 {
2620 kref_put(&ctx->ref, i915_gem_context_free);
2621 }
2622
i915_gem_context_is_default(const struct intel_context * c)2623 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2624 {
2625 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2626 }
2627
2628 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2629 struct drm_file *file);
2630 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2631 struct drm_file *file);
2632
2633 /* i915_gem_evict.c */
2634 int __must_check i915_gem_evict_something(struct drm_device *dev,
2635 struct i915_address_space *vm,
2636 int min_size,
2637 unsigned alignment,
2638 unsigned cache_level,
2639 unsigned long start,
2640 unsigned long end,
2641 unsigned flags);
2642 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2643 int i915_gem_evict_everything(struct drm_device *dev);
2644
2645 /* belongs in i915_gem_gtt.h */
i915_gem_chipset_flush(struct drm_device * dev)2646 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2647 {
2648 if (INTEL_INFO(dev)->gen < 6)
2649 intel_gtt_chipset_flush();
2650 }
2651
2652 /* i915_gem_stolen.c */
2653 int i915_gem_init_stolen(struct drm_device *dev);
2654 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2655 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2656 void i915_gem_cleanup_stolen(struct drm_device *dev);
2657 struct drm_i915_gem_object *
2658 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2659 struct drm_i915_gem_object *
2660 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2661 u32 stolen_offset,
2662 u32 gtt_offset,
2663 u32 size);
2664
2665 /* i915_gem_tiling.c */
i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object * obj)2666 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2667 {
2668 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2669
2670 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2671 obj->tiling_mode != I915_TILING_NONE;
2672 }
2673
2674 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2675 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2676 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2677
2678 /* i915_gem_debug.c */
2679 #if WATCH_LISTS
2680 int i915_verify_lists(struct drm_device *dev);
2681 #else
2682 #define i915_verify_lists(dev) 0
2683 #endif
2684
2685 /* i915_debugfs.c */
2686 int i915_debugfs_init(struct drm_minor *minor);
2687 void i915_debugfs_cleanup(struct drm_minor *minor);
2688 #ifdef CONFIG_DEBUG_FS
2689 void intel_display_crc_init(struct drm_device *dev);
2690 #else
intel_display_crc_init(struct drm_device * dev)2691 static inline void intel_display_crc_init(struct drm_device *dev) {}
2692 #endif
2693
2694 /* i915_gpu_error.c */
2695 __printf(2, 3)
2696 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2697 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2698 const struct i915_error_state_file_priv *error);
2699 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2700 struct drm_i915_private *i915,
2701 size_t count, loff_t pos);
i915_error_state_buf_release(struct drm_i915_error_state_buf * eb)2702 static inline void i915_error_state_buf_release(
2703 struct drm_i915_error_state_buf *eb)
2704 {
2705 kfree(eb->buf);
2706 }
2707 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2708 const char *error_msg);
2709 void i915_error_state_get(struct drm_device *dev,
2710 struct i915_error_state_file_priv *error_priv);
2711 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2712 void i915_destroy_error_state(struct drm_device *dev);
2713
2714 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2715 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2716
2717 /* i915_cmd_parser.c */
2718 int i915_cmd_parser_get_version(void);
2719 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2720 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2721 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2722 int i915_parse_cmds(struct intel_engine_cs *ring,
2723 struct drm_i915_gem_object *batch_obj,
2724 u32 batch_start_offset,
2725 bool is_master);
2726
2727 /* i915_suspend.c */
2728 extern int i915_save_state(struct drm_device *dev);
2729 extern int i915_restore_state(struct drm_device *dev);
2730
2731 /* i915_ums.c */
2732 void i915_save_display_reg(struct drm_device *dev);
2733 void i915_restore_display_reg(struct drm_device *dev);
2734
2735 /* i915_sysfs.c */
2736 void i915_setup_sysfs(struct drm_device *dev_priv);
2737 void i915_teardown_sysfs(struct drm_device *dev_priv);
2738
2739 /* intel_i2c.c */
2740 extern int intel_setup_gmbus(struct drm_device *dev);
2741 extern void intel_teardown_gmbus(struct drm_device *dev);
intel_gmbus_is_port_valid(unsigned port)2742 static inline bool intel_gmbus_is_port_valid(unsigned port)
2743 {
2744 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2745 }
2746
2747 extern struct i2c_adapter *intel_gmbus_get_adapter(
2748 struct drm_i915_private *dev_priv, unsigned port);
2749 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2750 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)2751 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2752 {
2753 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2754 }
2755 extern void intel_i2c_reset(struct drm_device *dev);
2756
2757 /* intel_opregion.c */
2758 struct intel_encoder;
2759 #ifdef CONFIG_ACPI
2760 extern int intel_opregion_setup(struct drm_device *dev);
2761 extern void intel_opregion_init(struct drm_device *dev);
2762 extern void intel_opregion_fini(struct drm_device *dev);
2763 extern void intel_opregion_asle_intr(struct drm_device *dev);
2764 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2765 bool enable);
2766 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2767 pci_power_t state);
2768 #else
intel_opregion_setup(struct drm_device * dev)2769 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
intel_opregion_init(struct drm_device * dev)2770 static inline void intel_opregion_init(struct drm_device *dev) { return; }
intel_opregion_fini(struct drm_device * dev)2771 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
intel_opregion_asle_intr(struct drm_device * dev)2772 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2773 static inline int
intel_opregion_notify_encoder(struct intel_encoder * intel_encoder,bool enable)2774 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2775 {
2776 return 0;
2777 }
2778 static inline int
intel_opregion_notify_adapter(struct drm_device * dev,pci_power_t state)2779 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2780 {
2781 return 0;
2782 }
2783 #endif
2784
2785 /* intel_acpi.c */
2786 #ifdef CONFIG_ACPI
2787 extern void intel_register_dsm_handler(void);
2788 extern void intel_unregister_dsm_handler(void);
2789 #else
intel_register_dsm_handler(void)2790 static inline void intel_register_dsm_handler(void) { return; }
intel_unregister_dsm_handler(void)2791 static inline void intel_unregister_dsm_handler(void) { return; }
2792 #endif /* CONFIG_ACPI */
2793
2794 /* modesetting */
2795 extern void intel_modeset_init_hw(struct drm_device *dev);
2796 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2797 extern void intel_modeset_init(struct drm_device *dev);
2798 extern void intel_modeset_gem_init(struct drm_device *dev);
2799 extern void intel_modeset_cleanup(struct drm_device *dev);
2800 extern void intel_connector_unregister(struct intel_connector *);
2801 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2802 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2803 bool force_restore);
2804 extern void i915_redisable_vga(struct drm_device *dev);
2805 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2806 extern bool intel_fbc_enabled(struct drm_device *dev);
2807 extern void gen8_fbc_sw_flush(struct drm_device *dev, u32 value);
2808 extern void intel_disable_fbc(struct drm_device *dev);
2809 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2810 extern void intel_init_pch_refclk(struct drm_device *dev);
2811 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2812 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2813 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2814 bool enable);
2815 extern void intel_detect_pch(struct drm_device *dev);
2816 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2817 extern int intel_enable_rc6(const struct drm_device *dev);
2818
2819 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2820 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2821 struct drm_file *file);
2822 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2823 struct drm_file *file);
2824
2825 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2826
2827 /* overlay */
2828 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2829 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2830 struct intel_overlay_error_state *error);
2831
2832 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2833 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2834 struct drm_device *dev,
2835 struct intel_display_error_state *error);
2836
2837 /* On SNB platform, before reading ring registers forcewake bit
2838 * must be set to prevent GT core from power down and stale values being
2839 * returned.
2840 */
2841 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2842 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2843 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2844
2845 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2846 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2847
2848 /* intel_sideband.c */
2849 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2850 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2851 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2852 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2853 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2854 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2855 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2856 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2857 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2858 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2859 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2860 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2861 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2862 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2863 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2864 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2865 enum intel_sbi_destination destination);
2866 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2867 enum intel_sbi_destination destination);
2868 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2869 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2870
2871 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2872 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2873
2874 #define FORCEWAKE_RENDER (1 << 0)
2875 #define FORCEWAKE_MEDIA (1 << 1)
2876 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2877
2878
2879 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2880 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2881
2882 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2883 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2884 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2885 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2886
2887 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2888 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2889 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2890 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2891
2892 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2893 * will be implemented using 2 32-bit writes in an arbitrary order with
2894 * an arbitrary delay between them. This can cause the hardware to
2895 * act upon the intermediate value, possibly leading to corruption and
2896 * machine death. You have been warned.
2897 */
2898 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2899 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2900
2901 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2902 u32 upper, lower, tmp; \
2903 tmp = I915_READ(upper_reg); \
2904 do { \
2905 upper = tmp; \
2906 lower = I915_READ(lower_reg); \
2907 tmp = I915_READ(upper_reg); \
2908 } while (upper != tmp); \
2909 (u64)upper << 32 | lower; })
2910
2911 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2912 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2913
2914 /* "Broadcast RGB" property */
2915 #define INTEL_BROADCAST_RGB_AUTO 0
2916 #define INTEL_BROADCAST_RGB_FULL 1
2917 #define INTEL_BROADCAST_RGB_LIMITED 2
2918
i915_vgacntrl_reg(struct drm_device * dev)2919 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2920 {
2921 if (IS_VALLEYVIEW(dev))
2922 return VLV_VGACNTRL;
2923 else if (INTEL_INFO(dev)->gen >= 5)
2924 return CPU_VGACNTRL;
2925 else
2926 return VGACNTRL;
2927 }
2928
to_user_ptr(u64 address)2929 static inline void __user *to_user_ptr(u64 address)
2930 {
2931 return (void __user *)(uintptr_t)address;
2932 }
2933
msecs_to_jiffies_timeout(const unsigned int m)2934 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2935 {
2936 unsigned long j = msecs_to_jiffies(m);
2937
2938 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2939 }
2940
2941 static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec * value)2942 timespec_to_jiffies_timeout(const struct timespec *value)
2943 {
2944 unsigned long j = timespec_to_jiffies(value);
2945
2946 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2947 }
2948
2949 /*
2950 * If you need to wait X milliseconds between events A and B, but event B
2951 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2952 * when event A happened, then just before event B you call this function and
2953 * pass the timestamp as the first argument, and X as the second argument.
2954 */
2955 static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies,int to_wait_ms)2956 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2957 {
2958 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2959
2960 /*
2961 * Don't re-read the value of "jiffies" every time since it may change
2962 * behind our back and break the math.
2963 */
2964 tmp_jiffies = jiffies;
2965 target_jiffies = timestamp_jiffies +
2966 msecs_to_jiffies_timeout(to_wait_ms);
2967
2968 if (time_after(target_jiffies, tmp_jiffies)) {
2969 remaining_jiffies = target_jiffies - tmp_jiffies;
2970 while (remaining_jiffies)
2971 remaining_jiffies =
2972 schedule_timeout_uninterruptible(remaining_jiffies);
2973 }
2974 }
2975
2976 #endif
2977