1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
32
33 #include "sdhci.h"
34
35 #define DRIVER_NAME "sdhci"
36
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
43 #endif
44
45 #define MAX_TUNING_LOOP 40
46
47 #define ADMA_SIZE ((128 * 2 + 1) * 4)
48
49 static unsigned int debug_quirks = 0;
50 static unsigned int debug_quirks2;
51
52 static void sdhci_finish_data(struct sdhci_host *);
53
54 static void sdhci_finish_command(struct sdhci_host *);
55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
56 static void sdhci_tuning_timer(unsigned long data);
57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
58
59 #ifdef CONFIG_PM_RUNTIME
60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
64 #else
sdhci_runtime_pm_get(struct sdhci_host * host)65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66 {
67 return 0;
68 }
sdhci_runtime_pm_put(struct sdhci_host * host)69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70 {
71 return 0;
72 }
sdhci_runtime_pm_bus_on(struct sdhci_host * host)73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74 {
75 }
sdhci_runtime_pm_bus_off(struct sdhci_host * host)76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77 {
78 }
79 #endif
80
sdhci_dumpregs(struct sdhci_host * host)81 static void sdhci_dumpregs(struct sdhci_host *host)
82 {
83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
84 mmc_hostname(host->mmc));
85
86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
114 sdhci_readl(host, SDHCI_CAPABILITIES),
115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
117 sdhci_readw(host, SDHCI_COMMAND),
118 sdhci_readl(host, SDHCI_MAX_CURRENT));
119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
121
122 if (host->flags & SDHCI_USE_ADMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
127 pr_debug(DRIVER_NAME ": ===========================================\n");
128 }
129
130 /*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134 \*****************************************************************************/
135
sdhci_set_card_detection(struct sdhci_host * host,bool enable)136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137 {
138 u32 present;
139
140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
142 return;
143
144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
147
148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
156 }
157
sdhci_enable_card_detection(struct sdhci_host * host)158 static void sdhci_enable_card_detection(struct sdhci_host *host)
159 {
160 sdhci_set_card_detection(host, true);
161 }
162
sdhci_disable_card_detection(struct sdhci_host * host)163 static void sdhci_disable_card_detection(struct sdhci_host *host)
164 {
165 sdhci_set_card_detection(host, false);
166 }
167
sdhci_reset(struct sdhci_host * host,u8 mask)168 void sdhci_reset(struct sdhci_host *host, u8 mask)
169 {
170 unsigned long timeout;
171
172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
173
174 if (mask & SDHCI_RESET_ALL) {
175 host->clock = 0;
176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
180
181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
186 if (timeout == 0) {
187 pr_err("%s: Reset 0x%x never completed.\n",
188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
194 }
195 }
196 EXPORT_SYMBOL_GPL(sdhci_reset);
197
sdhci_do_reset(struct sdhci_host * host,u8 mask)198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199 {
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
205
206 host->ops->reset(host, mask);
207
208 if (mask & SDHCI_RESET_ALL) {
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if (host->ops->enable_dma)
211 host->ops->enable_dma(host);
212 }
213
214 /* Resetting the controller clears many */
215 host->preset_enabled = false;
216 }
217 }
218
219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220
sdhci_init(struct sdhci_host * host,int soft)221 static void sdhci_init(struct sdhci_host *host, int soft)
222 {
223 if (soft)
224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
225 else
226 sdhci_do_reset(host, SDHCI_RESET_ALL);
227
228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
232 SDHCI_INT_RESPONSE;
233
234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
236
237 if (soft) {
238 /* force clock reconfiguration */
239 host->clock = 0;
240 sdhci_set_ios(host->mmc, &host->mmc->ios);
241 }
242 }
243
sdhci_reinit(struct sdhci_host * host)244 static void sdhci_reinit(struct sdhci_host *host)
245 {
246 sdhci_init(host, 0);
247 /*
248 * Retuning stuffs are affected by different cards inserted and only
249 * applicable to UHS-I cards. So reset these fields to their initial
250 * value when card is removed.
251 */
252 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
254
255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
259 }
260 sdhci_enable_card_detection(host);
261 }
262
sdhci_activate_led(struct sdhci_host * host)263 static void sdhci_activate_led(struct sdhci_host *host)
264 {
265 u8 ctrl;
266
267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
268 ctrl |= SDHCI_CTRL_LED;
269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
270 }
271
sdhci_deactivate_led(struct sdhci_host * host)272 static void sdhci_deactivate_led(struct sdhci_host *host)
273 {
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl &= ~SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279 }
280
281 #ifdef SDHCI_USE_LEDS_CLASS
sdhci_led_control(struct led_classdev * led,enum led_brightness brightness)282 static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
284 {
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
286 unsigned long flags;
287
288 spin_lock_irqsave(&host->lock, flags);
289
290 if (host->runtime_suspended)
291 goto out;
292
293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
295 else
296 sdhci_activate_led(host);
297 out:
298 spin_unlock_irqrestore(&host->lock, flags);
299 }
300 #endif
301
302 /*****************************************************************************\
303 * *
304 * Core functions *
305 * *
306 \*****************************************************************************/
307
sdhci_read_block_pio(struct sdhci_host * host)308 static void sdhci_read_block_pio(struct sdhci_host *host)
309 {
310 unsigned long flags;
311 size_t blksize, len, chunk;
312 u32 uninitialized_var(scratch);
313 u8 *buf;
314
315 DBG("PIO reading\n");
316
317 blksize = host->data->blksz;
318 chunk = 0;
319
320 local_irq_save(flags);
321
322 while (blksize) {
323 if (!sg_miter_next(&host->sg_miter))
324 BUG();
325
326 len = min(host->sg_miter.length, blksize);
327
328 blksize -= len;
329 host->sg_miter.consumed = len;
330
331 buf = host->sg_miter.addr;
332
333 while (len) {
334 if (chunk == 0) {
335 scratch = sdhci_readl(host, SDHCI_BUFFER);
336 chunk = 4;
337 }
338
339 *buf = scratch & 0xFF;
340
341 buf++;
342 scratch >>= 8;
343 chunk--;
344 len--;
345 }
346 }
347
348 sg_miter_stop(&host->sg_miter);
349
350 local_irq_restore(flags);
351 }
352
sdhci_write_block_pio(struct sdhci_host * host)353 static void sdhci_write_block_pio(struct sdhci_host *host)
354 {
355 unsigned long flags;
356 size_t blksize, len, chunk;
357 u32 scratch;
358 u8 *buf;
359
360 DBG("PIO writing\n");
361
362 blksize = host->data->blksz;
363 chunk = 0;
364 scratch = 0;
365
366 local_irq_save(flags);
367
368 while (blksize) {
369 if (!sg_miter_next(&host->sg_miter))
370 BUG();
371
372 len = min(host->sg_miter.length, blksize);
373
374 blksize -= len;
375 host->sg_miter.consumed = len;
376
377 buf = host->sg_miter.addr;
378
379 while (len) {
380 scratch |= (u32)*buf << (chunk * 8);
381
382 buf++;
383 chunk++;
384 len--;
385
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
387 sdhci_writel(host, scratch, SDHCI_BUFFER);
388 chunk = 0;
389 scratch = 0;
390 }
391 }
392 }
393
394 sg_miter_stop(&host->sg_miter);
395
396 local_irq_restore(flags);
397 }
398
sdhci_transfer_pio(struct sdhci_host * host)399 static void sdhci_transfer_pio(struct sdhci_host *host)
400 {
401 u32 mask;
402
403 BUG_ON(!host->data);
404
405 if (host->blocks == 0)
406 return;
407
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
410 else
411 mask = SDHCI_SPACE_AVAILABLE;
412
413 /*
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
417 */
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
420 mask = ~0;
421
422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
424 udelay(100);
425
426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
428 else
429 sdhci_write_block_pio(host);
430
431 host->blocks--;
432 if (host->blocks == 0)
433 break;
434 }
435
436 DBG("PIO transfer complete.\n");
437 }
438
sdhci_kmap_atomic(struct scatterlist * sg,unsigned long * flags)439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
440 {
441 local_irq_save(*flags);
442 return kmap_atomic(sg_page(sg)) + sg->offset;
443 }
444
sdhci_kunmap_atomic(void * buffer,unsigned long * flags)445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446 {
447 kunmap_atomic(buffer);
448 local_irq_restore(*flags);
449 }
450
sdhci_set_adma_desc(u8 * desc,u32 addr,int len,unsigned cmd)451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
452 {
453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
455
456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
458
459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
461
462 dataddr[0] = cpu_to_le32(addr);
463 }
464
sdhci_adma_table_pre(struct sdhci_host * host,struct mmc_data * data)465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
467 {
468 int direction;
469
470 u8 *desc;
471 u8 *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, 128 * 4, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494 goto fail;
495 BUG_ON(host->align_addr & 0x3);
496
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
499 if (host->sg_count == 0)
500 goto unmap_align;
501
502 desc = host->adma_desc;
503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
518 offset = (4 - (addr & 0x3)) & 0x3;
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
527 /* tran, valid */
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
529
530 BUG_ON(offset > 65536);
531
532 align += 4;
533 align_addr += 4;
534
535 desc += 8;
536
537 addr += offset;
538 len -= offset;
539 }
540
541 BUG_ON(len > 65536);
542
543 /* tran, valid */
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
545 desc += 8;
546
547 /*
548 * If this triggers then we have a calculation bug
549 * somewhere. :/
550 */
551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
552 }
553
554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555 /*
556 * Mark the last descriptor as the terminating descriptor
557 */
558 if (desc != host->adma_desc) {
559 desc -= 8;
560 desc[0] |= 0x2; /* end */
561 }
562 } else {
563 /*
564 * Add a terminating entry.
565 */
566
567 /* nop, end, valid */
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
569 }
570
571 /*
572 * Resync align buffer as we might have changed it.
573 */
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, 128 * 4, direction);
577 }
578
579 return 0;
580
581 unmap_align:
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584 fail:
585 return -EINVAL;
586 }
587
sdhci_adma_table_post(struct sdhci_host * host,struct mmc_data * data)588 static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
590 {
591 int direction;
592
593 struct scatterlist *sg;
594 int i, size;
595 u8 *align;
596 char *buffer;
597 unsigned long flags;
598 bool has_unaligned;
599
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
602 else
603 direction = DMA_TO_DEVICE;
604
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 128 * 4, direction);
607
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & 3) {
612 has_unaligned = true;
613 break;
614 }
615
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
619
620 align = host->align_buffer;
621
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
625
626 buffer = sdhci_kmap_atomic(sg, &flags);
627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
630
631 align += 4;
632 }
633 }
634 }
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
638 }
639
sdhci_calc_timeout(struct sdhci_host * host,struct mmc_command * cmd)640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
641 {
642 u8 count;
643 struct mmc_data *data = cmd->data;
644 unsigned target_timeout, current_timeout;
645
646 /*
647 * If the host controller provides us with an incorrect timeout
648 * value, just skip the check and use 0xE. The hardware may take
649 * longer to time out, but that's much better than having a too-short
650 * timeout value.
651 */
652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
653 return 0xE;
654
655 /* Unspecified timeout, assume max */
656 if (!data && !cmd->busy_timeout)
657 return 0xE;
658
659 /* timeout in us */
660 if (!data)
661 target_timeout = cmd->busy_timeout * 1000;
662 else {
663 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
664 if (host->clock && data->timeout_clks) {
665 unsigned long long val;
666
667 /*
668 * data->timeout_clks is in units of clock cycles.
669 * host->clock is in Hz. target_timeout is in us.
670 * Hence, us = 1000000 * cycles / Hz. Round up.
671 */
672 val = 1000000ULL * data->timeout_clks;
673 if (do_div(val, host->clock))
674 target_timeout++;
675 target_timeout += val;
676 }
677 }
678
679 /*
680 * Figure out needed cycles.
681 * We do this in steps in order to fit inside a 32 bit int.
682 * The first step is the minimum timeout, which will have a
683 * minimum resolution of 6 bits:
684 * (1) 2^13*1000 > 2^22,
685 * (2) host->timeout_clk < 2^16
686 * =>
687 * (1) / (2) > 2^6
688 */
689 count = 0;
690 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
691 while (current_timeout < target_timeout) {
692 count++;
693 current_timeout <<= 1;
694 if (count >= 0xF)
695 break;
696 }
697
698 if (count >= 0xF) {
699 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
700 mmc_hostname(host->mmc), count, cmd->opcode);
701 count = 0xE;
702 }
703
704 return count;
705 }
706
sdhci_set_transfer_irqs(struct sdhci_host * host)707 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708 {
709 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
710 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711
712 if (host->flags & SDHCI_REQ_USE_DMA)
713 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
714 else
715 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
716
717 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
718 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
719 }
720
sdhci_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)721 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
722 {
723 u8 count;
724
725 if (host->ops->set_timeout) {
726 host->ops->set_timeout(host, cmd);
727 } else {
728 count = sdhci_calc_timeout(host, cmd);
729 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
730 }
731 }
732
sdhci_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)733 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
734 {
735 u8 ctrl;
736 struct mmc_data *data = cmd->data;
737 int ret;
738
739 WARN_ON(host->data);
740
741 if (data || (cmd->flags & MMC_RSP_BUSY))
742 sdhci_set_timeout(host, cmd);
743
744 if (!data)
745 return;
746
747 /* Sanity checks */
748 BUG_ON(data->blksz * data->blocks > 524288);
749 BUG_ON(data->blksz > host->mmc->max_blk_size);
750 BUG_ON(data->blocks > 65535);
751
752 host->data = data;
753 host->data_early = 0;
754 host->data->bytes_xfered = 0;
755
756 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
757 host->flags |= SDHCI_REQ_USE_DMA;
758
759 /*
760 * FIXME: This doesn't account for merging when mapping the
761 * scatterlist.
762 */
763 if (host->flags & SDHCI_REQ_USE_DMA) {
764 int broken, i;
765 struct scatterlist *sg;
766
767 broken = 0;
768 if (host->flags & SDHCI_USE_ADMA) {
769 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
770 broken = 1;
771 } else {
772 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
773 broken = 1;
774 }
775
776 if (unlikely(broken)) {
777 for_each_sg(data->sg, sg, data->sg_len, i) {
778 if (sg->length & 0x3) {
779 DBG("Reverting to PIO because of "
780 "transfer size (%d)\n",
781 sg->length);
782 host->flags &= ~SDHCI_REQ_USE_DMA;
783 break;
784 }
785 }
786 }
787 }
788
789 /*
790 * The assumption here being that alignment is the same after
791 * translation to device address space.
792 */
793 if (host->flags & SDHCI_REQ_USE_DMA) {
794 int broken, i;
795 struct scatterlist *sg;
796
797 broken = 0;
798 if (host->flags & SDHCI_USE_ADMA) {
799 /*
800 * As we use 3 byte chunks to work around
801 * alignment problems, we need to check this
802 * quirk.
803 */
804 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
805 broken = 1;
806 } else {
807 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
808 broken = 1;
809 }
810
811 if (unlikely(broken)) {
812 for_each_sg(data->sg, sg, data->sg_len, i) {
813 if (sg->offset & 0x3) {
814 DBG("Reverting to PIO because of "
815 "bad alignment\n");
816 host->flags &= ~SDHCI_REQ_USE_DMA;
817 break;
818 }
819 }
820 }
821 }
822
823 if (host->flags & SDHCI_REQ_USE_DMA) {
824 if (host->flags & SDHCI_USE_ADMA) {
825 ret = sdhci_adma_table_pre(host, data);
826 if (ret) {
827 /*
828 * This only happens when someone fed
829 * us an invalid request.
830 */
831 WARN_ON(1);
832 host->flags &= ~SDHCI_REQ_USE_DMA;
833 } else {
834 sdhci_writel(host, host->adma_addr,
835 SDHCI_ADMA_ADDRESS);
836 }
837 } else {
838 int sg_cnt;
839
840 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
841 data->sg, data->sg_len,
842 (data->flags & MMC_DATA_READ) ?
843 DMA_FROM_DEVICE :
844 DMA_TO_DEVICE);
845 if (sg_cnt == 0) {
846 /*
847 * This only happens when someone fed
848 * us an invalid request.
849 */
850 WARN_ON(1);
851 host->flags &= ~SDHCI_REQ_USE_DMA;
852 } else {
853 WARN_ON(sg_cnt != 1);
854 sdhci_writel(host, sg_dma_address(data->sg),
855 SDHCI_DMA_ADDRESS);
856 }
857 }
858 }
859
860 /*
861 * Always adjust the DMA selection as some controllers
862 * (e.g. JMicron) can't do PIO properly when the selection
863 * is ADMA.
864 */
865 if (host->version >= SDHCI_SPEC_200) {
866 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
867 ctrl &= ~SDHCI_CTRL_DMA_MASK;
868 if ((host->flags & SDHCI_REQ_USE_DMA) &&
869 (host->flags & SDHCI_USE_ADMA))
870 ctrl |= SDHCI_CTRL_ADMA32;
871 else
872 ctrl |= SDHCI_CTRL_SDMA;
873 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
874 }
875
876 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
877 int flags;
878
879 flags = SG_MITER_ATOMIC;
880 if (host->data->flags & MMC_DATA_READ)
881 flags |= SG_MITER_TO_SG;
882 else
883 flags |= SG_MITER_FROM_SG;
884 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
885 host->blocks = data->blocks;
886 }
887
888 sdhci_set_transfer_irqs(host);
889
890 /* Set the DMA boundary value and block size */
891 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
892 data->blksz), SDHCI_BLOCK_SIZE);
893 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
894 }
895
sdhci_set_transfer_mode(struct sdhci_host * host,struct mmc_command * cmd)896 static void sdhci_set_transfer_mode(struct sdhci_host *host,
897 struct mmc_command *cmd)
898 {
899 u16 mode;
900 struct mmc_data *data = cmd->data;
901
902 if (data == NULL) {
903 /* clear Auto CMD settings for no data CMDs */
904 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
905 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
906 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
907 return;
908 }
909
910 WARN_ON(!host->data);
911
912 mode = SDHCI_TRNS_BLK_CNT_EN;
913 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
914 mode |= SDHCI_TRNS_MULTI;
915 /*
916 * If we are sending CMD23, CMD12 never gets sent
917 * on successful completion (so no Auto-CMD12).
918 */
919 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
920 mode |= SDHCI_TRNS_AUTO_CMD12;
921 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
922 mode |= SDHCI_TRNS_AUTO_CMD23;
923 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
924 }
925 }
926
927 if (data->flags & MMC_DATA_READ)
928 mode |= SDHCI_TRNS_READ;
929 if (host->flags & SDHCI_REQ_USE_DMA)
930 mode |= SDHCI_TRNS_DMA;
931
932 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
933 }
934
sdhci_finish_data(struct sdhci_host * host)935 static void sdhci_finish_data(struct sdhci_host *host)
936 {
937 struct mmc_data *data;
938
939 BUG_ON(!host->data);
940
941 data = host->data;
942 host->data = NULL;
943
944 if (host->flags & SDHCI_REQ_USE_DMA) {
945 if (host->flags & SDHCI_USE_ADMA)
946 sdhci_adma_table_post(host, data);
947 else {
948 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
949 data->sg_len, (data->flags & MMC_DATA_READ) ?
950 DMA_FROM_DEVICE : DMA_TO_DEVICE);
951 }
952 }
953
954 /*
955 * The specification states that the block count register must
956 * be updated, but it does not specify at what point in the
957 * data flow. That makes the register entirely useless to read
958 * back so we have to assume that nothing made it to the card
959 * in the event of an error.
960 */
961 if (data->error)
962 data->bytes_xfered = 0;
963 else
964 data->bytes_xfered = data->blksz * data->blocks;
965
966 /*
967 * Need to send CMD12 if -
968 * a) open-ended multiblock transfer (no CMD23)
969 * b) error in multiblock transfer
970 */
971 if (data->stop &&
972 (data->error ||
973 !host->mrq->sbc)) {
974
975 /*
976 * The controller needs a reset of internal state machines
977 * upon error conditions.
978 */
979 if (data->error) {
980 sdhci_do_reset(host, SDHCI_RESET_CMD);
981 sdhci_do_reset(host, SDHCI_RESET_DATA);
982 }
983
984 sdhci_send_command(host, data->stop);
985 } else
986 tasklet_schedule(&host->finish_tasklet);
987 }
988
sdhci_send_command(struct sdhci_host * host,struct mmc_command * cmd)989 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
990 {
991 int flags;
992 u32 mask;
993 unsigned long timeout;
994
995 WARN_ON(host->cmd);
996
997 /* Wait max 10 ms */
998 timeout = 10;
999
1000 mask = SDHCI_CMD_INHIBIT;
1001 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1002 mask |= SDHCI_DATA_INHIBIT;
1003
1004 /* We shouldn't wait for data inihibit for stop commands, even
1005 though they might use busy signaling */
1006 if (host->mrq->data && (cmd == host->mrq->data->stop))
1007 mask &= ~SDHCI_DATA_INHIBIT;
1008
1009 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1010 if (timeout == 0) {
1011 pr_err("%s: Controller never released "
1012 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1013 sdhci_dumpregs(host);
1014 cmd->error = -EIO;
1015 tasklet_schedule(&host->finish_tasklet);
1016 return;
1017 }
1018 timeout--;
1019 mdelay(1);
1020 }
1021
1022 timeout = jiffies;
1023 if (!cmd->data && cmd->busy_timeout > 9000)
1024 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1025 else
1026 timeout += 10 * HZ;
1027 mod_timer(&host->timer, timeout);
1028
1029 host->cmd = cmd;
1030 host->busy_handle = 0;
1031
1032 sdhci_prepare_data(host, cmd);
1033
1034 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1035
1036 sdhci_set_transfer_mode(host, cmd);
1037
1038 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1039 pr_err("%s: Unsupported response type!\n",
1040 mmc_hostname(host->mmc));
1041 cmd->error = -EINVAL;
1042 tasklet_schedule(&host->finish_tasklet);
1043 return;
1044 }
1045
1046 if (!(cmd->flags & MMC_RSP_PRESENT))
1047 flags = SDHCI_CMD_RESP_NONE;
1048 else if (cmd->flags & MMC_RSP_136)
1049 flags = SDHCI_CMD_RESP_LONG;
1050 else if (cmd->flags & MMC_RSP_BUSY)
1051 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1052 else
1053 flags = SDHCI_CMD_RESP_SHORT;
1054
1055 if (cmd->flags & MMC_RSP_CRC)
1056 flags |= SDHCI_CMD_CRC;
1057 if (cmd->flags & MMC_RSP_OPCODE)
1058 flags |= SDHCI_CMD_INDEX;
1059
1060 /* CMD19 is special in that the Data Present Select should be set */
1061 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1062 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1063 flags |= SDHCI_CMD_DATA;
1064
1065 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1066 }
1067 EXPORT_SYMBOL_GPL(sdhci_send_command);
1068
sdhci_finish_command(struct sdhci_host * host)1069 static void sdhci_finish_command(struct sdhci_host *host)
1070 {
1071 int i;
1072
1073 BUG_ON(host->cmd == NULL);
1074
1075 if (host->cmd->flags & MMC_RSP_PRESENT) {
1076 if (host->cmd->flags & MMC_RSP_136) {
1077 /* CRC is stripped so we need to do some shifting. */
1078 for (i = 0;i < 4;i++) {
1079 host->cmd->resp[i] = sdhci_readl(host,
1080 SDHCI_RESPONSE + (3-i)*4) << 8;
1081 if (i != 3)
1082 host->cmd->resp[i] |=
1083 sdhci_readb(host,
1084 SDHCI_RESPONSE + (3-i)*4-1);
1085 }
1086 } else {
1087 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1088 }
1089 }
1090
1091 host->cmd->error = 0;
1092
1093 /* Finished CMD23, now send actual command. */
1094 if (host->cmd == host->mrq->sbc) {
1095 host->cmd = NULL;
1096 sdhci_send_command(host, host->mrq->cmd);
1097 } else {
1098
1099 /* Processed actual command. */
1100 if (host->data && host->data_early)
1101 sdhci_finish_data(host);
1102
1103 if (!host->cmd->data)
1104 tasklet_schedule(&host->finish_tasklet);
1105
1106 host->cmd = NULL;
1107 }
1108 }
1109
sdhci_get_preset_value(struct sdhci_host * host)1110 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1111 {
1112 u16 preset = 0;
1113
1114 switch (host->timing) {
1115 case MMC_TIMING_UHS_SDR12:
1116 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1117 break;
1118 case MMC_TIMING_UHS_SDR25:
1119 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1120 break;
1121 case MMC_TIMING_UHS_SDR50:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1123 break;
1124 case MMC_TIMING_UHS_SDR104:
1125 case MMC_TIMING_MMC_HS200:
1126 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1127 break;
1128 case MMC_TIMING_UHS_DDR50:
1129 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1130 break;
1131 default:
1132 pr_warn("%s: Invalid UHS-I mode selected\n",
1133 mmc_hostname(host->mmc));
1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1135 break;
1136 }
1137 return preset;
1138 }
1139
sdhci_set_clock(struct sdhci_host * host,unsigned int clock)1140 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1141 {
1142 int div = 0; /* Initialized for compiler warning */
1143 int real_div = div, clk_mul = 1;
1144 u16 clk = 0;
1145 unsigned long timeout;
1146
1147 host->mmc->actual_clock = 0;
1148
1149 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1150
1151 if (clock == 0)
1152 return;
1153
1154 if (host->version >= SDHCI_SPEC_300) {
1155 if (host->preset_enabled) {
1156 u16 pre_val;
1157
1158 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1159 pre_val = sdhci_get_preset_value(host);
1160 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1161 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1162 if (host->clk_mul &&
1163 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1164 clk = SDHCI_PROG_CLOCK_MODE;
1165 real_div = div + 1;
1166 clk_mul = host->clk_mul;
1167 } else {
1168 real_div = max_t(int, 1, div << 1);
1169 }
1170 goto clock_set;
1171 }
1172
1173 /*
1174 * Check if the Host Controller supports Programmable Clock
1175 * Mode.
1176 */
1177 if (host->clk_mul) {
1178 for (div = 1; div <= 1024; div++) {
1179 if ((host->max_clk * host->clk_mul / div)
1180 <= clock)
1181 break;
1182 }
1183 /*
1184 * Set Programmable Clock Mode in the Clock
1185 * Control register.
1186 */
1187 clk = SDHCI_PROG_CLOCK_MODE;
1188 real_div = div;
1189 clk_mul = host->clk_mul;
1190 div--;
1191 } else {
1192 /* Version 3.00 divisors must be a multiple of 2. */
1193 if (host->max_clk <= clock)
1194 div = 1;
1195 else {
1196 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1197 div += 2) {
1198 if ((host->max_clk / div) <= clock)
1199 break;
1200 }
1201 }
1202 real_div = div;
1203 div >>= 1;
1204 }
1205 } else {
1206 /* Version 2.00 divisors must be a power of 2. */
1207 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1208 if ((host->max_clk / div) <= clock)
1209 break;
1210 }
1211 real_div = div;
1212 div >>= 1;
1213 }
1214
1215 clock_set:
1216 if (real_div)
1217 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1218 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1219 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1220 << SDHCI_DIVIDER_HI_SHIFT;
1221 clk |= SDHCI_CLOCK_INT_EN;
1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1223
1224 /* Wait max 20 ms */
1225 timeout = 20;
1226 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1227 & SDHCI_CLOCK_INT_STABLE)) {
1228 if (timeout == 0) {
1229 pr_err("%s: Internal clock never "
1230 "stabilised.\n", mmc_hostname(host->mmc));
1231 sdhci_dumpregs(host);
1232 return;
1233 }
1234 timeout--;
1235 spin_unlock_irq(&host->lock);
1236 usleep_range(900, 1100);
1237 spin_lock_irq(&host->lock);
1238 }
1239
1240 clk |= SDHCI_CLOCK_CARD_EN;
1241 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1242 }
1243 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1244
sdhci_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)1245 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1246 unsigned short vdd)
1247 {
1248 struct mmc_host *mmc = host->mmc;
1249 u8 pwr = 0;
1250
1251 if (!IS_ERR(mmc->supply.vmmc)) {
1252 spin_unlock_irq(&host->lock);
1253 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1254 spin_lock_irq(&host->lock);
1255
1256 if (mode != MMC_POWER_OFF)
1257 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1258 else
1259 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1260
1261 return;
1262 }
1263
1264 if (mode != MMC_POWER_OFF) {
1265 switch (1 << vdd) {
1266 case MMC_VDD_165_195:
1267 pwr = SDHCI_POWER_180;
1268 break;
1269 case MMC_VDD_29_30:
1270 case MMC_VDD_30_31:
1271 pwr = SDHCI_POWER_300;
1272 break;
1273 case MMC_VDD_32_33:
1274 case MMC_VDD_33_34:
1275 pwr = SDHCI_POWER_330;
1276 break;
1277 default:
1278 BUG();
1279 }
1280 }
1281
1282 if (host->pwr == pwr)
1283 return;
1284
1285 host->pwr = pwr;
1286
1287 if (pwr == 0) {
1288 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1289 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1290 sdhci_runtime_pm_bus_off(host);
1291 vdd = 0;
1292 } else {
1293 /*
1294 * Spec says that we should clear the power reg before setting
1295 * a new value. Some controllers don't seem to like this though.
1296 */
1297 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1298 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1299
1300 /*
1301 * At least the Marvell CaFe chip gets confused if we set the
1302 * voltage and set turn on power at the same time, so set the
1303 * voltage first.
1304 */
1305 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1306 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1307
1308 pwr |= SDHCI_POWER_ON;
1309
1310 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1311
1312 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1313 sdhci_runtime_pm_bus_on(host);
1314
1315 /*
1316 * Some controllers need an extra 10ms delay of 10ms before
1317 * they can apply clock after applying power
1318 */
1319 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1320 mdelay(10);
1321 }
1322 }
1323
1324 /*****************************************************************************\
1325 * *
1326 * MMC callbacks *
1327 * *
1328 \*****************************************************************************/
1329
sdhci_request(struct mmc_host * mmc,struct mmc_request * mrq)1330 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1331 {
1332 struct sdhci_host *host;
1333 int present;
1334 unsigned long flags;
1335 u32 tuning_opcode;
1336
1337 host = mmc_priv(mmc);
1338
1339 sdhci_runtime_pm_get(host);
1340
1341 present = mmc_gpio_get_cd(host->mmc);
1342
1343 spin_lock_irqsave(&host->lock, flags);
1344
1345 WARN_ON(host->mrq != NULL);
1346
1347 #ifndef SDHCI_USE_LEDS_CLASS
1348 sdhci_activate_led(host);
1349 #endif
1350
1351 /*
1352 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1353 * requests if Auto-CMD12 is enabled.
1354 */
1355 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1356 if (mrq->stop) {
1357 mrq->data->stop = NULL;
1358 mrq->stop = NULL;
1359 }
1360 }
1361
1362 host->mrq = mrq;
1363
1364 /*
1365 * Firstly check card presence from cd-gpio. The return could
1366 * be one of the following possibilities:
1367 * negative: cd-gpio is not available
1368 * zero: cd-gpio is used, and card is removed
1369 * one: cd-gpio is used, and card is present
1370 */
1371 if (present < 0) {
1372 /* If polling, assume that the card is always present. */
1373 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1374 present = 1;
1375 else
1376 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1377 SDHCI_CARD_PRESENT;
1378 }
1379
1380 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1381 host->mrq->cmd->error = -ENOMEDIUM;
1382 tasklet_schedule(&host->finish_tasklet);
1383 } else {
1384 u32 present_state;
1385
1386 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1387 /*
1388 * Check if the re-tuning timer has already expired and there
1389 * is no on-going data transfer and DAT0 is not busy. If so,
1390 * we need to execute tuning procedure before sending command.
1391 */
1392 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1393 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1394 (present_state & SDHCI_DATA_0_LVL_MASK)) {
1395 if (mmc->card) {
1396 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1397 tuning_opcode =
1398 mmc->card->type == MMC_TYPE_MMC ?
1399 MMC_SEND_TUNING_BLOCK_HS200 :
1400 MMC_SEND_TUNING_BLOCK;
1401
1402 /* Here we need to set the host->mrq to NULL,
1403 * in case the pending finish_tasklet
1404 * finishes it incorrectly.
1405 */
1406 host->mrq = NULL;
1407
1408 spin_unlock_irqrestore(&host->lock, flags);
1409 sdhci_execute_tuning(mmc, tuning_opcode);
1410 spin_lock_irqsave(&host->lock, flags);
1411
1412 /* Restore original mmc_request structure */
1413 host->mrq = mrq;
1414 }
1415 }
1416
1417 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1418 sdhci_send_command(host, mrq->sbc);
1419 else
1420 sdhci_send_command(host, mrq->cmd);
1421 }
1422
1423 mmiowb();
1424 spin_unlock_irqrestore(&host->lock, flags);
1425 }
1426
sdhci_set_bus_width(struct sdhci_host * host,int width)1427 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1428 {
1429 u8 ctrl;
1430
1431 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1432 if (width == MMC_BUS_WIDTH_8) {
1433 ctrl &= ~SDHCI_CTRL_4BITBUS;
1434 if (host->version >= SDHCI_SPEC_300)
1435 ctrl |= SDHCI_CTRL_8BITBUS;
1436 } else {
1437 if (host->version >= SDHCI_SPEC_300)
1438 ctrl &= ~SDHCI_CTRL_8BITBUS;
1439 if (width == MMC_BUS_WIDTH_4)
1440 ctrl |= SDHCI_CTRL_4BITBUS;
1441 else
1442 ctrl &= ~SDHCI_CTRL_4BITBUS;
1443 }
1444 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1445 }
1446 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1447
sdhci_set_uhs_signaling(struct sdhci_host * host,unsigned timing)1448 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1449 {
1450 u16 ctrl_2;
1451
1452 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1453 /* Select Bus Speed Mode for host */
1454 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1455 if ((timing == MMC_TIMING_MMC_HS200) ||
1456 (timing == MMC_TIMING_UHS_SDR104))
1457 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1458 else if (timing == MMC_TIMING_UHS_SDR12)
1459 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1460 else if (timing == MMC_TIMING_UHS_SDR25)
1461 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1462 else if (timing == MMC_TIMING_UHS_SDR50)
1463 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1464 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1465 (timing == MMC_TIMING_MMC_DDR52))
1466 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1467 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1468 }
1469 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1470
sdhci_do_set_ios(struct sdhci_host * host,struct mmc_ios * ios)1471 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1472 {
1473 unsigned long flags;
1474 u8 ctrl;
1475 struct mmc_host *mmc = host->mmc;
1476
1477 spin_lock_irqsave(&host->lock, flags);
1478
1479 if (host->flags & SDHCI_DEVICE_DEAD) {
1480 spin_unlock_irqrestore(&host->lock, flags);
1481 if (!IS_ERR(mmc->supply.vmmc) &&
1482 ios->power_mode == MMC_POWER_OFF)
1483 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1484 return;
1485 }
1486
1487 /*
1488 * Reset the chip on each power off.
1489 * Should clear out any weird states.
1490 */
1491 if (ios->power_mode == MMC_POWER_OFF) {
1492 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1493 sdhci_reinit(host);
1494 }
1495
1496 if (host->version >= SDHCI_SPEC_300 &&
1497 (ios->power_mode == MMC_POWER_UP) &&
1498 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1499 sdhci_enable_preset_value(host, false);
1500
1501 if (!ios->clock || ios->clock != host->clock) {
1502 host->ops->set_clock(host, ios->clock);
1503 host->clock = ios->clock;
1504
1505 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1506 host->clock) {
1507 host->timeout_clk = host->mmc->actual_clock ?
1508 host->mmc->actual_clock / 1000 :
1509 host->clock / 1000;
1510 host->mmc->max_busy_timeout =
1511 host->ops->get_max_timeout_count ?
1512 host->ops->get_max_timeout_count(host) :
1513 1 << 27;
1514 host->mmc->max_busy_timeout /= host->timeout_clk;
1515 }
1516 }
1517
1518 sdhci_set_power(host, ios->power_mode, ios->vdd);
1519
1520 if (host->ops->platform_send_init_74_clocks)
1521 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1522
1523 host->ops->set_bus_width(host, ios->bus_width);
1524
1525 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1526
1527 if ((ios->timing == MMC_TIMING_SD_HS ||
1528 ios->timing == MMC_TIMING_MMC_HS)
1529 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1530 ctrl |= SDHCI_CTRL_HISPD;
1531 else
1532 ctrl &= ~SDHCI_CTRL_HISPD;
1533
1534 if (host->version >= SDHCI_SPEC_300) {
1535 u16 clk, ctrl_2;
1536
1537 /* In case of UHS-I modes, set High Speed Enable */
1538 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1539 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1540 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1541 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1542 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1543 (ios->timing == MMC_TIMING_UHS_SDR25))
1544 ctrl |= SDHCI_CTRL_HISPD;
1545
1546 if (!host->preset_enabled) {
1547 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1548 /*
1549 * We only need to set Driver Strength if the
1550 * preset value enable is not set.
1551 */
1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1553 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1554 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1555 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1556 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1557 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1558
1559 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1560 } else {
1561 /*
1562 * According to SDHC Spec v3.00, if the Preset Value
1563 * Enable in the Host Control 2 register is set, we
1564 * need to reset SD Clock Enable before changing High
1565 * Speed Enable to avoid generating clock gliches.
1566 */
1567
1568 /* Reset SD Clock Enable */
1569 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1570 clk &= ~SDHCI_CLOCK_CARD_EN;
1571 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1572
1573 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1574
1575 /* Re-enable SD Clock */
1576 host->ops->set_clock(host, host->clock);
1577 }
1578
1579 /* Reset SD Clock Enable */
1580 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1581 clk &= ~SDHCI_CLOCK_CARD_EN;
1582 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1583
1584 host->ops->set_uhs_signaling(host, ios->timing);
1585 host->timing = ios->timing;
1586
1587 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1588 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1589 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1590 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1591 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1592 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1593 u16 preset;
1594
1595 sdhci_enable_preset_value(host, true);
1596 preset = sdhci_get_preset_value(host);
1597 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1598 >> SDHCI_PRESET_DRV_SHIFT;
1599 }
1600
1601 /* Re-enable SD Clock */
1602 host->ops->set_clock(host, host->clock);
1603 } else
1604 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1605
1606 /*
1607 * Some (ENE) controllers go apeshit on some ios operation,
1608 * signalling timeout and CRC errors even on CMD0. Resetting
1609 * it on each ios seems to solve the problem.
1610 */
1611 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1612 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1613
1614 mmiowb();
1615 spin_unlock_irqrestore(&host->lock, flags);
1616 }
1617
sdhci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1618 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1619 {
1620 struct sdhci_host *host = mmc_priv(mmc);
1621
1622 sdhci_runtime_pm_get(host);
1623 sdhci_do_set_ios(host, ios);
1624 sdhci_runtime_pm_put(host);
1625 }
1626
sdhci_do_get_cd(struct sdhci_host * host)1627 static int sdhci_do_get_cd(struct sdhci_host *host)
1628 {
1629 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1630
1631 if (host->flags & SDHCI_DEVICE_DEAD)
1632 return 0;
1633
1634 /* If polling/nonremovable, assume that the card is always present. */
1635 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1636 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1637 return 1;
1638
1639 /* Try slot gpio detect */
1640 if (!IS_ERR_VALUE(gpio_cd))
1641 return !!gpio_cd;
1642
1643 /* Host native card detect */
1644 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1645 }
1646
sdhci_get_cd(struct mmc_host * mmc)1647 static int sdhci_get_cd(struct mmc_host *mmc)
1648 {
1649 struct sdhci_host *host = mmc_priv(mmc);
1650 int ret;
1651
1652 sdhci_runtime_pm_get(host);
1653 ret = sdhci_do_get_cd(host);
1654 sdhci_runtime_pm_put(host);
1655 return ret;
1656 }
1657
sdhci_check_ro(struct sdhci_host * host)1658 static int sdhci_check_ro(struct sdhci_host *host)
1659 {
1660 unsigned long flags;
1661 int is_readonly;
1662
1663 spin_lock_irqsave(&host->lock, flags);
1664
1665 if (host->flags & SDHCI_DEVICE_DEAD)
1666 is_readonly = 0;
1667 else if (host->ops->get_ro)
1668 is_readonly = host->ops->get_ro(host);
1669 else
1670 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1671 & SDHCI_WRITE_PROTECT);
1672
1673 spin_unlock_irqrestore(&host->lock, flags);
1674
1675 /* This quirk needs to be replaced by a callback-function later */
1676 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1677 !is_readonly : is_readonly;
1678 }
1679
1680 #define SAMPLE_COUNT 5
1681
sdhci_do_get_ro(struct sdhci_host * host)1682 static int sdhci_do_get_ro(struct sdhci_host *host)
1683 {
1684 int i, ro_count;
1685
1686 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1687 return sdhci_check_ro(host);
1688
1689 ro_count = 0;
1690 for (i = 0; i < SAMPLE_COUNT; i++) {
1691 if (sdhci_check_ro(host)) {
1692 if (++ro_count > SAMPLE_COUNT / 2)
1693 return 1;
1694 }
1695 msleep(30);
1696 }
1697 return 0;
1698 }
1699
sdhci_hw_reset(struct mmc_host * mmc)1700 static void sdhci_hw_reset(struct mmc_host *mmc)
1701 {
1702 struct sdhci_host *host = mmc_priv(mmc);
1703
1704 if (host->ops && host->ops->hw_reset)
1705 host->ops->hw_reset(host);
1706 }
1707
sdhci_get_ro(struct mmc_host * mmc)1708 static int sdhci_get_ro(struct mmc_host *mmc)
1709 {
1710 struct sdhci_host *host = mmc_priv(mmc);
1711 int ret;
1712
1713 sdhci_runtime_pm_get(host);
1714 ret = sdhci_do_get_ro(host);
1715 sdhci_runtime_pm_put(host);
1716 return ret;
1717 }
1718
sdhci_enable_sdio_irq_nolock(struct sdhci_host * host,int enable)1719 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1720 {
1721 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1722 if (enable)
1723 host->ier |= SDHCI_INT_CARD_INT;
1724 else
1725 host->ier &= ~SDHCI_INT_CARD_INT;
1726
1727 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1728 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1729 mmiowb();
1730 }
1731 }
1732
sdhci_enable_sdio_irq(struct mmc_host * mmc,int enable)1733 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1734 {
1735 struct sdhci_host *host = mmc_priv(mmc);
1736 unsigned long flags;
1737
1738 sdhci_runtime_pm_get(host);
1739
1740 spin_lock_irqsave(&host->lock, flags);
1741 if (enable)
1742 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1743 else
1744 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1745
1746 sdhci_enable_sdio_irq_nolock(host, enable);
1747 spin_unlock_irqrestore(&host->lock, flags);
1748
1749 sdhci_runtime_pm_put(host);
1750 }
1751
sdhci_do_start_signal_voltage_switch(struct sdhci_host * host,struct mmc_ios * ios)1752 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1753 struct mmc_ios *ios)
1754 {
1755 struct mmc_host *mmc = host->mmc;
1756 u16 ctrl;
1757 int ret;
1758
1759 /*
1760 * Signal Voltage Switching is only applicable for Host Controllers
1761 * v3.00 and above.
1762 */
1763 if (host->version < SDHCI_SPEC_300)
1764 return 0;
1765
1766 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767
1768 switch (ios->signal_voltage) {
1769 case MMC_SIGNAL_VOLTAGE_330:
1770 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1771 ctrl &= ~SDHCI_CTRL_VDD_180;
1772 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1773
1774 if (!IS_ERR(mmc->supply.vqmmc)) {
1775 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1776 3600000);
1777 if (ret) {
1778 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1779 mmc_hostname(mmc));
1780 return -EIO;
1781 }
1782 }
1783 /* Wait for 5ms */
1784 usleep_range(5000, 5500);
1785
1786 /* 3.3V regulator output should be stable within 5 ms */
1787 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1788 if (!(ctrl & SDHCI_CTRL_VDD_180))
1789 return 0;
1790
1791 pr_warn("%s: 3.3V regulator output did not became stable\n",
1792 mmc_hostname(mmc));
1793
1794 return -EAGAIN;
1795 case MMC_SIGNAL_VOLTAGE_180:
1796 if (!IS_ERR(mmc->supply.vqmmc)) {
1797 ret = regulator_set_voltage(mmc->supply.vqmmc,
1798 1700000, 1950000);
1799 if (ret) {
1800 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1801 mmc_hostname(mmc));
1802 return -EIO;
1803 }
1804 }
1805
1806 /*
1807 * Enable 1.8V Signal Enable in the Host Control2
1808 * register
1809 */
1810 ctrl |= SDHCI_CTRL_VDD_180;
1811 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1812
1813 /* 1.8V regulator output should be stable within 5 ms */
1814 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1815 if (ctrl & SDHCI_CTRL_VDD_180)
1816 return 0;
1817
1818 pr_warn("%s: 1.8V regulator output did not became stable\n",
1819 mmc_hostname(mmc));
1820
1821 return -EAGAIN;
1822 case MMC_SIGNAL_VOLTAGE_120:
1823 if (!IS_ERR(mmc->supply.vqmmc)) {
1824 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1825 1300000);
1826 if (ret) {
1827 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1828 mmc_hostname(mmc));
1829 return -EIO;
1830 }
1831 }
1832 return 0;
1833 default:
1834 /* No signal voltage switch required */
1835 return 0;
1836 }
1837 }
1838
sdhci_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1839 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1840 struct mmc_ios *ios)
1841 {
1842 struct sdhci_host *host = mmc_priv(mmc);
1843 int err;
1844
1845 if (host->version < SDHCI_SPEC_300)
1846 return 0;
1847 sdhci_runtime_pm_get(host);
1848 err = sdhci_do_start_signal_voltage_switch(host, ios);
1849 sdhci_runtime_pm_put(host);
1850 return err;
1851 }
1852
sdhci_card_busy(struct mmc_host * mmc)1853 static int sdhci_card_busy(struct mmc_host *mmc)
1854 {
1855 struct sdhci_host *host = mmc_priv(mmc);
1856 u32 present_state;
1857
1858 sdhci_runtime_pm_get(host);
1859 /* Check whether DAT[3:0] is 0000 */
1860 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1861 sdhci_runtime_pm_put(host);
1862
1863 return !(present_state & SDHCI_DATA_LVL_MASK);
1864 }
1865
sdhci_execute_tuning(struct mmc_host * mmc,u32 opcode)1866 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1867 {
1868 struct sdhci_host *host = mmc_priv(mmc);
1869 u16 ctrl;
1870 int tuning_loop_counter = MAX_TUNING_LOOP;
1871 int err = 0;
1872 unsigned long flags;
1873
1874 sdhci_runtime_pm_get(host);
1875 spin_lock_irqsave(&host->lock, flags);
1876
1877 /*
1878 * The Host Controller needs tuning only in case of SDR104 mode
1879 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1880 * Capabilities register.
1881 * If the Host Controller supports the HS200 mode then the
1882 * tuning function has to be executed.
1883 */
1884 switch (host->timing) {
1885 case MMC_TIMING_MMC_HS200:
1886 case MMC_TIMING_UHS_SDR104:
1887 break;
1888
1889 case MMC_TIMING_UHS_SDR50:
1890 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1891 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1892 break;
1893 /* FALLTHROUGH */
1894
1895 default:
1896 spin_unlock_irqrestore(&host->lock, flags);
1897 sdhci_runtime_pm_put(host);
1898 return 0;
1899 }
1900
1901 if (host->ops->platform_execute_tuning) {
1902 spin_unlock_irqrestore(&host->lock, flags);
1903 err = host->ops->platform_execute_tuning(host, opcode);
1904 sdhci_runtime_pm_put(host);
1905 return err;
1906 }
1907
1908 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1909 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1910 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1911
1912 /*
1913 * As per the Host Controller spec v3.00, tuning command
1914 * generates Buffer Read Ready interrupt, so enable that.
1915 *
1916 * Note: The spec clearly says that when tuning sequence
1917 * is being performed, the controller does not generate
1918 * interrupts other than Buffer Read Ready interrupt. But
1919 * to make sure we don't hit a controller bug, we _only_
1920 * enable Buffer Read Ready interrupt here.
1921 */
1922 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1923 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1924
1925 /*
1926 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1927 * of loops reaches 40 times or a timeout of 150ms occurs.
1928 */
1929 do {
1930 struct mmc_command cmd = {0};
1931 struct mmc_request mrq = {NULL};
1932
1933 cmd.opcode = opcode;
1934 cmd.arg = 0;
1935 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1936 cmd.retries = 0;
1937 cmd.data = NULL;
1938 cmd.error = 0;
1939
1940 if (tuning_loop_counter-- == 0)
1941 break;
1942
1943 mrq.cmd = &cmd;
1944 host->mrq = &mrq;
1945
1946 /*
1947 * In response to CMD19, the card sends 64 bytes of tuning
1948 * block to the Host Controller. So we set the block size
1949 * to 64 here.
1950 */
1951 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1952 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1953 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1954 SDHCI_BLOCK_SIZE);
1955 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1956 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1957 SDHCI_BLOCK_SIZE);
1958 } else {
1959 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1960 SDHCI_BLOCK_SIZE);
1961 }
1962
1963 /*
1964 * The tuning block is sent by the card to the host controller.
1965 * So we set the TRNS_READ bit in the Transfer Mode register.
1966 * This also takes care of setting DMA Enable and Multi Block
1967 * Select in the same register to 0.
1968 */
1969 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1970
1971 sdhci_send_command(host, &cmd);
1972
1973 host->cmd = NULL;
1974 host->mrq = NULL;
1975
1976 spin_unlock_irqrestore(&host->lock, flags);
1977 /* Wait for Buffer Read Ready interrupt */
1978 wait_event_interruptible_timeout(host->buf_ready_int,
1979 (host->tuning_done == 1),
1980 msecs_to_jiffies(50));
1981 spin_lock_irqsave(&host->lock, flags);
1982
1983 if (!host->tuning_done) {
1984 pr_info(DRIVER_NAME ": Timeout waiting for "
1985 "Buffer Read Ready interrupt during tuning "
1986 "procedure, falling back to fixed sampling "
1987 "clock\n");
1988 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1989 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1990 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1991 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1992
1993 sdhci_do_reset(host, SDHCI_RESET_CMD);
1994 sdhci_do_reset(host, SDHCI_RESET_DATA);
1995
1996 err = -EIO;
1997
1998 if (cmd.opcode != MMC_SEND_TUNING_BLOCK_HS200)
1999 goto out;
2000
2001 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2002 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2003
2004 spin_unlock_irqrestore(&host->lock, flags);
2005
2006 memset(&cmd, 0, sizeof(cmd));
2007 cmd.opcode = MMC_STOP_TRANSMISSION;
2008 cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
2009 cmd.busy_timeout = 50;
2010 mmc_wait_for_cmd(mmc, &cmd, 0);
2011
2012 spin_lock_irqsave(&host->lock, flags);
2013
2014 goto out;
2015 }
2016
2017 host->tuning_done = 0;
2018
2019 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2020
2021 /* eMMC spec does not require a delay between tuning cycles */
2022 if (opcode == MMC_SEND_TUNING_BLOCK)
2023 mdelay(1);
2024 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2025
2026 /*
2027 * The Host Driver has exhausted the maximum number of loops allowed,
2028 * so use fixed sampling frequency.
2029 */
2030 if (tuning_loop_counter < 0) {
2031 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2032 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2033 }
2034 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2035 pr_info(DRIVER_NAME ": Tuning procedure"
2036 " failed, falling back to fixed sampling"
2037 " clock\n");
2038 err = -EIO;
2039 }
2040
2041 out:
2042 /*
2043 * If this is the very first time we are here, we start the retuning
2044 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2045 * flag won't be set, we check this condition before actually starting
2046 * the timer.
2047 */
2048 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2049 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2050 host->flags |= SDHCI_USING_RETUNING_TIMER;
2051 mod_timer(&host->tuning_timer, jiffies +
2052 host->tuning_count * HZ);
2053 /* Tuning mode 1 limits the maximum data length to 4MB */
2054 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2055 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2056 host->flags &= ~SDHCI_NEEDS_RETUNING;
2057 /* Reload the new initial value for timer */
2058 mod_timer(&host->tuning_timer, jiffies +
2059 host->tuning_count * HZ);
2060 }
2061
2062 /*
2063 * In case tuning fails, host controllers which support re-tuning can
2064 * try tuning again at a later time, when the re-tuning timer expires.
2065 * So for these controllers, we return 0. Since there might be other
2066 * controllers who do not have this capability, we return error for
2067 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2068 * a retuning timer to do the retuning for the card.
2069 */
2070 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2071 err = 0;
2072
2073 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2074 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2075 spin_unlock_irqrestore(&host->lock, flags);
2076 sdhci_runtime_pm_put(host);
2077
2078 return err;
2079 }
2080
2081
sdhci_enable_preset_value(struct sdhci_host * host,bool enable)2082 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2083 {
2084 /* Host Controller v3.00 defines preset value registers */
2085 if (host->version < SDHCI_SPEC_300)
2086 return;
2087
2088 /*
2089 * We only enable or disable Preset Value if they are not already
2090 * enabled or disabled respectively. Otherwise, we bail out.
2091 */
2092 if (host->preset_enabled != enable) {
2093 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2094
2095 if (enable)
2096 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2097 else
2098 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2099
2100 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2101
2102 if (enable)
2103 host->flags |= SDHCI_PV_ENABLED;
2104 else
2105 host->flags &= ~SDHCI_PV_ENABLED;
2106
2107 host->preset_enabled = enable;
2108 }
2109 }
2110
sdhci_card_event(struct mmc_host * mmc)2111 static void sdhci_card_event(struct mmc_host *mmc)
2112 {
2113 struct sdhci_host *host = mmc_priv(mmc);
2114 unsigned long flags;
2115 int present;
2116
2117 /* First check if client has provided their own card event */
2118 if (host->ops->card_event)
2119 host->ops->card_event(host);
2120
2121 present = sdhci_do_get_cd(host);
2122
2123 spin_lock_irqsave(&host->lock, flags);
2124
2125 /* Check host->mrq first in case we are runtime suspended */
2126 if (host->mrq && !present) {
2127 pr_err("%s: Card removed during transfer!\n",
2128 mmc_hostname(host->mmc));
2129 pr_err("%s: Resetting controller.\n",
2130 mmc_hostname(host->mmc));
2131
2132 sdhci_do_reset(host, SDHCI_RESET_CMD);
2133 sdhci_do_reset(host, SDHCI_RESET_DATA);
2134
2135 host->mrq->cmd->error = -ENOMEDIUM;
2136 tasklet_schedule(&host->finish_tasklet);
2137 }
2138
2139 spin_unlock_irqrestore(&host->lock, flags);
2140 }
2141
2142 static const struct mmc_host_ops sdhci_ops = {
2143 .request = sdhci_request,
2144 .set_ios = sdhci_set_ios,
2145 .get_cd = sdhci_get_cd,
2146 .get_ro = sdhci_get_ro,
2147 .hw_reset = sdhci_hw_reset,
2148 .enable_sdio_irq = sdhci_enable_sdio_irq,
2149 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2150 .execute_tuning = sdhci_execute_tuning,
2151 .card_event = sdhci_card_event,
2152 .card_busy = sdhci_card_busy,
2153 };
2154
2155 /*****************************************************************************\
2156 * *
2157 * Tasklets *
2158 * *
2159 \*****************************************************************************/
2160
sdhci_tasklet_finish(unsigned long param)2161 static void sdhci_tasklet_finish(unsigned long param)
2162 {
2163 struct sdhci_host *host;
2164 unsigned long flags;
2165 struct mmc_request *mrq;
2166
2167 host = (struct sdhci_host*)param;
2168
2169 spin_lock_irqsave(&host->lock, flags);
2170
2171 /*
2172 * If this tasklet gets rescheduled while running, it will
2173 * be run again afterwards but without any active request.
2174 */
2175 if (!host->mrq) {
2176 spin_unlock_irqrestore(&host->lock, flags);
2177 return;
2178 }
2179
2180 del_timer(&host->timer);
2181
2182 mrq = host->mrq;
2183
2184 /*
2185 * The controller needs a reset of internal state machines
2186 * upon error conditions.
2187 */
2188 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2189 ((mrq->cmd && mrq->cmd->error) ||
2190 (mrq->data && (mrq->data->error ||
2191 (mrq->data->stop && mrq->data->stop->error))) ||
2192 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2193
2194 /* Some controllers need this kick or reset won't work here */
2195 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2196 /* This is to force an update */
2197 host->ops->set_clock(host, host->clock);
2198
2199 /* Spec says we should do both at the same time, but Ricoh
2200 controllers do not like that. */
2201 sdhci_do_reset(host, SDHCI_RESET_CMD);
2202 sdhci_do_reset(host, SDHCI_RESET_DATA);
2203 }
2204
2205 host->mrq = NULL;
2206 host->cmd = NULL;
2207 host->data = NULL;
2208
2209 #ifndef SDHCI_USE_LEDS_CLASS
2210 sdhci_deactivate_led(host);
2211 #endif
2212
2213 mmiowb();
2214 spin_unlock_irqrestore(&host->lock, flags);
2215
2216 mmc_request_done(host->mmc, mrq);
2217 sdhci_runtime_pm_put(host);
2218 }
2219
sdhci_timeout_timer(unsigned long data)2220 static void sdhci_timeout_timer(unsigned long data)
2221 {
2222 struct sdhci_host *host;
2223 unsigned long flags;
2224
2225 host = (struct sdhci_host*)data;
2226
2227 spin_lock_irqsave(&host->lock, flags);
2228
2229 if (host->mrq) {
2230 pr_err("%s: Timeout waiting for hardware "
2231 "interrupt.\n", mmc_hostname(host->mmc));
2232 sdhci_dumpregs(host);
2233
2234 if (host->data) {
2235 host->data->error = -ETIMEDOUT;
2236 sdhci_finish_data(host);
2237 } else {
2238 if (host->cmd)
2239 host->cmd->error = -ETIMEDOUT;
2240 else
2241 host->mrq->cmd->error = -ETIMEDOUT;
2242
2243 tasklet_schedule(&host->finish_tasklet);
2244 }
2245 }
2246
2247 mmiowb();
2248 spin_unlock_irqrestore(&host->lock, flags);
2249 }
2250
sdhci_tuning_timer(unsigned long data)2251 static void sdhci_tuning_timer(unsigned long data)
2252 {
2253 struct sdhci_host *host;
2254 unsigned long flags;
2255
2256 host = (struct sdhci_host *)data;
2257
2258 spin_lock_irqsave(&host->lock, flags);
2259
2260 host->flags |= SDHCI_NEEDS_RETUNING;
2261
2262 spin_unlock_irqrestore(&host->lock, flags);
2263 }
2264
2265 /*****************************************************************************\
2266 * *
2267 * Interrupt handling *
2268 * *
2269 \*****************************************************************************/
2270
sdhci_cmd_irq(struct sdhci_host * host,u32 intmask,u32 * mask)2271 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2272 {
2273 BUG_ON(intmask == 0);
2274
2275 if (!host->cmd) {
2276 pr_err("%s: Got command interrupt 0x%08x even "
2277 "though no command operation was in progress.\n",
2278 mmc_hostname(host->mmc), (unsigned)intmask);
2279 sdhci_dumpregs(host);
2280 return;
2281 }
2282
2283 if (intmask & SDHCI_INT_TIMEOUT)
2284 host->cmd->error = -ETIMEDOUT;
2285 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2286 SDHCI_INT_INDEX))
2287 host->cmd->error = -EILSEQ;
2288
2289 if (host->cmd->error) {
2290 tasklet_schedule(&host->finish_tasklet);
2291 return;
2292 }
2293
2294 /*
2295 * The host can send and interrupt when the busy state has
2296 * ended, allowing us to wait without wasting CPU cycles.
2297 * Unfortunately this is overloaded on the "data complete"
2298 * interrupt, so we need to take some care when handling
2299 * it.
2300 *
2301 * Note: The 1.0 specification is a bit ambiguous about this
2302 * feature so there might be some problems with older
2303 * controllers.
2304 */
2305 if (host->cmd->flags & MMC_RSP_BUSY) {
2306 if (host->cmd->data)
2307 DBG("Cannot wait for busy signal when also "
2308 "doing a data transfer");
2309 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2310 && !host->busy_handle) {
2311 /* Mark that command complete before busy is ended */
2312 host->busy_handle = 1;
2313 return;
2314 }
2315
2316 /* The controller does not support the end-of-busy IRQ,
2317 * fall through and take the SDHCI_INT_RESPONSE */
2318 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2319 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2320 *mask &= ~SDHCI_INT_DATA_END;
2321 }
2322
2323 if (intmask & SDHCI_INT_RESPONSE)
2324 sdhci_finish_command(host);
2325 }
2326
2327 #ifdef CONFIG_MMC_DEBUG
sdhci_show_adma_error(struct sdhci_host * host)2328 static void sdhci_show_adma_error(struct sdhci_host *host)
2329 {
2330 const char *name = mmc_hostname(host->mmc);
2331 u8 *desc = host->adma_desc;
2332 __le32 *dma;
2333 __le16 *len;
2334 u8 attr;
2335
2336 sdhci_dumpregs(host);
2337
2338 while (true) {
2339 dma = (__le32 *)(desc + 4);
2340 len = (__le16 *)(desc + 2);
2341 attr = *desc;
2342
2343 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2344 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2345
2346 desc += 8;
2347
2348 if (attr & 2)
2349 break;
2350 }
2351 }
2352 #else
sdhci_show_adma_error(struct sdhci_host * host)2353 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2354 #endif
2355
sdhci_data_irq(struct sdhci_host * host,u32 intmask)2356 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2357 {
2358 u32 command;
2359 BUG_ON(intmask == 0);
2360
2361 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2362 if (intmask & SDHCI_INT_DATA_AVAIL) {
2363 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2364 if (command == MMC_SEND_TUNING_BLOCK ||
2365 command == MMC_SEND_TUNING_BLOCK_HS200) {
2366 host->tuning_done = 1;
2367 wake_up(&host->buf_ready_int);
2368 return;
2369 }
2370 }
2371
2372 if (!host->data) {
2373 /*
2374 * The "data complete" interrupt is also used to
2375 * indicate that a busy state has ended. See comment
2376 * above in sdhci_cmd_irq().
2377 */
2378 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2379 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2380 host->cmd->error = -ETIMEDOUT;
2381 tasklet_schedule(&host->finish_tasklet);
2382 return;
2383 }
2384 if (intmask & SDHCI_INT_DATA_END) {
2385 /*
2386 * Some cards handle busy-end interrupt
2387 * before the command completed, so make
2388 * sure we do things in the proper order.
2389 */
2390 if (host->busy_handle)
2391 sdhci_finish_command(host);
2392 else
2393 host->busy_handle = 1;
2394 return;
2395 }
2396 }
2397
2398 pr_err("%s: Got data interrupt 0x%08x even "
2399 "though no data operation was in progress.\n",
2400 mmc_hostname(host->mmc), (unsigned)intmask);
2401 sdhci_dumpregs(host);
2402
2403 return;
2404 }
2405
2406 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2407 host->data->error = -ETIMEDOUT;
2408 else if (intmask & SDHCI_INT_DATA_END_BIT)
2409 host->data->error = -EILSEQ;
2410 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2411 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2412 != MMC_BUS_TEST_R)
2413 host->data->error = -EILSEQ;
2414 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2415 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2416 sdhci_show_adma_error(host);
2417 host->data->error = -EIO;
2418 if (host->ops->adma_workaround)
2419 host->ops->adma_workaround(host, intmask);
2420 }
2421
2422 if (host->data->error)
2423 sdhci_finish_data(host);
2424 else {
2425 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2426 sdhci_transfer_pio(host);
2427
2428 /*
2429 * We currently don't do anything fancy with DMA
2430 * boundaries, but as we can't disable the feature
2431 * we need to at least restart the transfer.
2432 *
2433 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2434 * should return a valid address to continue from, but as
2435 * some controllers are faulty, don't trust them.
2436 */
2437 if (intmask & SDHCI_INT_DMA_END) {
2438 u32 dmastart, dmanow;
2439 dmastart = sg_dma_address(host->data->sg);
2440 dmanow = dmastart + host->data->bytes_xfered;
2441 /*
2442 * Force update to the next DMA block boundary.
2443 */
2444 dmanow = (dmanow &
2445 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2446 SDHCI_DEFAULT_BOUNDARY_SIZE;
2447 host->data->bytes_xfered = dmanow - dmastart;
2448 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2449 " next 0x%08x\n",
2450 mmc_hostname(host->mmc), dmastart,
2451 host->data->bytes_xfered, dmanow);
2452 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2453 }
2454
2455 if (intmask & SDHCI_INT_DATA_END) {
2456 if (host->cmd) {
2457 /*
2458 * Data managed to finish before the
2459 * command completed. Make sure we do
2460 * things in the proper order.
2461 */
2462 host->data_early = 1;
2463 } else {
2464 sdhci_finish_data(host);
2465 }
2466 }
2467 }
2468 }
2469
sdhci_irq(int irq,void * dev_id)2470 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2471 {
2472 irqreturn_t result = IRQ_NONE;
2473 struct sdhci_host *host = dev_id;
2474 u32 intmask, mask, unexpected = 0;
2475 int max_loops = 16;
2476
2477 spin_lock(&host->lock);
2478
2479 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2480 spin_unlock(&host->lock);
2481 return IRQ_NONE;
2482 }
2483
2484 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2485 if (!intmask || intmask == 0xffffffff) {
2486 result = IRQ_NONE;
2487 goto out;
2488 }
2489
2490 do {
2491 /* Clear selected interrupts. */
2492 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2493 SDHCI_INT_BUS_POWER);
2494 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2495
2496 DBG("*** %s got interrupt: 0x%08x\n",
2497 mmc_hostname(host->mmc), intmask);
2498
2499 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2500 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2501 SDHCI_CARD_PRESENT;
2502
2503 /*
2504 * There is a observation on i.mx esdhc. INSERT
2505 * bit will be immediately set again when it gets
2506 * cleared, if a card is inserted. We have to mask
2507 * the irq to prevent interrupt storm which will
2508 * freeze the system. And the REMOVE gets the
2509 * same situation.
2510 *
2511 * More testing are needed here to ensure it works
2512 * for other platforms though.
2513 */
2514 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2515 SDHCI_INT_CARD_REMOVE);
2516 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2517 SDHCI_INT_CARD_INSERT;
2518 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2519 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2520
2521 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2522 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2523
2524 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2525 SDHCI_INT_CARD_REMOVE);
2526 result = IRQ_WAKE_THREAD;
2527 }
2528
2529 if (intmask & SDHCI_INT_CMD_MASK)
2530 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2531 &intmask);
2532
2533 if (intmask & SDHCI_INT_DATA_MASK)
2534 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2535
2536 if (intmask & SDHCI_INT_BUS_POWER)
2537 pr_err("%s: Card is consuming too much power!\n",
2538 mmc_hostname(host->mmc));
2539
2540 if (intmask & SDHCI_INT_CARD_INT) {
2541 sdhci_enable_sdio_irq_nolock(host, false);
2542 host->thread_isr |= SDHCI_INT_CARD_INT;
2543 result = IRQ_WAKE_THREAD;
2544 }
2545
2546 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2547 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2548 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2549 SDHCI_INT_CARD_INT);
2550
2551 if (intmask) {
2552 unexpected |= intmask;
2553 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2554 }
2555
2556 if (result == IRQ_NONE)
2557 result = IRQ_HANDLED;
2558
2559 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2560 } while (intmask && --max_loops);
2561 out:
2562 spin_unlock(&host->lock);
2563
2564 if (unexpected) {
2565 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2566 mmc_hostname(host->mmc), unexpected);
2567 sdhci_dumpregs(host);
2568 }
2569
2570 return result;
2571 }
2572
sdhci_thread_irq(int irq,void * dev_id)2573 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2574 {
2575 struct sdhci_host *host = dev_id;
2576 unsigned long flags;
2577 u32 isr;
2578
2579 spin_lock_irqsave(&host->lock, flags);
2580 isr = host->thread_isr;
2581 host->thread_isr = 0;
2582 spin_unlock_irqrestore(&host->lock, flags);
2583
2584 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2585 sdhci_card_event(host->mmc);
2586 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2587 }
2588
2589 if (isr & SDHCI_INT_CARD_INT) {
2590 sdio_run_irqs(host->mmc);
2591
2592 spin_lock_irqsave(&host->lock, flags);
2593 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2594 sdhci_enable_sdio_irq_nolock(host, true);
2595 spin_unlock_irqrestore(&host->lock, flags);
2596 }
2597
2598 return isr ? IRQ_HANDLED : IRQ_NONE;
2599 }
2600
2601 /*****************************************************************************\
2602 * *
2603 * Suspend/resume *
2604 * *
2605 \*****************************************************************************/
2606
2607 #ifdef CONFIG_PM
sdhci_enable_irq_wakeups(struct sdhci_host * host)2608 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2609 {
2610 u8 val;
2611 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2612 | SDHCI_WAKE_ON_INT;
2613
2614 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2615 val |= mask ;
2616 /* Avoid fake wake up */
2617 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2618 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2619 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2620 }
2621 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2622
sdhci_disable_irq_wakeups(struct sdhci_host * host)2623 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2624 {
2625 u8 val;
2626 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2627 | SDHCI_WAKE_ON_INT;
2628
2629 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2630 val &= ~mask;
2631 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2632 }
2633
sdhci_suspend_host(struct sdhci_host * host)2634 int sdhci_suspend_host(struct sdhci_host *host)
2635 {
2636 sdhci_disable_card_detection(host);
2637
2638 /* Disable tuning since we are suspending */
2639 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2640 del_timer_sync(&host->tuning_timer);
2641 host->flags &= ~SDHCI_NEEDS_RETUNING;
2642 }
2643
2644 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2645 host->ier = 0;
2646 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2647 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2648 free_irq(host->irq, host);
2649 } else {
2650 sdhci_enable_irq_wakeups(host);
2651 enable_irq_wake(host->irq);
2652 }
2653 return 0;
2654 }
2655
2656 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2657
sdhci_resume_host(struct sdhci_host * host)2658 int sdhci_resume_host(struct sdhci_host *host)
2659 {
2660 int ret = 0;
2661
2662 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2663 if (host->ops->enable_dma)
2664 host->ops->enable_dma(host);
2665 }
2666
2667 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2668 ret = request_threaded_irq(host->irq, sdhci_irq,
2669 sdhci_thread_irq, IRQF_SHARED,
2670 mmc_hostname(host->mmc), host);
2671 if (ret)
2672 return ret;
2673 } else {
2674 sdhci_disable_irq_wakeups(host);
2675 disable_irq_wake(host->irq);
2676 }
2677
2678 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2679 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2680 /* Card keeps power but host controller does not */
2681 sdhci_init(host, 0);
2682 host->pwr = 0;
2683 host->clock = 0;
2684 sdhci_do_set_ios(host, &host->mmc->ios);
2685 } else {
2686 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2687 mmiowb();
2688 }
2689
2690 sdhci_enable_card_detection(host);
2691
2692 /* Set the re-tuning expiration flag */
2693 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2694 host->flags |= SDHCI_NEEDS_RETUNING;
2695
2696 return ret;
2697 }
2698
2699 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2700 #endif /* CONFIG_PM */
2701
2702 #ifdef CONFIG_PM_RUNTIME
2703
sdhci_runtime_pm_get(struct sdhci_host * host)2704 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2705 {
2706 return pm_runtime_get_sync(host->mmc->parent);
2707 }
2708
sdhci_runtime_pm_put(struct sdhci_host * host)2709 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2710 {
2711 pm_runtime_mark_last_busy(host->mmc->parent);
2712 return pm_runtime_put_autosuspend(host->mmc->parent);
2713 }
2714
sdhci_runtime_pm_bus_on(struct sdhci_host * host)2715 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2716 {
2717 if (host->bus_on)
2718 return;
2719 host->bus_on = true;
2720 pm_runtime_get_noresume(host->mmc->parent);
2721 }
2722
sdhci_runtime_pm_bus_off(struct sdhci_host * host)2723 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2724 {
2725 if (!host->bus_on)
2726 return;
2727 host->bus_on = false;
2728 pm_runtime_put_noidle(host->mmc->parent);
2729 }
2730
sdhci_runtime_suspend_host(struct sdhci_host * host)2731 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2732 {
2733 unsigned long flags;
2734
2735 /* Disable tuning since we are suspending */
2736 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2737 del_timer_sync(&host->tuning_timer);
2738 host->flags &= ~SDHCI_NEEDS_RETUNING;
2739 }
2740
2741 spin_lock_irqsave(&host->lock, flags);
2742 host->ier &= SDHCI_INT_CARD_INT;
2743 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2744 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2745 spin_unlock_irqrestore(&host->lock, flags);
2746
2747 synchronize_hardirq(host->irq);
2748
2749 spin_lock_irqsave(&host->lock, flags);
2750 host->runtime_suspended = true;
2751 spin_unlock_irqrestore(&host->lock, flags);
2752
2753 return 0;
2754 }
2755 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2756
sdhci_runtime_resume_host(struct sdhci_host * host)2757 int sdhci_runtime_resume_host(struct sdhci_host *host)
2758 {
2759 unsigned long flags;
2760 int host_flags = host->flags;
2761
2762 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2763 if (host->ops->enable_dma)
2764 host->ops->enable_dma(host);
2765 }
2766
2767 sdhci_init(host, 0);
2768
2769 /* Force clock and power re-program */
2770 host->pwr = 0;
2771 host->clock = 0;
2772 sdhci_do_set_ios(host, &host->mmc->ios);
2773
2774 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2775 if ((host_flags & SDHCI_PV_ENABLED) &&
2776 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2777 spin_lock_irqsave(&host->lock, flags);
2778 sdhci_enable_preset_value(host, true);
2779 spin_unlock_irqrestore(&host->lock, flags);
2780 }
2781
2782 /* Set the re-tuning expiration flag */
2783 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2784 host->flags |= SDHCI_NEEDS_RETUNING;
2785
2786 spin_lock_irqsave(&host->lock, flags);
2787
2788 host->runtime_suspended = false;
2789
2790 /* Enable SDIO IRQ */
2791 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2792 sdhci_enable_sdio_irq_nolock(host, true);
2793
2794 /* Enable Card Detection */
2795 sdhci_enable_card_detection(host);
2796
2797 spin_unlock_irqrestore(&host->lock, flags);
2798
2799 return 0;
2800 }
2801 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2802
2803 #endif
2804
2805 /*****************************************************************************\
2806 * *
2807 * Device allocation/registration *
2808 * *
2809 \*****************************************************************************/
2810
sdhci_alloc_host(struct device * dev,size_t priv_size)2811 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2812 size_t priv_size)
2813 {
2814 struct mmc_host *mmc;
2815 struct sdhci_host *host;
2816
2817 WARN_ON(dev == NULL);
2818
2819 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2820 if (!mmc)
2821 return ERR_PTR(-ENOMEM);
2822
2823 host = mmc_priv(mmc);
2824 host->mmc = mmc;
2825
2826 return host;
2827 }
2828
2829 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2830
sdhci_add_host(struct sdhci_host * host)2831 int sdhci_add_host(struct sdhci_host *host)
2832 {
2833 struct mmc_host *mmc;
2834 u32 caps[2] = {0, 0};
2835 u32 max_current_caps;
2836 unsigned int ocr_avail;
2837 unsigned int override_timeout_clk;
2838 int ret;
2839
2840 WARN_ON(host == NULL);
2841 if (host == NULL)
2842 return -EINVAL;
2843
2844 mmc = host->mmc;
2845
2846 if (debug_quirks)
2847 host->quirks = debug_quirks;
2848 if (debug_quirks2)
2849 host->quirks2 = debug_quirks2;
2850
2851 override_timeout_clk = host->timeout_clk;
2852
2853 sdhci_do_reset(host, SDHCI_RESET_ALL);
2854
2855 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2856 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2857 >> SDHCI_SPEC_VER_SHIFT;
2858 if (host->version > SDHCI_SPEC_300) {
2859 pr_err("%s: Unknown controller version (%d). "
2860 "You may experience problems.\n", mmc_hostname(mmc),
2861 host->version);
2862 }
2863
2864 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2865 sdhci_readl(host, SDHCI_CAPABILITIES);
2866
2867 if (host->version >= SDHCI_SPEC_300)
2868 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2869 host->caps1 :
2870 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2871
2872 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2873 host->flags |= SDHCI_USE_SDMA;
2874 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2875 DBG("Controller doesn't have SDMA capability\n");
2876 else
2877 host->flags |= SDHCI_USE_SDMA;
2878
2879 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2880 (host->flags & SDHCI_USE_SDMA)) {
2881 DBG("Disabling DMA as it is marked broken\n");
2882 host->flags &= ~SDHCI_USE_SDMA;
2883 }
2884
2885 if ((host->version >= SDHCI_SPEC_200) &&
2886 (caps[0] & SDHCI_CAN_DO_ADMA2))
2887 host->flags |= SDHCI_USE_ADMA;
2888
2889 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2890 (host->flags & SDHCI_USE_ADMA)) {
2891 DBG("Disabling ADMA as it is marked broken\n");
2892 host->flags &= ~SDHCI_USE_ADMA;
2893 }
2894
2895 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2896 if (host->ops->enable_dma) {
2897 if (host->ops->enable_dma(host)) {
2898 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2899 mmc_hostname(mmc));
2900 host->flags &=
2901 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2902 }
2903 }
2904 }
2905
2906 if (host->flags & SDHCI_USE_ADMA) {
2907 /*
2908 * We need to allocate descriptors for all sg entries
2909 * (128) and potentially one alignment transfer for
2910 * each of those entries.
2911 */
2912 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2913 ADMA_SIZE, &host->adma_addr,
2914 GFP_KERNEL);
2915 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2916 if (!host->adma_desc || !host->align_buffer) {
2917 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2918 host->adma_desc, host->adma_addr);
2919 kfree(host->align_buffer);
2920 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2921 mmc_hostname(mmc));
2922 host->flags &= ~SDHCI_USE_ADMA;
2923 host->adma_desc = NULL;
2924 host->align_buffer = NULL;
2925 } else if (host->adma_addr & 3) {
2926 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2927 mmc_hostname(mmc));
2928 host->flags &= ~SDHCI_USE_ADMA;
2929 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2930 host->adma_desc, host->adma_addr);
2931 kfree(host->align_buffer);
2932 host->adma_desc = NULL;
2933 host->align_buffer = NULL;
2934 }
2935 }
2936
2937 /*
2938 * If we use DMA, then it's up to the caller to set the DMA
2939 * mask, but PIO does not need the hw shim so we set a new
2940 * mask here in that case.
2941 */
2942 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2943 host->dma_mask = DMA_BIT_MASK(64);
2944 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2945 }
2946
2947 if (host->version >= SDHCI_SPEC_300)
2948 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2949 >> SDHCI_CLOCK_BASE_SHIFT;
2950 else
2951 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2952 >> SDHCI_CLOCK_BASE_SHIFT;
2953
2954 host->max_clk *= 1000000;
2955 if (host->max_clk == 0 || host->quirks &
2956 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2957 if (!host->ops->get_max_clock) {
2958 pr_err("%s: Hardware doesn't specify base clock "
2959 "frequency.\n", mmc_hostname(mmc));
2960 return -ENODEV;
2961 }
2962 host->max_clk = host->ops->get_max_clock(host);
2963 }
2964
2965 /*
2966 * In case of Host Controller v3.00, find out whether clock
2967 * multiplier is supported.
2968 */
2969 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2970 SDHCI_CLOCK_MUL_SHIFT;
2971
2972 /*
2973 * In case the value in Clock Multiplier is 0, then programmable
2974 * clock mode is not supported, otherwise the actual clock
2975 * multiplier is one more than the value of Clock Multiplier
2976 * in the Capabilities Register.
2977 */
2978 if (host->clk_mul)
2979 host->clk_mul += 1;
2980
2981 /*
2982 * Set host parameters.
2983 */
2984 mmc->ops = &sdhci_ops;
2985 mmc->f_max = host->max_clk;
2986 if (host->ops->get_min_clock)
2987 mmc->f_min = host->ops->get_min_clock(host);
2988 else if (host->version >= SDHCI_SPEC_300) {
2989 if (host->clk_mul) {
2990 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2991 mmc->f_max = host->max_clk * host->clk_mul;
2992 } else
2993 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2994 } else
2995 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2996
2997 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2998 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2999 SDHCI_TIMEOUT_CLK_SHIFT;
3000 if (host->timeout_clk == 0) {
3001 if (host->ops->get_timeout_clock) {
3002 host->timeout_clk =
3003 host->ops->get_timeout_clock(host);
3004 } else {
3005 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3006 mmc_hostname(mmc));
3007 return -ENODEV;
3008 }
3009 }
3010
3011 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3012 host->timeout_clk *= 1000;
3013
3014 if (override_timeout_clk)
3015 host->timeout_clk = override_timeout_clk;
3016
3017 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3018 host->ops->get_max_timeout_count(host) : 1 << 27;
3019 mmc->max_busy_timeout /= host->timeout_clk;
3020 }
3021
3022 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3023 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3024
3025 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3026 host->flags |= SDHCI_AUTO_CMD12;
3027
3028 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3029 if ((host->version >= SDHCI_SPEC_300) &&
3030 ((host->flags & SDHCI_USE_ADMA) ||
3031 !(host->flags & SDHCI_USE_SDMA))) {
3032 host->flags |= SDHCI_AUTO_CMD23;
3033 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3034 } else {
3035 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3036 }
3037
3038 /*
3039 * A controller may support 8-bit width, but the board itself
3040 * might not have the pins brought out. Boards that support
3041 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3042 * their platform code before calling sdhci_add_host(), and we
3043 * won't assume 8-bit width for hosts without that CAP.
3044 */
3045 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3046 mmc->caps |= MMC_CAP_4_BIT_DATA;
3047
3048 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3049 mmc->caps &= ~MMC_CAP_CMD23;
3050
3051 if (caps[0] & SDHCI_CAN_DO_HISPD)
3052 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3053
3054 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3055 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3056 mmc->caps |= MMC_CAP_NEEDS_POLL;
3057
3058 /* If there are external regulators, get them */
3059 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3060 return -EPROBE_DEFER;
3061
3062 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3063 if (!IS_ERR(mmc->supply.vqmmc)) {
3064 ret = regulator_enable(mmc->supply.vqmmc);
3065 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3066 1950000))
3067 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3068 SDHCI_SUPPORT_SDR50 |
3069 SDHCI_SUPPORT_DDR50);
3070 if (ret) {
3071 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3072 mmc_hostname(mmc), ret);
3073 mmc->supply.vqmmc = NULL;
3074 }
3075 }
3076
3077 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3078 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3079 SDHCI_SUPPORT_DDR50);
3080
3081 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3082 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3083 SDHCI_SUPPORT_DDR50))
3084 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3085
3086 /* SDR104 supports also implies SDR50 support */
3087 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3088 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3089 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3090 * field can be promoted to support HS200.
3091 */
3092 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
3093 mmc->caps2 |= MMC_CAP2_HS200;
3094 if (IS_ERR(mmc->supply.vqmmc) ||
3095 !regulator_is_supported_voltage
3096 (mmc->supply.vqmmc, 1100000, 1300000))
3097 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3098 }
3099 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3100 mmc->caps |= MMC_CAP_UHS_SDR50;
3101
3102 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3103 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3104 mmc->caps |= MMC_CAP_UHS_DDR50;
3105
3106 /* Does the host need tuning for SDR50? */
3107 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3108 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3109
3110 /* Does the host need tuning for SDR104 / HS200? */
3111 if (mmc->caps2 & MMC_CAP2_HS200)
3112 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3113
3114 /* Driver Type(s) (A, C, D) supported by the host */
3115 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3116 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3117 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3118 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3119 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3120 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3121
3122 /* Initial value for re-tuning timer count */
3123 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3124 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3125
3126 /*
3127 * In case Re-tuning Timer is not disabled, the actual value of
3128 * re-tuning timer will be 2 ^ (n - 1).
3129 */
3130 if (host->tuning_count)
3131 host->tuning_count = 1 << (host->tuning_count - 1);
3132
3133 /* Re-tuning mode supported by the Host Controller */
3134 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3135 SDHCI_RETUNING_MODE_SHIFT;
3136
3137 ocr_avail = 0;
3138
3139 /*
3140 * According to SD Host Controller spec v3.00, if the Host System
3141 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3142 * the value is meaningful only if Voltage Support in the Capabilities
3143 * register is set. The actual current value is 4 times the register
3144 * value.
3145 */
3146 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3147 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3148 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3149 if (curr > 0) {
3150
3151 /* convert to SDHCI_MAX_CURRENT format */
3152 curr = curr/1000; /* convert to mA */
3153 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3154
3155 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3156 max_current_caps =
3157 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3158 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3159 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3160 }
3161 }
3162
3163 if (caps[0] & SDHCI_CAN_VDD_330) {
3164 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3165
3166 mmc->max_current_330 = ((max_current_caps &
3167 SDHCI_MAX_CURRENT_330_MASK) >>
3168 SDHCI_MAX_CURRENT_330_SHIFT) *
3169 SDHCI_MAX_CURRENT_MULTIPLIER;
3170 }
3171 if (caps[0] & SDHCI_CAN_VDD_300) {
3172 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3173
3174 mmc->max_current_300 = ((max_current_caps &
3175 SDHCI_MAX_CURRENT_300_MASK) >>
3176 SDHCI_MAX_CURRENT_300_SHIFT) *
3177 SDHCI_MAX_CURRENT_MULTIPLIER;
3178 }
3179 if (caps[0] & SDHCI_CAN_VDD_180) {
3180 ocr_avail |= MMC_VDD_165_195;
3181
3182 mmc->max_current_180 = ((max_current_caps &
3183 SDHCI_MAX_CURRENT_180_MASK) >>
3184 SDHCI_MAX_CURRENT_180_SHIFT) *
3185 SDHCI_MAX_CURRENT_MULTIPLIER;
3186 }
3187
3188 /* If OCR set by external regulators, use it instead */
3189 if (mmc->ocr_avail)
3190 ocr_avail = mmc->ocr_avail;
3191
3192 if (host->ocr_mask)
3193 ocr_avail &= host->ocr_mask;
3194
3195 mmc->ocr_avail = ocr_avail;
3196 mmc->ocr_avail_sdio = ocr_avail;
3197 if (host->ocr_avail_sdio)
3198 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3199 mmc->ocr_avail_sd = ocr_avail;
3200 if (host->ocr_avail_sd)
3201 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3202 else /* normal SD controllers don't support 1.8V */
3203 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3204 mmc->ocr_avail_mmc = ocr_avail;
3205 if (host->ocr_avail_mmc)
3206 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3207
3208 if (mmc->ocr_avail == 0) {
3209 pr_err("%s: Hardware doesn't report any "
3210 "support voltages.\n", mmc_hostname(mmc));
3211 return -ENODEV;
3212 }
3213
3214 spin_lock_init(&host->lock);
3215
3216 /*
3217 * Maximum number of segments. Depends on if the hardware
3218 * can do scatter/gather or not.
3219 */
3220 if (host->flags & SDHCI_USE_ADMA)
3221 mmc->max_segs = 128;
3222 else if (host->flags & SDHCI_USE_SDMA)
3223 mmc->max_segs = 1;
3224 else /* PIO */
3225 mmc->max_segs = 128;
3226
3227 /*
3228 * Maximum number of sectors in one transfer. Limited by DMA boundary
3229 * size (512KiB).
3230 */
3231 mmc->max_req_size = 524288;
3232
3233 /*
3234 * Maximum segment size. Could be one segment with the maximum number
3235 * of bytes. When doing hardware scatter/gather, each entry cannot
3236 * be larger than 64 KiB though.
3237 */
3238 if (host->flags & SDHCI_USE_ADMA) {
3239 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3240 mmc->max_seg_size = 65535;
3241 else
3242 mmc->max_seg_size = 65536;
3243 } else {
3244 mmc->max_seg_size = mmc->max_req_size;
3245 }
3246
3247 /*
3248 * Maximum block size. This varies from controller to controller and
3249 * is specified in the capabilities register.
3250 */
3251 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3252 mmc->max_blk_size = 2;
3253 } else {
3254 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3255 SDHCI_MAX_BLOCK_SHIFT;
3256 if (mmc->max_blk_size >= 3) {
3257 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3258 mmc_hostname(mmc));
3259 mmc->max_blk_size = 0;
3260 }
3261 }
3262
3263 mmc->max_blk_size = 512 << mmc->max_blk_size;
3264
3265 /*
3266 * Maximum block count.
3267 */
3268 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3269
3270 /*
3271 * Init tasklets.
3272 */
3273 tasklet_init(&host->finish_tasklet,
3274 sdhci_tasklet_finish, (unsigned long)host);
3275
3276 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3277
3278 if (host->version >= SDHCI_SPEC_300) {
3279 init_waitqueue_head(&host->buf_ready_int);
3280
3281 /* Initialize re-tuning timer */
3282 init_timer(&host->tuning_timer);
3283 host->tuning_timer.data = (unsigned long)host;
3284 host->tuning_timer.function = sdhci_tuning_timer;
3285 }
3286
3287 sdhci_init(host, 0);
3288
3289 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3290 IRQF_SHARED, mmc_hostname(mmc), host);
3291 if (ret) {
3292 pr_err("%s: Failed to request IRQ %d: %d\n",
3293 mmc_hostname(mmc), host->irq, ret);
3294 goto untasklet;
3295 }
3296
3297 #ifdef CONFIG_MMC_DEBUG
3298 sdhci_dumpregs(host);
3299 #endif
3300
3301 #ifdef SDHCI_USE_LEDS_CLASS
3302 snprintf(host->led_name, sizeof(host->led_name),
3303 "%s::", mmc_hostname(mmc));
3304 host->led.name = host->led_name;
3305 host->led.brightness = LED_OFF;
3306 host->led.default_trigger = mmc_hostname(mmc);
3307 host->led.brightness_set = sdhci_led_control;
3308
3309 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3310 if (ret) {
3311 pr_err("%s: Failed to register LED device: %d\n",
3312 mmc_hostname(mmc), ret);
3313 goto reset;
3314 }
3315 #endif
3316
3317 mmiowb();
3318
3319 mmc_add_host(mmc);
3320
3321 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3322 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3323 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3324 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3325
3326 sdhci_enable_card_detection(host);
3327
3328 return 0;
3329
3330 #ifdef SDHCI_USE_LEDS_CLASS
3331 reset:
3332 sdhci_do_reset(host, SDHCI_RESET_ALL);
3333 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3334 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3335 free_irq(host->irq, host);
3336 #endif
3337 untasklet:
3338 tasklet_kill(&host->finish_tasklet);
3339
3340 return ret;
3341 }
3342
3343 EXPORT_SYMBOL_GPL(sdhci_add_host);
3344
sdhci_remove_host(struct sdhci_host * host,int dead)3345 void sdhci_remove_host(struct sdhci_host *host, int dead)
3346 {
3347 struct mmc_host *mmc = host->mmc;
3348 unsigned long flags;
3349
3350 if (dead) {
3351 spin_lock_irqsave(&host->lock, flags);
3352
3353 host->flags |= SDHCI_DEVICE_DEAD;
3354
3355 if (host->mrq) {
3356 pr_err("%s: Controller removed during "
3357 " transfer!\n", mmc_hostname(mmc));
3358
3359 host->mrq->cmd->error = -ENOMEDIUM;
3360 tasklet_schedule(&host->finish_tasklet);
3361 }
3362
3363 spin_unlock_irqrestore(&host->lock, flags);
3364 }
3365
3366 sdhci_disable_card_detection(host);
3367
3368 mmc_remove_host(mmc);
3369
3370 #ifdef SDHCI_USE_LEDS_CLASS
3371 led_classdev_unregister(&host->led);
3372 #endif
3373
3374 if (!dead)
3375 sdhci_do_reset(host, SDHCI_RESET_ALL);
3376
3377 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3378 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3379 free_irq(host->irq, host);
3380
3381 del_timer_sync(&host->timer);
3382
3383 tasklet_kill(&host->finish_tasklet);
3384
3385 if (!IS_ERR(mmc->supply.vmmc))
3386 regulator_disable(mmc->supply.vmmc);
3387
3388 if (!IS_ERR(mmc->supply.vqmmc))
3389 regulator_disable(mmc->supply.vqmmc);
3390
3391 if (host->adma_desc)
3392 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3393 host->adma_desc, host->adma_addr);
3394 kfree(host->align_buffer);
3395
3396 host->adma_desc = NULL;
3397 host->align_buffer = NULL;
3398 }
3399
3400 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3401
sdhci_free_host(struct sdhci_host * host)3402 void sdhci_free_host(struct sdhci_host *host)
3403 {
3404 mmc_free_host(host->mmc);
3405 }
3406
3407 EXPORT_SYMBOL_GPL(sdhci_free_host);
3408
3409 /*****************************************************************************\
3410 * *
3411 * Driver init/exit *
3412 * *
3413 \*****************************************************************************/
3414
sdhci_drv_init(void)3415 static int __init sdhci_drv_init(void)
3416 {
3417 pr_info(DRIVER_NAME
3418 ": Secure Digital Host Controller Interface driver\n");
3419 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3420
3421 return 0;
3422 }
3423
sdhci_drv_exit(void)3424 static void __exit sdhci_drv_exit(void)
3425 {
3426 }
3427
3428 module_init(sdhci_drv_init);
3429 module_exit(sdhci_drv_exit);
3430
3431 module_param(debug_quirks, uint, 0444);
3432 module_param(debug_quirks2, uint, 0444);
3433
3434 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3435 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3436 MODULE_LICENSE("GPL");
3437
3438 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3439 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
3440