1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <media/videobuf2-core.h>
26 #include "s5p_mfc_common.h"
27 #include "s5p_mfc_ctrl.h"
28 #include "s5p_mfc_debug.h"
29 #include "s5p_mfc_dec.h"
30 #include "s5p_mfc_enc.h"
31 #include "s5p_mfc_intr.h"
32 #include "s5p_mfc_opr.h"
33 #include "s5p_mfc_cmd.h"
34 #include "s5p_mfc_pm.h"
35
36 #define S5P_MFC_NAME "s5p-mfc"
37 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40 int mfc_debug_level;
41 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44 /* Helper functions for interrupt processing */
45
46 /* Remove from hw execution round robin */
clear_work_bit(struct s5p_mfc_ctx * ctx)47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
48 {
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
52 __clear_bit(ctx->num, &dev->ctx_work_bits);
53 spin_unlock(&dev->condlock);
54 }
55
56 /* Add to hw execution round robin */
set_work_bit(struct s5p_mfc_ctx * ctx)57 void set_work_bit(struct s5p_mfc_ctx *ctx)
58 {
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64 }
65
66 /* Remove from hw execution round robin */
clear_work_bit_irqsave(struct s5p_mfc_ctx * ctx)67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68 {
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75 }
76
77 /* Add to hw execution round robin */
set_work_bit_irqsave(struct s5p_mfc_ctx * ctx)78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79 {
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86 }
87
88 /* Wake up context wait_queue */
wake_up_ctx(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91 {
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96 }
97
98 /* Wake up device wait_queue */
wake_up_dev(struct s5p_mfc_dev * dev,unsigned int reason,unsigned int err)99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101 {
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106 }
107
s5p_mfc_watchdog(unsigned long arg)108 static void s5p_mfc_watchdog(unsigned long arg)
109 {
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126 }
127
s5p_mfc_watchdog_worker(struct work_struct * work)128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
129 {
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
154 &ctx->dst_queue, &ctx->vq_dst);
155 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
156 &ctx->src_queue, &ctx->vq_src);
157 clear_work_bit(ctx);
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
165 ret = s5p_mfc_load_firmware(dev);
166 if (ret) {
167 mfc_err("Failed to reload FW\n");
168 goto unlock;
169 }
170 s5p_mfc_clock_on();
171 ret = s5p_mfc_init_hw(dev);
172 s5p_mfc_clock_off();
173 if (ret)
174 mfc_err("Failed to reinit FW\n");
175 }
176 unlock:
177 if (mutex_locked)
178 mutex_unlock(&dev->mfc_mutex);
179 }
180
s5p_mfc_clear_int_flags(struct s5p_mfc_dev * dev)181 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
182 {
183 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
184 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
185 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
186 }
187
s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx * ctx)188 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
189 {
190 struct s5p_mfc_buf *dst_buf;
191 struct s5p_mfc_dev *dev = ctx->dev;
192
193 ctx->state = MFCINST_FINISHED;
194 ctx->sequence++;
195 while (!list_empty(&ctx->dst_queue)) {
196 dst_buf = list_entry(ctx->dst_queue.next,
197 struct s5p_mfc_buf, list);
198 mfc_debug(2, "Cleaning up buffer: %d\n",
199 dst_buf->b->v4l2_buf.index);
200 vb2_set_plane_payload(dst_buf->b, 0, 0);
201 vb2_set_plane_payload(dst_buf->b, 1, 0);
202 list_del(&dst_buf->list);
203 ctx->dst_queue_cnt--;
204 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
205
206 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
207 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
208 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
209 else
210 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
211
212 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
213 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
214 }
215 }
216
s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx * ctx)217 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
218 {
219 struct s5p_mfc_dev *dev = ctx->dev;
220 struct s5p_mfc_buf *dst_buf, *src_buf;
221 size_t dec_y_addr;
222 unsigned int frame_type;
223
224 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
225 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
226
227 /* Copy timestamp / timecode from decoded src to dst and set
228 appropriate flags */
229 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
230 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
231 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
232 dst_buf->b->v4l2_buf.timecode =
233 src_buf->b->v4l2_buf.timecode;
234 dst_buf->b->v4l2_buf.timestamp =
235 src_buf->b->v4l2_buf.timestamp;
236 dst_buf->b->v4l2_buf.flags &=
237 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
238 dst_buf->b->v4l2_buf.flags |=
239 src_buf->b->v4l2_buf.flags
240 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
241 switch (frame_type) {
242 case S5P_FIMV_DECODE_FRAME_I_FRAME:
243 dst_buf->b->v4l2_buf.flags |=
244 V4L2_BUF_FLAG_KEYFRAME;
245 break;
246 case S5P_FIMV_DECODE_FRAME_P_FRAME:
247 dst_buf->b->v4l2_buf.flags |=
248 V4L2_BUF_FLAG_PFRAME;
249 break;
250 case S5P_FIMV_DECODE_FRAME_B_FRAME:
251 dst_buf->b->v4l2_buf.flags |=
252 V4L2_BUF_FLAG_BFRAME;
253 break;
254 }
255 break;
256 }
257 }
258 }
259
s5p_mfc_handle_frame_new(struct s5p_mfc_ctx * ctx,unsigned int err)260 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
261 {
262 struct s5p_mfc_dev *dev = ctx->dev;
263 struct s5p_mfc_buf *dst_buf;
264 size_t dspl_y_addr;
265 unsigned int frame_type;
266
267 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
268 if (IS_MFCV6_PLUS(dev))
269 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
270 get_disp_frame_type, ctx);
271 else
272 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
273 get_dec_frame_type, dev);
274
275 /* If frame is same as previous then skip and do not dequeue */
276 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
277 if (!ctx->after_packed_pb)
278 ctx->sequence++;
279 ctx->after_packed_pb = 0;
280 return;
281 }
282 ctx->sequence++;
283 /* The MFC returns address of the buffer, now we have to
284 * check which videobuf does it correspond to */
285 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
286 /* Check if this is the buffer we're looking for */
287 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
288 list_del(&dst_buf->list);
289 ctx->dst_queue_cnt--;
290 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
291 if (s5p_mfc_hw_call(dev->mfc_ops,
292 get_pic_type_top, ctx) ==
293 s5p_mfc_hw_call(dev->mfc_ops,
294 get_pic_type_bot, ctx))
295 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
296 else
297 dst_buf->b->v4l2_buf.field =
298 V4L2_FIELD_INTERLACED;
299 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
300 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
301 clear_bit(dst_buf->b->v4l2_buf.index,
302 &ctx->dec_dst_flag);
303
304 vb2_buffer_done(dst_buf->b,
305 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
306
307 break;
308 }
309 }
310 }
311
312 /* Handle frame decoding interrupt */
s5p_mfc_handle_frame(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)313 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
314 unsigned int reason, unsigned int err)
315 {
316 struct s5p_mfc_dev *dev = ctx->dev;
317 unsigned int dst_frame_status;
318 unsigned int dec_frame_status;
319 struct s5p_mfc_buf *src_buf;
320 unsigned long flags;
321 unsigned int res_change;
322
323 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
324 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
325 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
326 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
327 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
328 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
329 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
330 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
331 if (ctx->state == MFCINST_RES_CHANGE_INIT)
332 ctx->state = MFCINST_RES_CHANGE_FLUSH;
333 if (res_change == S5P_FIMV_RES_INCREASE ||
334 res_change == S5P_FIMV_RES_DECREASE) {
335 ctx->state = MFCINST_RES_CHANGE_INIT;
336 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
337 wake_up_ctx(ctx, reason, err);
338 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
339 BUG();
340 s5p_mfc_clock_off();
341 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
342 return;
343 }
344 if (ctx->dpb_flush_flag)
345 ctx->dpb_flush_flag = 0;
346
347 spin_lock_irqsave(&dev->irqlock, flags);
348 /* All frames remaining in the buffer have been extracted */
349 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
350 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
351 static const struct v4l2_event ev_src_ch = {
352 .type = V4L2_EVENT_SOURCE_CHANGE,
353 .u.src_change.changes =
354 V4L2_EVENT_SRC_CH_RESOLUTION,
355 };
356
357 s5p_mfc_handle_frame_all_extracted(ctx);
358 ctx->state = MFCINST_RES_CHANGE_END;
359 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
360
361 goto leave_handle_frame;
362 } else {
363 s5p_mfc_handle_frame_all_extracted(ctx);
364 }
365 }
366
367 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
368 s5p_mfc_handle_frame_copy_time(ctx);
369
370 /* A frame has been decoded and is in the buffer */
371 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
372 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
373 s5p_mfc_handle_frame_new(ctx, err);
374 } else {
375 mfc_debug(2, "No frame decode\n");
376 }
377 /* Mark source buffer as complete */
378 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
379 && !list_empty(&ctx->src_queue)) {
380 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
381 list);
382 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
383 get_consumed_stream, dev);
384 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
385 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
386 ctx->consumed_stream + STUFF_BYTE <
387 src_buf->b->v4l2_planes[0].bytesused) {
388 /* Run MFC again on the same buffer */
389 mfc_debug(2, "Running again the same buffer\n");
390 ctx->after_packed_pb = 1;
391 } else {
392 mfc_debug(2, "MFC needs next buffer\n");
393 ctx->consumed_stream = 0;
394 if (src_buf->flags & MFC_BUF_FLAG_EOS)
395 ctx->state = MFCINST_FINISHING;
396 list_del(&src_buf->list);
397 ctx->src_queue_cnt--;
398 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
399 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
400 else
401 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
402 }
403 }
404 leave_handle_frame:
405 spin_unlock_irqrestore(&dev->irqlock, flags);
406 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
407 || ctx->dst_queue_cnt < ctx->pb_count)
408 clear_work_bit(ctx);
409 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
410 wake_up_ctx(ctx, reason, err);
411 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
412 BUG();
413 s5p_mfc_clock_off();
414 /* if suspending, wake up device and do not try_run again*/
415 if (test_bit(0, &dev->enter_suspend))
416 wake_up_dev(dev, reason, err);
417 else
418 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
419 }
420
421 /* Error handling for interrupt */
s5p_mfc_handle_error(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)422 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
423 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
424 {
425 unsigned long flags;
426
427 mfc_err("Interrupt Error: %08x\n", err);
428
429 if (ctx != NULL) {
430 /* Error recovery is dependent on the state of context */
431 switch (ctx->state) {
432 case MFCINST_RES_CHANGE_INIT:
433 case MFCINST_RES_CHANGE_FLUSH:
434 case MFCINST_RES_CHANGE_END:
435 case MFCINST_FINISHING:
436 case MFCINST_FINISHED:
437 case MFCINST_RUNNING:
438 /* It is highly probable that an error occurred
439 * while decoding a frame */
440 clear_work_bit(ctx);
441 ctx->state = MFCINST_ERROR;
442 /* Mark all dst buffers as having an error */
443 spin_lock_irqsave(&dev->irqlock, flags);
444 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
445 &ctx->dst_queue, &ctx->vq_dst);
446 /* Mark all src buffers as having an error */
447 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
448 &ctx->src_queue, &ctx->vq_src);
449 spin_unlock_irqrestore(&dev->irqlock, flags);
450 wake_up_ctx(ctx, reason, err);
451 break;
452 default:
453 clear_work_bit(ctx);
454 ctx->state = MFCINST_ERROR;
455 wake_up_ctx(ctx, reason, err);
456 break;
457 }
458 }
459 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
460 BUG();
461 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
462 s5p_mfc_clock_off();
463 wake_up_dev(dev, reason, err);
464 return;
465 }
466
467 /* Header parsing interrupt handling */
s5p_mfc_handle_seq_done(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)468 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
469 unsigned int reason, unsigned int err)
470 {
471 struct s5p_mfc_dev *dev;
472
473 if (ctx == NULL)
474 return;
475 dev = ctx->dev;
476 if (ctx->c_ops->post_seq_start) {
477 if (ctx->c_ops->post_seq_start(ctx))
478 mfc_err("post_seq_start() failed\n");
479 } else {
480 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
481 dev);
482 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
483 dev);
484
485 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
486
487 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
488 dev);
489 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
490 dev);
491 if (ctx->img_width == 0 || ctx->img_height == 0)
492 ctx->state = MFCINST_ERROR;
493 else
494 ctx->state = MFCINST_HEAD_PARSED;
495
496 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
497 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
498 !list_empty(&ctx->src_queue)) {
499 struct s5p_mfc_buf *src_buf;
500 src_buf = list_entry(ctx->src_queue.next,
501 struct s5p_mfc_buf, list);
502 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
503 dev) <
504 src_buf->b->v4l2_planes[0].bytesused)
505 ctx->head_processed = 0;
506 else
507 ctx->head_processed = 1;
508 } else {
509 ctx->head_processed = 1;
510 }
511 }
512 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
513 clear_work_bit(ctx);
514 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
515 BUG();
516 s5p_mfc_clock_off();
517 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
518 wake_up_ctx(ctx, reason, err);
519 }
520
521 /* Header parsing interrupt handling */
s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)522 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
523 unsigned int reason, unsigned int err)
524 {
525 struct s5p_mfc_buf *src_buf;
526 struct s5p_mfc_dev *dev;
527 unsigned long flags;
528
529 if (ctx == NULL)
530 return;
531 dev = ctx->dev;
532 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
533 ctx->int_type = reason;
534 ctx->int_err = err;
535 ctx->int_cond = 1;
536 clear_work_bit(ctx);
537 if (err == 0) {
538 ctx->state = MFCINST_RUNNING;
539 if (!ctx->dpb_flush_flag && ctx->head_processed) {
540 spin_lock_irqsave(&dev->irqlock, flags);
541 if (!list_empty(&ctx->src_queue)) {
542 src_buf = list_entry(ctx->src_queue.next,
543 struct s5p_mfc_buf, list);
544 list_del(&src_buf->list);
545 ctx->src_queue_cnt--;
546 vb2_buffer_done(src_buf->b,
547 VB2_BUF_STATE_DONE);
548 }
549 spin_unlock_irqrestore(&dev->irqlock, flags);
550 } else {
551 ctx->dpb_flush_flag = 0;
552 }
553 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
554 BUG();
555
556 s5p_mfc_clock_off();
557
558 wake_up(&ctx->queue);
559 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
560 } else {
561 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
562 BUG();
563
564 s5p_mfc_clock_off();
565
566 wake_up(&ctx->queue);
567 }
568 }
569
s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)570 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
571 unsigned int reason, unsigned int err)
572 {
573 struct s5p_mfc_dev *dev = ctx->dev;
574 struct s5p_mfc_buf *mb_entry;
575
576 mfc_debug(2, "Stream completed\n");
577
578 s5p_mfc_clear_int_flags(dev);
579 ctx->int_type = reason;
580 ctx->int_err = err;
581 ctx->state = MFCINST_FINISHED;
582
583 spin_lock(&dev->irqlock);
584 if (!list_empty(&ctx->dst_queue)) {
585 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
586 list);
587 list_del(&mb_entry->list);
588 ctx->dst_queue_cnt--;
589 vb2_set_plane_payload(mb_entry->b, 0, 0);
590 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
591 }
592 spin_unlock(&dev->irqlock);
593
594 clear_work_bit(ctx);
595
596 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
597
598 s5p_mfc_clock_off();
599 wake_up(&ctx->queue);
600 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
601 }
602
603 /* Interrupt processing */
s5p_mfc_irq(int irq,void * priv)604 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
605 {
606 struct s5p_mfc_dev *dev = priv;
607 struct s5p_mfc_ctx *ctx;
608 unsigned int reason;
609 unsigned int err;
610
611 mfc_debug_enter();
612 /* Reset the timeout watchdog */
613 atomic_set(&dev->watchdog_cnt, 0);
614 ctx = dev->ctx[dev->curr_ctx];
615 /* Get the reason of interrupt and the error code */
616 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
617 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
618 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
619 switch (reason) {
620 case S5P_MFC_R2H_CMD_ERR_RET:
621 /* An error has occurred */
622 if (ctx->state == MFCINST_RUNNING &&
623 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
624 dev->warn_start)
625 s5p_mfc_handle_frame(ctx, reason, err);
626 else
627 s5p_mfc_handle_error(dev, ctx, reason, err);
628 clear_bit(0, &dev->enter_suspend);
629 break;
630
631 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
632 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
633 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
634 if (ctx->c_ops->post_frame_start) {
635 if (ctx->c_ops->post_frame_start(ctx))
636 mfc_err("post_frame_start() failed\n");
637 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
638 wake_up_ctx(ctx, reason, err);
639 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
640 BUG();
641 s5p_mfc_clock_off();
642 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
643 } else {
644 s5p_mfc_handle_frame(ctx, reason, err);
645 }
646 break;
647
648 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
649 s5p_mfc_handle_seq_done(ctx, reason, err);
650 break;
651
652 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
653 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
654 ctx->state = MFCINST_GOT_INST;
655 clear_work_bit(ctx);
656 wake_up(&ctx->queue);
657 goto irq_cleanup_hw;
658
659 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
660 clear_work_bit(ctx);
661 ctx->inst_no = MFC_NO_INSTANCE_SET;
662 ctx->state = MFCINST_FREE;
663 wake_up(&ctx->queue);
664 goto irq_cleanup_hw;
665
666 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
667 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
668 case S5P_MFC_R2H_CMD_SLEEP_RET:
669 case S5P_MFC_R2H_CMD_WAKEUP_RET:
670 if (ctx)
671 clear_work_bit(ctx);
672 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
673 wake_up_dev(dev, reason, err);
674 clear_bit(0, &dev->hw_lock);
675 clear_bit(0, &dev->enter_suspend);
676 break;
677
678 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
679 s5p_mfc_handle_init_buffers(ctx, reason, err);
680 break;
681
682 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
683 s5p_mfc_handle_stream_complete(ctx, reason, err);
684 break;
685
686 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
687 clear_work_bit(ctx);
688 ctx->state = MFCINST_RUNNING;
689 wake_up(&ctx->queue);
690 goto irq_cleanup_hw;
691
692 default:
693 mfc_debug(2, "Unknown int reason\n");
694 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
695 }
696 mfc_debug_leave();
697 return IRQ_HANDLED;
698 irq_cleanup_hw:
699 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
700 ctx->int_type = reason;
701 ctx->int_err = err;
702 ctx->int_cond = 1;
703 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
704 mfc_err("Failed to unlock hw\n");
705
706 s5p_mfc_clock_off();
707
708 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
709 mfc_debug(2, "Exit via irq_cleanup_hw\n");
710 return IRQ_HANDLED;
711 }
712
713 /* Open an MFC node */
s5p_mfc_open(struct file * file)714 static int s5p_mfc_open(struct file *file)
715 {
716 struct video_device *vdev = video_devdata(file);
717 struct s5p_mfc_dev *dev = video_drvdata(file);
718 struct s5p_mfc_ctx *ctx = NULL;
719 struct vb2_queue *q;
720 int ret = 0;
721
722 mfc_debug_enter();
723 if (mutex_lock_interruptible(&dev->mfc_mutex))
724 return -ERESTARTSYS;
725 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
726 /* Allocate memory for context */
727 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
728 if (!ctx) {
729 mfc_err("Not enough memory\n");
730 ret = -ENOMEM;
731 goto err_alloc;
732 }
733 v4l2_fh_init(&ctx->fh, vdev);
734 file->private_data = &ctx->fh;
735 v4l2_fh_add(&ctx->fh);
736 ctx->dev = dev;
737 INIT_LIST_HEAD(&ctx->src_queue);
738 INIT_LIST_HEAD(&ctx->dst_queue);
739 ctx->src_queue_cnt = 0;
740 ctx->dst_queue_cnt = 0;
741 /* Get context number */
742 ctx->num = 0;
743 while (dev->ctx[ctx->num]) {
744 ctx->num++;
745 if (ctx->num >= MFC_NUM_CONTEXTS) {
746 mfc_err("Too many open contexts\n");
747 ret = -EBUSY;
748 goto err_no_ctx;
749 }
750 }
751 /* Mark context as idle */
752 clear_work_bit_irqsave(ctx);
753 dev->ctx[ctx->num] = ctx;
754 if (vdev == dev->vfd_dec) {
755 ctx->type = MFCINST_DECODER;
756 ctx->c_ops = get_dec_codec_ops();
757 s5p_mfc_dec_init(ctx);
758 /* Setup ctrl handler */
759 ret = s5p_mfc_dec_ctrls_setup(ctx);
760 if (ret) {
761 mfc_err("Failed to setup mfc controls\n");
762 goto err_ctrls_setup;
763 }
764 } else if (vdev == dev->vfd_enc) {
765 ctx->type = MFCINST_ENCODER;
766 ctx->c_ops = get_enc_codec_ops();
767 /* only for encoder */
768 INIT_LIST_HEAD(&ctx->ref_queue);
769 ctx->ref_queue_cnt = 0;
770 s5p_mfc_enc_init(ctx);
771 /* Setup ctrl handler */
772 ret = s5p_mfc_enc_ctrls_setup(ctx);
773 if (ret) {
774 mfc_err("Failed to setup mfc controls\n");
775 goto err_ctrls_setup;
776 }
777 } else {
778 ret = -ENOENT;
779 goto err_bad_node;
780 }
781 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
782 ctx->inst_no = MFC_NO_INSTANCE_SET;
783 /* Load firmware if this is the first instance */
784 if (dev->num_inst == 1) {
785 dev->watchdog_timer.expires = jiffies +
786 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
787 add_timer(&dev->watchdog_timer);
788 ret = s5p_mfc_power_on();
789 if (ret < 0) {
790 mfc_err("power on failed\n");
791 goto err_pwr_enable;
792 }
793 s5p_mfc_clock_on();
794 ret = s5p_mfc_load_firmware(dev);
795 if (ret) {
796 s5p_mfc_clock_off();
797 goto err_load_fw;
798 }
799 /* Init the FW */
800 ret = s5p_mfc_init_hw(dev);
801 s5p_mfc_clock_off();
802 if (ret)
803 goto err_init_hw;
804 }
805 /* Init videobuf2 queue for CAPTURE */
806 q = &ctx->vq_dst;
807 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
808 q->drv_priv = &ctx->fh;
809 if (vdev == dev->vfd_dec) {
810 q->io_modes = VB2_MMAP;
811 q->ops = get_dec_queue_ops();
812 } else if (vdev == dev->vfd_enc) {
813 q->io_modes = VB2_MMAP | VB2_USERPTR;
814 q->ops = get_enc_queue_ops();
815 } else {
816 ret = -ENOENT;
817 goto err_queue_init;
818 }
819 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
820 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
821 ret = vb2_queue_init(q);
822 if (ret) {
823 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
824 goto err_queue_init;
825 }
826 /* Init videobuf2 queue for OUTPUT */
827 q = &ctx->vq_src;
828 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
829 q->io_modes = VB2_MMAP;
830 q->drv_priv = &ctx->fh;
831 if (vdev == dev->vfd_dec) {
832 q->io_modes = VB2_MMAP;
833 q->ops = get_dec_queue_ops();
834 } else if (vdev == dev->vfd_enc) {
835 q->io_modes = VB2_MMAP | VB2_USERPTR;
836 q->ops = get_enc_queue_ops();
837 } else {
838 ret = -ENOENT;
839 goto err_queue_init;
840 }
841 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
842 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
843 ret = vb2_queue_init(q);
844 if (ret) {
845 mfc_err("Failed to initialize videobuf2 queue(output)\n");
846 goto err_queue_init;
847 }
848 init_waitqueue_head(&ctx->queue);
849 mutex_unlock(&dev->mfc_mutex);
850 mfc_debug_leave();
851 return ret;
852 /* Deinit when failure occurred */
853 err_queue_init:
854 if (dev->num_inst == 1)
855 s5p_mfc_deinit_hw(dev);
856 err_init_hw:
857 err_load_fw:
858 err_pwr_enable:
859 if (dev->num_inst == 1) {
860 if (s5p_mfc_power_off() < 0)
861 mfc_err("power off failed\n");
862 del_timer_sync(&dev->watchdog_timer);
863 }
864 err_ctrls_setup:
865 s5p_mfc_dec_ctrls_delete(ctx);
866 err_bad_node:
867 dev->ctx[ctx->num] = NULL;
868 err_no_ctx:
869 v4l2_fh_del(&ctx->fh);
870 v4l2_fh_exit(&ctx->fh);
871 kfree(ctx);
872 err_alloc:
873 dev->num_inst--;
874 mutex_unlock(&dev->mfc_mutex);
875 mfc_debug_leave();
876 return ret;
877 }
878
879 /* Release MFC context */
s5p_mfc_release(struct file * file)880 static int s5p_mfc_release(struct file *file)
881 {
882 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
883 struct s5p_mfc_dev *dev = ctx->dev;
884
885 mfc_debug_enter();
886 mutex_lock(&dev->mfc_mutex);
887 s5p_mfc_clock_on();
888 vb2_queue_release(&ctx->vq_src);
889 vb2_queue_release(&ctx->vq_dst);
890 /* Mark context as idle */
891 clear_work_bit_irqsave(ctx);
892 /* If instance was initialised and not yet freed,
893 * return instance and free resources */
894 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
895 mfc_debug(2, "Has to free instance\n");
896 s5p_mfc_close_mfc_inst(dev, ctx);
897 }
898 /* hardware locking scheme */
899 if (dev->curr_ctx == ctx->num)
900 clear_bit(0, &dev->hw_lock);
901 dev->num_inst--;
902 if (dev->num_inst == 0) {
903 mfc_debug(2, "Last instance\n");
904 s5p_mfc_deinit_hw(dev);
905 del_timer_sync(&dev->watchdog_timer);
906 if (s5p_mfc_power_off() < 0)
907 mfc_err("Power off failed\n");
908 }
909 mfc_debug(2, "Shutting down clock\n");
910 s5p_mfc_clock_off();
911 dev->ctx[ctx->num] = NULL;
912 s5p_mfc_dec_ctrls_delete(ctx);
913 v4l2_fh_del(&ctx->fh);
914 v4l2_fh_exit(&ctx->fh);
915 kfree(ctx);
916 mfc_debug_leave();
917 mutex_unlock(&dev->mfc_mutex);
918 return 0;
919 }
920
921 /* Poll */
s5p_mfc_poll(struct file * file,struct poll_table_struct * wait)922 static unsigned int s5p_mfc_poll(struct file *file,
923 struct poll_table_struct *wait)
924 {
925 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
926 struct s5p_mfc_dev *dev = ctx->dev;
927 struct vb2_queue *src_q, *dst_q;
928 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
929 unsigned int rc = 0;
930 unsigned long flags;
931
932 mutex_lock(&dev->mfc_mutex);
933 src_q = &ctx->vq_src;
934 dst_q = &ctx->vq_dst;
935 /*
936 * There has to be at least one buffer queued on each queued_list, which
937 * means either in driver already or waiting for driver to claim it
938 * and start processing.
939 */
940 if ((!src_q->streaming || list_empty(&src_q->queued_list))
941 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
942 rc = POLLERR;
943 goto end;
944 }
945 mutex_unlock(&dev->mfc_mutex);
946 poll_wait(file, &ctx->fh.wait, wait);
947 poll_wait(file, &src_q->done_wq, wait);
948 poll_wait(file, &dst_q->done_wq, wait);
949 mutex_lock(&dev->mfc_mutex);
950 if (v4l2_event_pending(&ctx->fh))
951 rc |= POLLPRI;
952 spin_lock_irqsave(&src_q->done_lock, flags);
953 if (!list_empty(&src_q->done_list))
954 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
955 done_entry);
956 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
957 || src_vb->state == VB2_BUF_STATE_ERROR))
958 rc |= POLLOUT | POLLWRNORM;
959 spin_unlock_irqrestore(&src_q->done_lock, flags);
960 spin_lock_irqsave(&dst_q->done_lock, flags);
961 if (!list_empty(&dst_q->done_list))
962 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
963 done_entry);
964 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
965 || dst_vb->state == VB2_BUF_STATE_ERROR))
966 rc |= POLLIN | POLLRDNORM;
967 spin_unlock_irqrestore(&dst_q->done_lock, flags);
968 end:
969 mutex_unlock(&dev->mfc_mutex);
970 return rc;
971 }
972
973 /* Mmap */
s5p_mfc_mmap(struct file * file,struct vm_area_struct * vma)974 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
975 {
976 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
977 struct s5p_mfc_dev *dev = ctx->dev;
978 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
979 int ret;
980
981 if (mutex_lock_interruptible(&dev->mfc_mutex))
982 return -ERESTARTSYS;
983 if (offset < DST_QUEUE_OFF_BASE) {
984 mfc_debug(2, "mmaping source\n");
985 ret = vb2_mmap(&ctx->vq_src, vma);
986 } else { /* capture */
987 mfc_debug(2, "mmaping destination\n");
988 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
989 ret = vb2_mmap(&ctx->vq_dst, vma);
990 }
991 mutex_unlock(&dev->mfc_mutex);
992 return ret;
993 }
994
995 /* v4l2 ops */
996 static const struct v4l2_file_operations s5p_mfc_fops = {
997 .owner = THIS_MODULE,
998 .open = s5p_mfc_open,
999 .release = s5p_mfc_release,
1000 .poll = s5p_mfc_poll,
1001 .unlocked_ioctl = video_ioctl2,
1002 .mmap = s5p_mfc_mmap,
1003 };
1004
match_child(struct device * dev,void * data)1005 static int match_child(struct device *dev, void *data)
1006 {
1007 if (!dev_name(dev))
1008 return 0;
1009 return !strcmp(dev_name(dev), (char *)data);
1010 }
1011
s5p_mfc_memdev_release(struct device * dev)1012 static void s5p_mfc_memdev_release(struct device *dev)
1013 {
1014 dma_release_declared_memory(dev);
1015 }
1016
1017 static void *mfc_get_drv_data(struct platform_device *pdev);
1018
s5p_mfc_alloc_memdevs(struct s5p_mfc_dev * dev)1019 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1020 {
1021 unsigned int mem_info[2] = { };
1022
1023 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1024 sizeof(struct device), GFP_KERNEL);
1025 if (!dev->mem_dev_l) {
1026 mfc_err("Not enough memory\n");
1027 return -ENOMEM;
1028 }
1029
1030 dev_set_name(dev->mem_dev_l, "%s", "s5p-mfc-l");
1031 dev->mem_dev_l->release = s5p_mfc_memdev_release;
1032 device_initialize(dev->mem_dev_l);
1033 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1034 "samsung,mfc-l", mem_info, 2);
1035 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1036 mem_info[0], mem_info[1],
1037 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1038 mfc_err("Failed to declare coherent memory for\n"
1039 "MFC device\n");
1040 return -ENOMEM;
1041 }
1042
1043 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1044 sizeof(struct device), GFP_KERNEL);
1045 if (!dev->mem_dev_r) {
1046 mfc_err("Not enough memory\n");
1047 return -ENOMEM;
1048 }
1049
1050 dev_set_name(dev->mem_dev_r, "%s", "s5p-mfc-r");
1051 dev->mem_dev_r->release = s5p_mfc_memdev_release;
1052 device_initialize(dev->mem_dev_r);
1053 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1054 "samsung,mfc-r", mem_info, 2);
1055 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1056 mem_info[0], mem_info[1],
1057 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1058 pr_err("Failed to declare coherent memory for\n"
1059 "MFC device\n");
1060 return -ENOMEM;
1061 }
1062 return 0;
1063 }
1064
1065 /* MFC probe function */
s5p_mfc_probe(struct platform_device * pdev)1066 static int s5p_mfc_probe(struct platform_device *pdev)
1067 {
1068 struct s5p_mfc_dev *dev;
1069 struct video_device *vfd;
1070 struct resource *res;
1071 int ret;
1072
1073 pr_debug("%s++\n", __func__);
1074 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1075 if (!dev) {
1076 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1077 return -ENOMEM;
1078 }
1079
1080 spin_lock_init(&dev->irqlock);
1081 spin_lock_init(&dev->condlock);
1082 dev->plat_dev = pdev;
1083 if (!dev->plat_dev) {
1084 dev_err(&pdev->dev, "No platform data specified\n");
1085 return -ENODEV;
1086 }
1087
1088 dev->variant = mfc_get_drv_data(pdev);
1089
1090 ret = s5p_mfc_init_pm(dev);
1091 if (ret < 0) {
1092 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1093 return ret;
1094 }
1095
1096 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1097
1098 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1099 if (IS_ERR(dev->regs_base))
1100 return PTR_ERR(dev->regs_base);
1101
1102 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1103 if (res == NULL) {
1104 dev_err(&pdev->dev, "failed to get irq resource\n");
1105 ret = -ENOENT;
1106 goto err_res;
1107 }
1108 dev->irq = res->start;
1109 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1110 0, pdev->name, dev);
1111 if (ret) {
1112 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1113 goto err_res;
1114 }
1115
1116 if (pdev->dev.of_node) {
1117 ret = s5p_mfc_alloc_memdevs(dev);
1118 if (ret < 0)
1119 goto err_res;
1120 } else {
1121 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1122 "s5p-mfc-l", match_child);
1123 if (!dev->mem_dev_l) {
1124 mfc_err("Mem child (L) device get failed\n");
1125 ret = -ENODEV;
1126 goto err_res;
1127 }
1128 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1129 "s5p-mfc-r", match_child);
1130 if (!dev->mem_dev_r) {
1131 mfc_err("Mem child (R) device get failed\n");
1132 ret = -ENODEV;
1133 goto err_res;
1134 }
1135 }
1136
1137 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1138 if (IS_ERR(dev->alloc_ctx[0])) {
1139 ret = PTR_ERR(dev->alloc_ctx[0]);
1140 goto err_res;
1141 }
1142 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1143 if (IS_ERR(dev->alloc_ctx[1])) {
1144 ret = PTR_ERR(dev->alloc_ctx[1]);
1145 goto err_mem_init_ctx_1;
1146 }
1147
1148 mutex_init(&dev->mfc_mutex);
1149
1150 ret = s5p_mfc_alloc_firmware(dev);
1151 if (ret)
1152 goto err_alloc_fw;
1153
1154 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1155 if (ret)
1156 goto err_v4l2_dev_reg;
1157 init_waitqueue_head(&dev->queue);
1158
1159 /* decoder */
1160 vfd = video_device_alloc();
1161 if (!vfd) {
1162 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1163 ret = -ENOMEM;
1164 goto err_dec_alloc;
1165 }
1166 vfd->fops = &s5p_mfc_fops;
1167 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1168 vfd->release = video_device_release;
1169 vfd->lock = &dev->mfc_mutex;
1170 vfd->v4l2_dev = &dev->v4l2_dev;
1171 vfd->vfl_dir = VFL_DIR_M2M;
1172 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1173 dev->vfd_dec = vfd;
1174 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1175 if (ret) {
1176 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1177 video_device_release(vfd);
1178 goto err_dec_reg;
1179 }
1180 v4l2_info(&dev->v4l2_dev,
1181 "decoder registered as /dev/video%d\n", vfd->num);
1182 video_set_drvdata(vfd, dev);
1183
1184 /* encoder */
1185 vfd = video_device_alloc();
1186 if (!vfd) {
1187 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1188 ret = -ENOMEM;
1189 goto err_enc_alloc;
1190 }
1191 vfd->fops = &s5p_mfc_fops;
1192 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1193 vfd->release = video_device_release;
1194 vfd->lock = &dev->mfc_mutex;
1195 vfd->v4l2_dev = &dev->v4l2_dev;
1196 vfd->vfl_dir = VFL_DIR_M2M;
1197 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1198 dev->vfd_enc = vfd;
1199 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1200 if (ret) {
1201 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1202 video_device_release(vfd);
1203 goto err_enc_reg;
1204 }
1205 v4l2_info(&dev->v4l2_dev,
1206 "encoder registered as /dev/video%d\n", vfd->num);
1207 video_set_drvdata(vfd, dev);
1208 platform_set_drvdata(pdev, dev);
1209
1210 dev->hw_lock = 0;
1211 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1212 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1213 atomic_set(&dev->watchdog_cnt, 0);
1214 init_timer(&dev->watchdog_timer);
1215 dev->watchdog_timer.data = (unsigned long)dev;
1216 dev->watchdog_timer.function = s5p_mfc_watchdog;
1217
1218 /* Initialize HW ops and commands based on MFC version */
1219 s5p_mfc_init_hw_ops(dev);
1220 s5p_mfc_init_hw_cmds(dev);
1221 s5p_mfc_init_regs(dev);
1222
1223 pr_debug("%s--\n", __func__);
1224 return 0;
1225
1226 /* Deinit MFC if probe had failed */
1227 err_enc_reg:
1228 video_device_release(dev->vfd_enc);
1229 err_enc_alloc:
1230 video_unregister_device(dev->vfd_dec);
1231 err_dec_reg:
1232 video_device_release(dev->vfd_dec);
1233 err_dec_alloc:
1234 v4l2_device_unregister(&dev->v4l2_dev);
1235 err_v4l2_dev_reg:
1236 s5p_mfc_release_firmware(dev);
1237 err_alloc_fw:
1238 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1239 err_mem_init_ctx_1:
1240 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1241 err_res:
1242 s5p_mfc_final_pm(dev);
1243
1244 pr_debug("%s-- with error\n", __func__);
1245 return ret;
1246
1247 }
1248
1249 /* Remove the driver */
s5p_mfc_remove(struct platform_device * pdev)1250 static int s5p_mfc_remove(struct platform_device *pdev)
1251 {
1252 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1253
1254 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1255
1256 del_timer_sync(&dev->watchdog_timer);
1257 flush_workqueue(dev->watchdog_workqueue);
1258 destroy_workqueue(dev->watchdog_workqueue);
1259
1260 video_unregister_device(dev->vfd_enc);
1261 video_unregister_device(dev->vfd_dec);
1262 v4l2_device_unregister(&dev->v4l2_dev);
1263 s5p_mfc_release_firmware(dev);
1264 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1265 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1266 if (pdev->dev.of_node) {
1267 put_device(dev->mem_dev_l);
1268 put_device(dev->mem_dev_r);
1269 }
1270
1271 s5p_mfc_final_pm(dev);
1272 return 0;
1273 }
1274
1275 #ifdef CONFIG_PM_SLEEP
1276
s5p_mfc_suspend(struct device * dev)1277 static int s5p_mfc_suspend(struct device *dev)
1278 {
1279 struct platform_device *pdev = to_platform_device(dev);
1280 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1281 int ret;
1282
1283 if (m_dev->num_inst == 0)
1284 return 0;
1285
1286 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1287 mfc_err("Error: going to suspend for a second time\n");
1288 return -EIO;
1289 }
1290
1291 /* Check if we're processing then wait if it necessary. */
1292 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1293 /* Try and lock the HW */
1294 /* Wait on the interrupt waitqueue */
1295 ret = wait_event_interruptible_timeout(m_dev->queue,
1296 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1297 if (ret == 0) {
1298 mfc_err("Waiting for hardware to finish timed out\n");
1299 return -EIO;
1300 }
1301 }
1302
1303 return s5p_mfc_sleep(m_dev);
1304 }
1305
s5p_mfc_resume(struct device * dev)1306 static int s5p_mfc_resume(struct device *dev)
1307 {
1308 struct platform_device *pdev = to_platform_device(dev);
1309 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1310
1311 if (m_dev->num_inst == 0)
1312 return 0;
1313 return s5p_mfc_wakeup(m_dev);
1314 }
1315 #endif
1316
1317 #ifdef CONFIG_PM_RUNTIME
s5p_mfc_runtime_suspend(struct device * dev)1318 static int s5p_mfc_runtime_suspend(struct device *dev)
1319 {
1320 struct platform_device *pdev = to_platform_device(dev);
1321 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1322
1323 atomic_set(&m_dev->pm.power, 0);
1324 return 0;
1325 }
1326
s5p_mfc_runtime_resume(struct device * dev)1327 static int s5p_mfc_runtime_resume(struct device *dev)
1328 {
1329 struct platform_device *pdev = to_platform_device(dev);
1330 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1331
1332 if (!m_dev->alloc_ctx)
1333 return 0;
1334 atomic_set(&m_dev->pm.power, 1);
1335 return 0;
1336 }
1337 #endif
1338
1339 /* Power management */
1340 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1341 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1342 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1343 NULL)
1344 };
1345
1346 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1347 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1348 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1349 .dsc = DESC_BUF_SIZE,
1350 .shm = SHARED_BUF_SIZE,
1351 };
1352
1353 static struct s5p_mfc_buf_size buf_size_v5 = {
1354 .fw = MAX_FW_SIZE,
1355 .cpb = MAX_CPB_SIZE,
1356 .priv = &mfc_buf_size_v5,
1357 };
1358
1359 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1360 .base = MFC_BASE_ALIGN_ORDER,
1361 };
1362
1363 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1364 .version = MFC_VERSION,
1365 .version_bit = MFC_V5_BIT,
1366 .port_num = MFC_NUM_PORTS,
1367 .buf_size = &buf_size_v5,
1368 .buf_align = &mfc_buf_align_v5,
1369 .fw_name[0] = "s5p-mfc.fw",
1370 };
1371
1372 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1373 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1374 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1375 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1376 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1377 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1378 };
1379
1380 static struct s5p_mfc_buf_size buf_size_v6 = {
1381 .fw = MAX_FW_SIZE_V6,
1382 .cpb = MAX_CPB_SIZE_V6,
1383 .priv = &mfc_buf_size_v6,
1384 };
1385
1386 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1387 .base = 0,
1388 };
1389
1390 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1391 .version = MFC_VERSION_V6,
1392 .version_bit = MFC_V6_BIT,
1393 .port_num = MFC_NUM_PORTS_V6,
1394 .buf_size = &buf_size_v6,
1395 .buf_align = &mfc_buf_align_v6,
1396 .fw_name[0] = "s5p-mfc-v6.fw",
1397 /*
1398 * v6-v2 firmware contains bug fixes and interface change
1399 * for init buffer command
1400 */
1401 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1402 };
1403
1404 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1405 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1406 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1407 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1408 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1409 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1410 };
1411
1412 static struct s5p_mfc_buf_size buf_size_v7 = {
1413 .fw = MAX_FW_SIZE_V7,
1414 .cpb = MAX_CPB_SIZE_V7,
1415 .priv = &mfc_buf_size_v7,
1416 };
1417
1418 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1419 .base = 0,
1420 };
1421
1422 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1423 .version = MFC_VERSION_V7,
1424 .version_bit = MFC_V7_BIT,
1425 .port_num = MFC_NUM_PORTS_V7,
1426 .buf_size = &buf_size_v7,
1427 .buf_align = &mfc_buf_align_v7,
1428 .fw_name[0] = "s5p-mfc-v7.fw",
1429 };
1430
1431 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1432 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1433 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1434 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1435 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1436 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1437 };
1438
1439 static struct s5p_mfc_buf_size buf_size_v8 = {
1440 .fw = MAX_FW_SIZE_V8,
1441 .cpb = MAX_CPB_SIZE_V8,
1442 .priv = &mfc_buf_size_v8,
1443 };
1444
1445 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1446 .base = 0,
1447 };
1448
1449 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1450 .version = MFC_VERSION_V8,
1451 .version_bit = MFC_V8_BIT,
1452 .port_num = MFC_NUM_PORTS_V8,
1453 .buf_size = &buf_size_v8,
1454 .buf_align = &mfc_buf_align_v8,
1455 .fw_name[0] = "s5p-mfc-v8.fw",
1456 };
1457
1458 static struct platform_device_id mfc_driver_ids[] = {
1459 {
1460 .name = "s5p-mfc",
1461 .driver_data = (unsigned long)&mfc_drvdata_v5,
1462 }, {
1463 .name = "s5p-mfc-v5",
1464 .driver_data = (unsigned long)&mfc_drvdata_v5,
1465 }, {
1466 .name = "s5p-mfc-v6",
1467 .driver_data = (unsigned long)&mfc_drvdata_v6,
1468 }, {
1469 .name = "s5p-mfc-v7",
1470 .driver_data = (unsigned long)&mfc_drvdata_v7,
1471 }, {
1472 .name = "s5p-mfc-v8",
1473 .driver_data = (unsigned long)&mfc_drvdata_v8,
1474 },
1475 {},
1476 };
1477 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1478
1479 static const struct of_device_id exynos_mfc_match[] = {
1480 {
1481 .compatible = "samsung,mfc-v5",
1482 .data = &mfc_drvdata_v5,
1483 }, {
1484 .compatible = "samsung,mfc-v6",
1485 .data = &mfc_drvdata_v6,
1486 }, {
1487 .compatible = "samsung,mfc-v7",
1488 .data = &mfc_drvdata_v7,
1489 }, {
1490 .compatible = "samsung,mfc-v8",
1491 .data = &mfc_drvdata_v8,
1492 },
1493 {},
1494 };
1495 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1496
mfc_get_drv_data(struct platform_device * pdev)1497 static void *mfc_get_drv_data(struct platform_device *pdev)
1498 {
1499 struct s5p_mfc_variant *driver_data = NULL;
1500
1501 if (pdev->dev.of_node) {
1502 const struct of_device_id *match;
1503 match = of_match_node(exynos_mfc_match,
1504 pdev->dev.of_node);
1505 if (match)
1506 driver_data = (struct s5p_mfc_variant *)match->data;
1507 } else {
1508 driver_data = (struct s5p_mfc_variant *)
1509 platform_get_device_id(pdev)->driver_data;
1510 }
1511 return driver_data;
1512 }
1513
1514 static struct platform_driver s5p_mfc_driver = {
1515 .probe = s5p_mfc_probe,
1516 .remove = s5p_mfc_remove,
1517 .id_table = mfc_driver_ids,
1518 .driver = {
1519 .name = S5P_MFC_NAME,
1520 .owner = THIS_MODULE,
1521 .pm = &s5p_mfc_pm_ops,
1522 .of_match_table = exynos_mfc_match,
1523 },
1524 };
1525
1526 module_platform_driver(s5p_mfc_driver);
1527
1528 MODULE_LICENSE("GPL");
1529 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1530 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1531
1532