1 /*
2 * sh73a0 processor support
3 *
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
29 #include <linux/i2c/i2c-sh_mobile.h>
30 #include <linux/io.h>
31 #include <linux/serial_sci.h>
32 #include <linux/sh_dma.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
36
37 #include <asm/mach-types.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41
42 #include "common.h"
43 #include "dma-register.h"
44 #include "intc.h"
45 #include "irqs.h"
46 #include "sh73a0.h"
47
48 static struct map_desc sh73a0_io_desc[] __initdata = {
49 /* create a 1:1 entity map for 0xe6xxxxxx
50 * used by CPGA, INTC and PFC.
51 */
52 {
53 .virtual = 0xe6000000,
54 .pfn = __phys_to_pfn(0xe6000000),
55 .length = 256 << 20,
56 .type = MT_DEVICE_NONSHARED
57 },
58 };
59
sh73a0_map_io(void)60 void __init sh73a0_map_io(void)
61 {
62 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
63 }
64
65 /* PFC */
66 static struct resource pfc_resources[] __initdata = {
67 DEFINE_RES_MEM(0xe6050000, 0x8000),
68 DEFINE_RES_MEM(0xe605801c, 0x000c),
69 };
70
sh73a0_pinmux_init(void)71 void __init sh73a0_pinmux_init(void)
72 {
73 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
74 ARRAY_SIZE(pfc_resources));
75 }
76
77 /* SCIF */
78 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
79 static struct plat_sci_port scif##index##_platform_data = { \
80 .type = scif_type, \
81 .flags = UPF_BOOT_AUTOCONF, \
82 .scscr = SCSCR_RE | SCSCR_TE, \
83 }; \
84 \
85 static struct resource scif##index##_resources[] = { \
86 DEFINE_RES_MEM(baseaddr, 0x100), \
87 DEFINE_RES_IRQ(irq), \
88 }; \
89 \
90 static struct platform_device scif##index##_device = { \
91 .name = "sh-sci", \
92 .id = index, \
93 .resource = scif##index##_resources, \
94 .num_resources = ARRAY_SIZE(scif##index##_resources), \
95 .dev = { \
96 .platform_data = &scif##index##_platform_data, \
97 }, \
98 }
99
100 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
101 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
102 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
103 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
104 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
105 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
106 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
107 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
108 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
109
110 static struct sh_timer_config cmt1_platform_data = {
111 .channels_mask = 0x3f,
112 };
113
114 static struct resource cmt1_resources[] = {
115 DEFINE_RES_MEM(0xe6138000, 0x200),
116 DEFINE_RES_IRQ(gic_spi(65)),
117 };
118
119 static struct platform_device cmt1_device = {
120 .name = "sh-cmt-48",
121 .id = 1,
122 .dev = {
123 .platform_data = &cmt1_platform_data,
124 },
125 .resource = cmt1_resources,
126 .num_resources = ARRAY_SIZE(cmt1_resources),
127 };
128
129 /* TMU */
130 static struct sh_timer_config tmu0_platform_data = {
131 .channels_mask = 7,
132 };
133
134 static struct resource tmu0_resources[] = {
135 DEFINE_RES_MEM(0xfff60000, 0x2c),
136 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
137 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
138 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
139 };
140
141 static struct platform_device tmu0_device = {
142 .name = "sh-tmu",
143 .id = 0,
144 .dev = {
145 .platform_data = &tmu0_platform_data,
146 },
147 .resource = tmu0_resources,
148 .num_resources = ARRAY_SIZE(tmu0_resources),
149 };
150
151 static struct resource i2c0_resources[] = {
152 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
153 [1] = {
154 .start = gic_spi(167),
155 .end = gic_spi(170),
156 .flags = IORESOURCE_IRQ,
157 },
158 };
159
160 static struct resource i2c1_resources[] = {
161 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
162 [1] = {
163 .start = gic_spi(51),
164 .end = gic_spi(54),
165 .flags = IORESOURCE_IRQ,
166 },
167 };
168
169 static struct resource i2c2_resources[] = {
170 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
171 [1] = {
172 .start = gic_spi(171),
173 .end = gic_spi(174),
174 .flags = IORESOURCE_IRQ,
175 },
176 };
177
178 static struct resource i2c3_resources[] = {
179 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
180 [1] = {
181 .start = gic_spi(183),
182 .end = gic_spi(186),
183 .flags = IORESOURCE_IRQ,
184 },
185 };
186
187 static struct resource i2c4_resources[] = {
188 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
189 [1] = {
190 .start = gic_spi(187),
191 .end = gic_spi(190),
192 .flags = IORESOURCE_IRQ,
193 },
194 };
195
196 static struct i2c_sh_mobile_platform_data i2c_platform_data = {
197 .clks_per_count = 2,
198 };
199
200 static struct platform_device i2c0_device = {
201 .name = "i2c-sh_mobile",
202 .id = 0,
203 .resource = i2c0_resources,
204 .num_resources = ARRAY_SIZE(i2c0_resources),
205 .dev = {
206 .platform_data = &i2c_platform_data,
207 },
208 };
209
210 static struct platform_device i2c1_device = {
211 .name = "i2c-sh_mobile",
212 .id = 1,
213 .resource = i2c1_resources,
214 .num_resources = ARRAY_SIZE(i2c1_resources),
215 .dev = {
216 .platform_data = &i2c_platform_data,
217 },
218 };
219
220 static struct platform_device i2c2_device = {
221 .name = "i2c-sh_mobile",
222 .id = 2,
223 .resource = i2c2_resources,
224 .num_resources = ARRAY_SIZE(i2c2_resources),
225 .dev = {
226 .platform_data = &i2c_platform_data,
227 },
228 };
229
230 static struct platform_device i2c3_device = {
231 .name = "i2c-sh_mobile",
232 .id = 3,
233 .resource = i2c3_resources,
234 .num_resources = ARRAY_SIZE(i2c3_resources),
235 .dev = {
236 .platform_data = &i2c_platform_data,
237 },
238 };
239
240 static struct platform_device i2c4_device = {
241 .name = "i2c-sh_mobile",
242 .id = 4,
243 .resource = i2c4_resources,
244 .num_resources = ARRAY_SIZE(i2c4_resources),
245 .dev = {
246 .platform_data = &i2c_platform_data,
247 },
248 };
249
250 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
251 {
252 .slave_id = SHDMA_SLAVE_SCIF0_TX,
253 .addr = 0xe6c40020,
254 .chcr = CHCR_TX(XMIT_SZ_8BIT),
255 .mid_rid = 0x21,
256 }, {
257 .slave_id = SHDMA_SLAVE_SCIF0_RX,
258 .addr = 0xe6c40024,
259 .chcr = CHCR_RX(XMIT_SZ_8BIT),
260 .mid_rid = 0x22,
261 }, {
262 .slave_id = SHDMA_SLAVE_SCIF1_TX,
263 .addr = 0xe6c50020,
264 .chcr = CHCR_TX(XMIT_SZ_8BIT),
265 .mid_rid = 0x25,
266 }, {
267 .slave_id = SHDMA_SLAVE_SCIF1_RX,
268 .addr = 0xe6c50024,
269 .chcr = CHCR_RX(XMIT_SZ_8BIT),
270 .mid_rid = 0x26,
271 }, {
272 .slave_id = SHDMA_SLAVE_SCIF2_TX,
273 .addr = 0xe6c60020,
274 .chcr = CHCR_TX(XMIT_SZ_8BIT),
275 .mid_rid = 0x29,
276 }, {
277 .slave_id = SHDMA_SLAVE_SCIF2_RX,
278 .addr = 0xe6c60024,
279 .chcr = CHCR_RX(XMIT_SZ_8BIT),
280 .mid_rid = 0x2a,
281 }, {
282 .slave_id = SHDMA_SLAVE_SCIF3_TX,
283 .addr = 0xe6c70020,
284 .chcr = CHCR_TX(XMIT_SZ_8BIT),
285 .mid_rid = 0x2d,
286 }, {
287 .slave_id = SHDMA_SLAVE_SCIF3_RX,
288 .addr = 0xe6c70024,
289 .chcr = CHCR_RX(XMIT_SZ_8BIT),
290 .mid_rid = 0x2e,
291 }, {
292 .slave_id = SHDMA_SLAVE_SCIF4_TX,
293 .addr = 0xe6c80020,
294 .chcr = CHCR_TX(XMIT_SZ_8BIT),
295 .mid_rid = 0x39,
296 }, {
297 .slave_id = SHDMA_SLAVE_SCIF4_RX,
298 .addr = 0xe6c80024,
299 .chcr = CHCR_RX(XMIT_SZ_8BIT),
300 .mid_rid = 0x3a,
301 }, {
302 .slave_id = SHDMA_SLAVE_SCIF5_TX,
303 .addr = 0xe6cb0020,
304 .chcr = CHCR_TX(XMIT_SZ_8BIT),
305 .mid_rid = 0x35,
306 }, {
307 .slave_id = SHDMA_SLAVE_SCIF5_RX,
308 .addr = 0xe6cb0024,
309 .chcr = CHCR_RX(XMIT_SZ_8BIT),
310 .mid_rid = 0x36,
311 }, {
312 .slave_id = SHDMA_SLAVE_SCIF6_TX,
313 .addr = 0xe6cc0020,
314 .chcr = CHCR_TX(XMIT_SZ_8BIT),
315 .mid_rid = 0x1d,
316 }, {
317 .slave_id = SHDMA_SLAVE_SCIF6_RX,
318 .addr = 0xe6cc0024,
319 .chcr = CHCR_RX(XMIT_SZ_8BIT),
320 .mid_rid = 0x1e,
321 }, {
322 .slave_id = SHDMA_SLAVE_SCIF7_TX,
323 .addr = 0xe6cd0020,
324 .chcr = CHCR_TX(XMIT_SZ_8BIT),
325 .mid_rid = 0x19,
326 }, {
327 .slave_id = SHDMA_SLAVE_SCIF7_RX,
328 .addr = 0xe6cd0024,
329 .chcr = CHCR_RX(XMIT_SZ_8BIT),
330 .mid_rid = 0x1a,
331 }, {
332 .slave_id = SHDMA_SLAVE_SCIF8_TX,
333 .addr = 0xe6c30040,
334 .chcr = CHCR_TX(XMIT_SZ_8BIT),
335 .mid_rid = 0x3d,
336 }, {
337 .slave_id = SHDMA_SLAVE_SCIF8_RX,
338 .addr = 0xe6c30060,
339 .chcr = CHCR_RX(XMIT_SZ_8BIT),
340 .mid_rid = 0x3e,
341 }, {
342 .slave_id = SHDMA_SLAVE_SDHI0_TX,
343 .addr = 0xee100030,
344 .chcr = CHCR_TX(XMIT_SZ_16BIT),
345 .mid_rid = 0xc1,
346 }, {
347 .slave_id = SHDMA_SLAVE_SDHI0_RX,
348 .addr = 0xee100030,
349 .chcr = CHCR_RX(XMIT_SZ_16BIT),
350 .mid_rid = 0xc2,
351 }, {
352 .slave_id = SHDMA_SLAVE_SDHI1_TX,
353 .addr = 0xee120030,
354 .chcr = CHCR_TX(XMIT_SZ_16BIT),
355 .mid_rid = 0xc9,
356 }, {
357 .slave_id = SHDMA_SLAVE_SDHI1_RX,
358 .addr = 0xee120030,
359 .chcr = CHCR_RX(XMIT_SZ_16BIT),
360 .mid_rid = 0xca,
361 }, {
362 .slave_id = SHDMA_SLAVE_SDHI2_TX,
363 .addr = 0xee140030,
364 .chcr = CHCR_TX(XMIT_SZ_16BIT),
365 .mid_rid = 0xcd,
366 }, {
367 .slave_id = SHDMA_SLAVE_SDHI2_RX,
368 .addr = 0xee140030,
369 .chcr = CHCR_RX(XMIT_SZ_16BIT),
370 .mid_rid = 0xce,
371 }, {
372 .slave_id = SHDMA_SLAVE_MMCIF_TX,
373 .addr = 0xe6bd0034,
374 .chcr = CHCR_TX(XMIT_SZ_32BIT),
375 .mid_rid = 0xd1,
376 }, {
377 .slave_id = SHDMA_SLAVE_MMCIF_RX,
378 .addr = 0xe6bd0034,
379 .chcr = CHCR_RX(XMIT_SZ_32BIT),
380 .mid_rid = 0xd2,
381 },
382 };
383
384 #define DMAE_CHANNEL(_offset) \
385 { \
386 .offset = _offset - 0x20, \
387 .dmars = _offset - 0x20 + 0x40, \
388 }
389
390 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
391 DMAE_CHANNEL(0x8000),
392 DMAE_CHANNEL(0x8080),
393 DMAE_CHANNEL(0x8100),
394 DMAE_CHANNEL(0x8180),
395 DMAE_CHANNEL(0x8200),
396 DMAE_CHANNEL(0x8280),
397 DMAE_CHANNEL(0x8300),
398 DMAE_CHANNEL(0x8380),
399 DMAE_CHANNEL(0x8400),
400 DMAE_CHANNEL(0x8480),
401 DMAE_CHANNEL(0x8500),
402 DMAE_CHANNEL(0x8580),
403 DMAE_CHANNEL(0x8600),
404 DMAE_CHANNEL(0x8680),
405 DMAE_CHANNEL(0x8700),
406 DMAE_CHANNEL(0x8780),
407 DMAE_CHANNEL(0x8800),
408 DMAE_CHANNEL(0x8880),
409 DMAE_CHANNEL(0x8900),
410 DMAE_CHANNEL(0x8980),
411 };
412
413 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
414 .slave = sh73a0_dmae_slaves,
415 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
416 .channel = sh73a0_dmae_channels,
417 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
418 .ts_low_shift = TS_LOW_SHIFT,
419 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
420 .ts_high_shift = TS_HI_SHIFT,
421 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
422 .ts_shift = dma_ts_shift,
423 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
424 .dmaor_init = DMAOR_DME,
425 };
426
427 static struct resource sh73a0_dmae_resources[] = {
428 DEFINE_RES_MEM(0xfe000020, 0x89e0),
429 {
430 .name = "error_irq",
431 .start = gic_spi(129),
432 .end = gic_spi(129),
433 .flags = IORESOURCE_IRQ,
434 },
435 {
436 /* IRQ for channels 0-19 */
437 .start = gic_spi(109),
438 .end = gic_spi(128),
439 .flags = IORESOURCE_IRQ,
440 },
441 };
442
443 static struct platform_device dma0_device = {
444 .name = "sh-dma-engine",
445 .id = 0,
446 .resource = sh73a0_dmae_resources,
447 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
448 .dev = {
449 .platform_data = &sh73a0_dmae_platform_data,
450 },
451 };
452
453 /* MPDMAC */
454 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
455 {
456 .slave_id = SHDMA_SLAVE_FSI2A_RX,
457 .addr = 0xec230020,
458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
459 .mid_rid = 0xd6, /* CHECK ME */
460 }, {
461 .slave_id = SHDMA_SLAVE_FSI2A_TX,
462 .addr = 0xec230024,
463 .chcr = CHCR_TX(XMIT_SZ_32BIT),
464 .mid_rid = 0xd5, /* CHECK ME */
465 }, {
466 .slave_id = SHDMA_SLAVE_FSI2C_RX,
467 .addr = 0xec230060,
468 .chcr = CHCR_RX(XMIT_SZ_32BIT),
469 .mid_rid = 0xda, /* CHECK ME */
470 }, {
471 .slave_id = SHDMA_SLAVE_FSI2C_TX,
472 .addr = 0xec230064,
473 .chcr = CHCR_TX(XMIT_SZ_32BIT),
474 .mid_rid = 0xd9, /* CHECK ME */
475 }, {
476 .slave_id = SHDMA_SLAVE_FSI2B_RX,
477 .addr = 0xec240020,
478 .chcr = CHCR_RX(XMIT_SZ_32BIT),
479 .mid_rid = 0x8e, /* CHECK ME */
480 }, {
481 .slave_id = SHDMA_SLAVE_FSI2B_TX,
482 .addr = 0xec240024,
483 .chcr = CHCR_RX(XMIT_SZ_32BIT),
484 .mid_rid = 0x8d, /* CHECK ME */
485 }, {
486 .slave_id = SHDMA_SLAVE_FSI2D_RX,
487 .addr = 0xec240060,
488 .chcr = CHCR_RX(XMIT_SZ_32BIT),
489 .mid_rid = 0x9a, /* CHECK ME */
490 },
491 };
492
493 #define MPDMA_CHANNEL(a, b, c) \
494 { \
495 .offset = a, \
496 .dmars = b, \
497 .dmars_bit = c, \
498 .chclr_offset = (0x220 - 0x20) + a \
499 }
500
501 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
502 MPDMA_CHANNEL(0x00, 0, 0),
503 MPDMA_CHANNEL(0x10, 0, 8),
504 MPDMA_CHANNEL(0x20, 4, 0),
505 MPDMA_CHANNEL(0x30, 4, 8),
506 MPDMA_CHANNEL(0x50, 8, 0),
507 MPDMA_CHANNEL(0x70, 8, 8),
508 };
509
510 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
511 .slave = sh73a0_mpdma_slaves,
512 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
513 .channel = sh73a0_mpdma_channels,
514 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
515 .ts_low_shift = TS_LOW_SHIFT,
516 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
517 .ts_high_shift = TS_HI_SHIFT,
518 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
519 .ts_shift = dma_ts_shift,
520 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
521 .dmaor_init = DMAOR_DME,
522 .chclr_present = 1,
523 };
524
525 /* Resource order important! */
526 static struct resource sh73a0_mpdma_resources[] = {
527 /* Channel registers and DMAOR */
528 DEFINE_RES_MEM(0xec618020, 0x270),
529 /* DMARSx */
530 DEFINE_RES_MEM(0xec619000, 0xc),
531 {
532 .name = "error_irq",
533 .start = gic_spi(181),
534 .end = gic_spi(181),
535 .flags = IORESOURCE_IRQ,
536 },
537 {
538 /* IRQ for channels 0-5 */
539 .start = gic_spi(175),
540 .end = gic_spi(180),
541 .flags = IORESOURCE_IRQ,
542 },
543 };
544
545 static struct platform_device mpdma0_device = {
546 .name = "sh-dma-engine",
547 .id = 1,
548 .resource = sh73a0_mpdma_resources,
549 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
550 .dev = {
551 .platform_data = &sh73a0_mpdma_platform_data,
552 },
553 };
554
555 static struct resource pmu_resources[] = {
556 [0] = {
557 .start = gic_spi(55),
558 .end = gic_spi(55),
559 .flags = IORESOURCE_IRQ,
560 },
561 [1] = {
562 .start = gic_spi(56),
563 .end = gic_spi(56),
564 .flags = IORESOURCE_IRQ,
565 },
566 };
567
568 static struct platform_device pmu_device = {
569 .name = "arm-pmu",
570 .id = -1,
571 .num_resources = ARRAY_SIZE(pmu_resources),
572 .resource = pmu_resources,
573 };
574
575 /* an IPMMU module for ICB */
576 static struct resource ipmmu_resources[] = {
577 DEFINE_RES_MEM(0xfe951000, 0x100),
578 };
579
580 static const char * const ipmmu_dev_names[] = {
581 "sh_mobile_lcdc_fb.0",
582 };
583
584 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
585 .dev_names = ipmmu_dev_names,
586 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
587 };
588
589 static struct platform_device ipmmu_device = {
590 .name = "ipmmu",
591 .id = -1,
592 .dev = {
593 .platform_data = &ipmmu_platform_data,
594 },
595 .resource = ipmmu_resources,
596 .num_resources = ARRAY_SIZE(ipmmu_resources),
597 };
598
599 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
600 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
601 .control_parent = true,
602 };
603
604 static struct resource irqpin0_resources[] = {
605 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
606 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
607 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
608 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
609 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
610 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
611 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
612 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
613 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
614 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
615 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
616 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
617 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
618 };
619
620 static struct platform_device irqpin0_device = {
621 .name = "renesas_intc_irqpin",
622 .id = 0,
623 .resource = irqpin0_resources,
624 .num_resources = ARRAY_SIZE(irqpin0_resources),
625 .dev = {
626 .platform_data = &irqpin0_platform_data,
627 },
628 };
629
630 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
631 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
632 .control_parent = true, /* Disable spurious IRQ10 */
633 };
634
635 static struct resource irqpin1_resources[] = {
636 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
637 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
638 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
639 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
640 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
641 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
642 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
643 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
644 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
645 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
646 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
647 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
648 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
649 };
650
651 static struct platform_device irqpin1_device = {
652 .name = "renesas_intc_irqpin",
653 .id = 1,
654 .resource = irqpin1_resources,
655 .num_resources = ARRAY_SIZE(irqpin1_resources),
656 .dev = {
657 .platform_data = &irqpin1_platform_data,
658 },
659 };
660
661 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
662 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
663 .control_parent = true,
664 };
665
666 static struct resource irqpin2_resources[] = {
667 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
668 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
669 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
670 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
671 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
672 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
673 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
674 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
675 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
676 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
677 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
678 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
679 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
680 };
681
682 static struct platform_device irqpin2_device = {
683 .name = "renesas_intc_irqpin",
684 .id = 2,
685 .resource = irqpin2_resources,
686 .num_resources = ARRAY_SIZE(irqpin2_resources),
687 .dev = {
688 .platform_data = &irqpin2_platform_data,
689 },
690 };
691
692 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
693 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
694 .control_parent = true,
695 };
696
697 static struct resource irqpin3_resources[] = {
698 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
699 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
700 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
701 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
702 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
703 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
704 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
705 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
706 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
707 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
708 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
709 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
710 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
711 };
712
713 static struct platform_device irqpin3_device = {
714 .name = "renesas_intc_irqpin",
715 .id = 3,
716 .resource = irqpin3_resources,
717 .num_resources = ARRAY_SIZE(irqpin3_resources),
718 .dev = {
719 .platform_data = &irqpin3_platform_data,
720 },
721 };
722
723 static struct platform_device *sh73a0_early_devices[] __initdata = {
724 &scif0_device,
725 &scif1_device,
726 &scif2_device,
727 &scif3_device,
728 &scif4_device,
729 &scif5_device,
730 &scif6_device,
731 &scif7_device,
732 &scif8_device,
733 &tmu0_device,
734 &ipmmu_device,
735 &cmt1_device,
736 };
737
738 static struct platform_device *sh73a0_late_devices[] __initdata = {
739 &i2c0_device,
740 &i2c1_device,
741 &i2c2_device,
742 &i2c3_device,
743 &i2c4_device,
744 &dma0_device,
745 &mpdma0_device,
746 &pmu_device,
747 &irqpin0_device,
748 &irqpin1_device,
749 &irqpin2_device,
750 &irqpin3_device,
751 };
752
753 #define SRCR2 IOMEM(0xe61580b0)
754
sh73a0_add_standard_devices(void)755 void __init sh73a0_add_standard_devices(void)
756 {
757 /* Clear software reset bit on SY-DMAC module */
758 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
759
760 platform_add_devices(sh73a0_early_devices,
761 ARRAY_SIZE(sh73a0_early_devices));
762 platform_add_devices(sh73a0_late_devices,
763 ARRAY_SIZE(sh73a0_late_devices));
764 }
765
sh73a0_init_delay(void)766 void __init sh73a0_init_delay(void)
767 {
768 shmobile_init_delay();
769 }
770
771 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
sh73a0_register_twd(void)772 void __init __weak sh73a0_register_twd(void) { }
773
sh73a0_earlytimer_init(void)774 void __init sh73a0_earlytimer_init(void)
775 {
776 sh73a0_init_delay();
777 sh73a0_clock_init();
778 shmobile_earlytimer_init();
779 sh73a0_register_twd();
780 }
781
sh73a0_add_early_devices(void)782 void __init sh73a0_add_early_devices(void)
783 {
784 early_platform_add_devices(sh73a0_early_devices,
785 ARRAY_SIZE(sh73a0_early_devices));
786
787 /* setup early console here as well */
788 shmobile_setup_console();
789 }
790
791 #ifdef CONFIG_USE_OF
792
sh73a0_add_standard_devices_dt(void)793 void __init sh73a0_add_standard_devices_dt(void)
794 {
795 /* clocks are setup late during boot in the case of DT */
796 sh73a0_clock_init();
797
798 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
799 }
800
801 static const char *sh73a0_boards_compat_dt[] __initdata = {
802 "renesas,sh73a0",
803 NULL,
804 };
805
806 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
807 .smp = smp_ops(sh73a0_smp_ops),
808 .map_io = sh73a0_map_io,
809 .init_early = sh73a0_init_delay,
810 .init_machine = sh73a0_add_standard_devices_dt,
811 .init_late = shmobile_init_late,
812 .dt_compat = sh73a0_boards_compat_dt,
813 MACHINE_END
814 #endif /* CONFIG_USE_OF */
815