1 /*
2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 *
16 */
17
18 #include <linux/device.h>
19 #include <linux/kobject.h>
20 #include <linux/kernel.h>
21 #include <linux/platform_device.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/io.h>
25
26 #include <soc/tegra/common.h>
27 #include <soc/tegra/fuse.h>
28
29 #include "fuse.h"
30
31 static u32 (*fuse_readl)(const unsigned int offset);
32 static int fuse_size;
33 struct tegra_sku_info tegra_sku_info;
34
35 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
36 [TEGRA_REVISION_UNKNOWN] = "unknown",
37 [TEGRA_REVISION_A01] = "A01",
38 [TEGRA_REVISION_A02] = "A02",
39 [TEGRA_REVISION_A03] = "A03",
40 [TEGRA_REVISION_A03p] = "A03 prime",
41 [TEGRA_REVISION_A04] = "A04",
42 };
43
fuse_readb(const unsigned int offset)44 static u8 fuse_readb(const unsigned int offset)
45 {
46 u32 val;
47
48 val = fuse_readl(round_down(offset, 4));
49 val >>= (offset % 4) * 8;
50 val &= 0xff;
51
52 return val;
53 }
54
fuse_read(struct file * fd,struct kobject * kobj,struct bin_attribute * attr,char * buf,loff_t pos,size_t size)55 static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
56 struct bin_attribute *attr, char *buf,
57 loff_t pos, size_t size)
58 {
59 int i;
60
61 if (pos < 0 || pos >= fuse_size)
62 return 0;
63
64 if (size > fuse_size - pos)
65 size = fuse_size - pos;
66
67 for (i = 0; i < size; i++)
68 buf[i] = fuse_readb(pos + i);
69
70 return i;
71 }
72
73 static struct bin_attribute fuse_bin_attr = {
74 .attr = { .name = "fuse", .mode = S_IRUGO, },
75 .read = fuse_read,
76 };
77
78 static const struct of_device_id car_match[] __initconst = {
79 { .compatible = "nvidia,tegra20-car", },
80 { .compatible = "nvidia,tegra30-car", },
81 { .compatible = "nvidia,tegra114-car", },
82 { .compatible = "nvidia,tegra124-car", },
83 {},
84 };
85
tegra_enable_fuse_clk(void __iomem * base)86 static void tegra_enable_fuse_clk(void __iomem *base)
87 {
88 u32 reg;
89
90 reg = readl_relaxed(base + 0x48);
91 reg |= 1 << 28;
92 writel(reg, base + 0x48);
93
94 /*
95 * Enable FUSE clock. This needs to be hardcoded because the clock
96 * subsystem is not active during early boot.
97 */
98 reg = readl(base + 0x14);
99 reg |= 1 << 7;
100 writel(reg, base + 0x14);
101 }
102
tegra_fuse_readl(unsigned long offset,u32 * value)103 int tegra_fuse_readl(unsigned long offset, u32 *value)
104 {
105 if (!fuse_readl)
106 return -EPROBE_DEFER;
107
108 *value = fuse_readl(offset);
109
110 return 0;
111 }
112 EXPORT_SYMBOL(tegra_fuse_readl);
113
tegra_fuse_create_sysfs(struct device * dev,int size,u32 (* readl)(const unsigned int offset))114 int tegra_fuse_create_sysfs(struct device *dev, int size,
115 u32 (*readl)(const unsigned int offset))
116 {
117 if (fuse_size)
118 return -ENODEV;
119
120 fuse_bin_attr.size = size;
121 fuse_bin_attr.read = fuse_read;
122
123 fuse_size = size;
124 fuse_readl = readl;
125
126 return device_create_bin_file(dev, &fuse_bin_attr);
127 }
128
tegra_init_fuse(void)129 static int __init tegra_init_fuse(void)
130 {
131 struct device_node *np;
132 void __iomem *car_base;
133
134 if (!soc_is_tegra())
135 return 0;
136
137 tegra_init_apbmisc();
138
139 np = of_find_matching_node(NULL, car_match);
140 car_base = of_iomap(np, 0);
141 if (car_base) {
142 tegra_enable_fuse_clk(car_base);
143 iounmap(car_base);
144 } else {
145 pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
146 return -ENXIO;
147 }
148
149 if (tegra_get_chip_id() == TEGRA20)
150 tegra20_init_fuse_early();
151 else
152 tegra30_init_fuse_early();
153
154 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
155 tegra_revision_name[tegra_sku_info.revision],
156 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
157 tegra_sku_info.core_process_id);
158 pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
159 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
160
161 return 0;
162 }
163 early_initcall(tegra_init_fuse);
164