1 /*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include <linux/mfd/arizona/registers.h>
34
35 #include "arizona.h"
36 #include "wm_adsp.h"
37
38 #define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40 #define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42 #define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44 #define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46 #define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48
49 #define ADSP1_CONTROL_1 0x00
50 #define ADSP1_CONTROL_2 0x02
51 #define ADSP1_CONTROL_3 0x03
52 #define ADSP1_CONTROL_4 0x04
53 #define ADSP1_CONTROL_5 0x06
54 #define ADSP1_CONTROL_6 0x07
55 #define ADSP1_CONTROL_7 0x08
56 #define ADSP1_CONTROL_8 0x09
57 #define ADSP1_CONTROL_9 0x0A
58 #define ADSP1_CONTROL_10 0x0B
59 #define ADSP1_CONTROL_11 0x0C
60 #define ADSP1_CONTROL_12 0x0D
61 #define ADSP1_CONTROL_13 0x0F
62 #define ADSP1_CONTROL_14 0x10
63 #define ADSP1_CONTROL_15 0x11
64 #define ADSP1_CONTROL_16 0x12
65 #define ADSP1_CONTROL_17 0x13
66 #define ADSP1_CONTROL_18 0x14
67 #define ADSP1_CONTROL_19 0x16
68 #define ADSP1_CONTROL_20 0x17
69 #define ADSP1_CONTROL_21 0x18
70 #define ADSP1_CONTROL_22 0x1A
71 #define ADSP1_CONTROL_23 0x1B
72 #define ADSP1_CONTROL_24 0x1C
73 #define ADSP1_CONTROL_25 0x1E
74 #define ADSP1_CONTROL_26 0x20
75 #define ADSP1_CONTROL_27 0x21
76 #define ADSP1_CONTROL_28 0x22
77 #define ADSP1_CONTROL_29 0x23
78 #define ADSP1_CONTROL_30 0x24
79 #define ADSP1_CONTROL_31 0x26
80
81 /*
82 * ADSP1 Control 19
83 */
84 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87
88
89 /*
90 * ADSP1 Control 30
91 */
92 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
97 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
100 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
101 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
104 #define ADSP1_START 0x0001 /* DSP1_START */
105 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
106 #define ADSP1_START_SHIFT 0 /* DSP1_START */
107 #define ADSP1_START_WIDTH 1 /* DSP1_START */
108
109 /*
110 * ADSP1 Control 31
111 */
112 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
113 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
115
116 #define ADSP2_CONTROL 0x0
117 #define ADSP2_CLOCKING 0x1
118 #define ADSP2_STATUS1 0x4
119 #define ADSP2_WDMA_CONFIG_1 0x30
120 #define ADSP2_WDMA_CONFIG_2 0x31
121 #define ADSP2_RDMA_CONFIG_1 0x34
122
123 /*
124 * ADSP2 Control
125 */
126
127 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
128 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
129 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
130 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
131 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
132 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
133 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
134 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
135 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
136 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
137 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
138 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
139 #define ADSP2_START 0x0001 /* DSP1_START */
140 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
141 #define ADSP2_START_SHIFT 0 /* DSP1_START */
142 #define ADSP2_START_WIDTH 1 /* DSP1_START */
143
144 /*
145 * ADSP2 clocking
146 */
147 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
148 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
149 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
150
151 /*
152 * ADSP2 Status 1
153 */
154 #define ADSP2_RAM_RDY 0x0001
155 #define ADSP2_RAM_RDY_MASK 0x0001
156 #define ADSP2_RAM_RDY_SHIFT 0
157 #define ADSP2_RAM_RDY_WIDTH 1
158
159 struct wm_adsp_buf {
160 struct list_head list;
161 void *buf;
162 };
163
wm_adsp_buf_alloc(const void * src,size_t len,struct list_head * list)164 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
165 struct list_head *list)
166 {
167 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
168
169 if (buf == NULL)
170 return NULL;
171
172 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
173 if (!buf->buf) {
174 kfree(buf);
175 return NULL;
176 }
177
178 if (list)
179 list_add_tail(&buf->list, list);
180
181 return buf;
182 }
183
wm_adsp_buf_free(struct list_head * list)184 static void wm_adsp_buf_free(struct list_head *list)
185 {
186 while (!list_empty(list)) {
187 struct wm_adsp_buf *buf = list_first_entry(list,
188 struct wm_adsp_buf,
189 list);
190 list_del(&buf->list);
191 kfree(buf->buf);
192 kfree(buf);
193 }
194 }
195
196 #define WM_ADSP_NUM_FW 4
197
198 #define WM_ADSP_FW_MBC_VSS 0
199 #define WM_ADSP_FW_TX 1
200 #define WM_ADSP_FW_TX_SPK 2
201 #define WM_ADSP_FW_RX_ANC 3
202
203 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
204 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
205 [WM_ADSP_FW_TX] = "Tx",
206 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
207 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
208 };
209
210 static struct {
211 const char *file;
212 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
213 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
214 [WM_ADSP_FW_TX] = { .file = "tx" },
215 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
216 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
217 };
218
219 struct wm_coeff_ctl_ops {
220 int (*xget)(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *ucontrol);
222 int (*xput)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xinfo)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_info *uinfo);
226 };
227
228 struct wm_coeff_ctl {
229 const char *name;
230 struct wm_adsp_alg_region region;
231 struct wm_coeff_ctl_ops ops;
232 struct wm_adsp *adsp;
233 void *private;
234 unsigned int enabled:1;
235 struct list_head list;
236 void *cache;
237 size_t len;
238 unsigned int set:1;
239 struct snd_kcontrol *kcontrol;
240 };
241
wm_adsp_fw_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)242 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
243 struct snd_ctl_elem_value *ucontrol)
244 {
245 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
246 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
247 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
248
249 ucontrol->value.enumerated.item[0] = adsp[e->shift_l].fw;
250
251 return 0;
252 }
253
wm_adsp_fw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)254 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol)
256 {
257 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
258 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
259 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
260
261 if (ucontrol->value.enumerated.item[0] == adsp[e->shift_l].fw)
262 return 0;
263
264 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
265 return -EINVAL;
266
267 if (adsp[e->shift_l].running)
268 return -EBUSY;
269
270 adsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
271
272 return 0;
273 }
274
275 static const struct soc_enum wm_adsp_fw_enum[] = {
276 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
277 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
278 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
279 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
280 };
281
282 const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
283 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
284 wm_adsp_fw_get, wm_adsp_fw_put),
285 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
286 wm_adsp_fw_get, wm_adsp_fw_put),
287 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
288 wm_adsp_fw_get, wm_adsp_fw_put),
289 };
290 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
291
292 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
293 static const struct soc_enum wm_adsp2_rate_enum[] = {
294 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
295 ARIZONA_DSP1_RATE_SHIFT, 0xf,
296 ARIZONA_RATE_ENUM_SIZE,
297 arizona_rate_text, arizona_rate_val),
298 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
299 ARIZONA_DSP1_RATE_SHIFT, 0xf,
300 ARIZONA_RATE_ENUM_SIZE,
301 arizona_rate_text, arizona_rate_val),
302 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
303 ARIZONA_DSP1_RATE_SHIFT, 0xf,
304 ARIZONA_RATE_ENUM_SIZE,
305 arizona_rate_text, arizona_rate_val),
306 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
307 ARIZONA_DSP1_RATE_SHIFT, 0xf,
308 ARIZONA_RATE_ENUM_SIZE,
309 arizona_rate_text, arizona_rate_val),
310 };
311
312 const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
313 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
314 wm_adsp_fw_get, wm_adsp_fw_put),
315 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
316 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
317 wm_adsp_fw_get, wm_adsp_fw_put),
318 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
319 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
320 wm_adsp_fw_get, wm_adsp_fw_put),
321 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
322 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
323 wm_adsp_fw_get, wm_adsp_fw_put),
324 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
325 };
326 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
327 #endif
328
wm_adsp_find_region(struct wm_adsp * dsp,int type)329 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
330 int type)
331 {
332 int i;
333
334 for (i = 0; i < dsp->num_mems; i++)
335 if (dsp->mem[i].type == type)
336 return &dsp->mem[i];
337
338 return NULL;
339 }
340
wm_adsp_region_to_reg(struct wm_adsp_region const * region,unsigned int offset)341 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
342 unsigned int offset)
343 {
344 if (WARN_ON(!region))
345 return offset;
346 switch (region->type) {
347 case WMFW_ADSP1_PM:
348 return region->base + (offset * 3);
349 case WMFW_ADSP1_DM:
350 return region->base + (offset * 2);
351 case WMFW_ADSP2_XM:
352 return region->base + (offset * 2);
353 case WMFW_ADSP2_YM:
354 return region->base + (offset * 2);
355 case WMFW_ADSP1_ZM:
356 return region->base + (offset * 2);
357 default:
358 WARN(1, "Unknown memory region type");
359 return offset;
360 }
361 }
362
wm_coeff_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)363 static int wm_coeff_info(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_info *uinfo)
365 {
366 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
367
368 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
369 uinfo->count = ctl->len;
370 return 0;
371 }
372
wm_coeff_write_control(struct snd_kcontrol * kcontrol,const void * buf,size_t len)373 static int wm_coeff_write_control(struct snd_kcontrol *kcontrol,
374 const void *buf, size_t len)
375 {
376 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
377 struct wm_adsp_alg_region *region = &ctl->region;
378 const struct wm_adsp_region *mem;
379 struct wm_adsp *adsp = ctl->adsp;
380 void *scratch;
381 int ret;
382 unsigned int reg;
383
384 mem = wm_adsp_find_region(adsp, region->type);
385 if (!mem) {
386 adsp_err(adsp, "No base for region %x\n",
387 region->type);
388 return -EINVAL;
389 }
390
391 reg = ctl->region.base;
392 reg = wm_adsp_region_to_reg(mem, reg);
393
394 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
395 if (!scratch)
396 return -ENOMEM;
397
398 ret = regmap_raw_write(adsp->regmap, reg, scratch,
399 ctl->len);
400 if (ret) {
401 adsp_err(adsp, "Failed to write %zu bytes to %x: %d\n",
402 ctl->len, reg, ret);
403 kfree(scratch);
404 return ret;
405 }
406 adsp_dbg(adsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
407
408 kfree(scratch);
409
410 return 0;
411 }
412
wm_coeff_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)413 static int wm_coeff_put(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
415 {
416 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
417 char *p = ucontrol->value.bytes.data;
418
419 memcpy(ctl->cache, p, ctl->len);
420
421 if (!ctl->enabled) {
422 ctl->set = 1;
423 return 0;
424 }
425
426 return wm_coeff_write_control(kcontrol, p, ctl->len);
427 }
428
wm_coeff_read_control(struct snd_kcontrol * kcontrol,void * buf,size_t len)429 static int wm_coeff_read_control(struct snd_kcontrol *kcontrol,
430 void *buf, size_t len)
431 {
432 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
433 struct wm_adsp_alg_region *region = &ctl->region;
434 const struct wm_adsp_region *mem;
435 struct wm_adsp *adsp = ctl->adsp;
436 void *scratch;
437 int ret;
438 unsigned int reg;
439
440 mem = wm_adsp_find_region(adsp, region->type);
441 if (!mem) {
442 adsp_err(adsp, "No base for region %x\n",
443 region->type);
444 return -EINVAL;
445 }
446
447 reg = ctl->region.base;
448 reg = wm_adsp_region_to_reg(mem, reg);
449
450 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
451 if (!scratch)
452 return -ENOMEM;
453
454 ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len);
455 if (ret) {
456 adsp_err(adsp, "Failed to read %zu bytes from %x: %d\n",
457 ctl->len, reg, ret);
458 kfree(scratch);
459 return ret;
460 }
461 adsp_dbg(adsp, "Read %zu bytes from %x\n", ctl->len, reg);
462
463 memcpy(buf, scratch, ctl->len);
464 kfree(scratch);
465
466 return 0;
467 }
468
wm_coeff_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)469 static int wm_coeff_get(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_value *ucontrol)
471 {
472 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
473 char *p = ucontrol->value.bytes.data;
474
475 memcpy(p, ctl->cache, ctl->len);
476 return 0;
477 }
478
479 struct wmfw_ctl_work {
480 struct wm_adsp *adsp;
481 struct wm_coeff_ctl *ctl;
482 struct work_struct work;
483 };
484
wmfw_add_ctl(struct wm_adsp * adsp,struct wm_coeff_ctl * ctl)485 static int wmfw_add_ctl(struct wm_adsp *adsp, struct wm_coeff_ctl *ctl)
486 {
487 struct snd_kcontrol_new *kcontrol;
488 int ret;
489
490 if (!ctl || !ctl->name)
491 return -EINVAL;
492
493 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
494 if (!kcontrol)
495 return -ENOMEM;
496 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
497
498 kcontrol->name = ctl->name;
499 kcontrol->info = wm_coeff_info;
500 kcontrol->get = wm_coeff_get;
501 kcontrol->put = wm_coeff_put;
502 kcontrol->private_value = (unsigned long)ctl;
503
504 ret = snd_soc_add_card_controls(adsp->card,
505 kcontrol, 1);
506 if (ret < 0)
507 goto err_kcontrol;
508
509 kfree(kcontrol);
510
511 ctl->kcontrol = snd_soc_card_get_kcontrol(adsp->card,
512 ctl->name);
513
514 list_add(&ctl->list, &adsp->ctl_list);
515 return 0;
516
517 err_kcontrol:
518 kfree(kcontrol);
519 return ret;
520 }
521
wm_adsp_load(struct wm_adsp * dsp)522 static int wm_adsp_load(struct wm_adsp *dsp)
523 {
524 LIST_HEAD(buf_list);
525 const struct firmware *firmware;
526 struct regmap *regmap = dsp->regmap;
527 unsigned int pos = 0;
528 const struct wmfw_header *header;
529 const struct wmfw_adsp1_sizes *adsp1_sizes;
530 const struct wmfw_adsp2_sizes *adsp2_sizes;
531 const struct wmfw_footer *footer;
532 const struct wmfw_region *region;
533 const struct wm_adsp_region *mem;
534 const char *region_name;
535 char *file, *text = NULL;
536 struct wm_adsp_buf *buf;
537 unsigned int reg;
538 int regions = 0;
539 int ret, offset, type, sizes;
540
541 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
542 if (file == NULL)
543 return -ENOMEM;
544
545 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
546 wm_adsp_fw[dsp->fw].file);
547 file[PAGE_SIZE - 1] = '\0';
548
549 ret = request_firmware(&firmware, file, dsp->dev);
550 if (ret != 0) {
551 adsp_err(dsp, "Failed to request '%s'\n", file);
552 goto out;
553 }
554 ret = -EINVAL;
555
556 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
557 if (pos >= firmware->size) {
558 adsp_err(dsp, "%s: file too short, %zu bytes\n",
559 file, firmware->size);
560 goto out_fw;
561 }
562
563 header = (void*)&firmware->data[0];
564
565 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
566 adsp_err(dsp, "%s: invalid magic\n", file);
567 goto out_fw;
568 }
569
570 if (header->ver != 0) {
571 adsp_err(dsp, "%s: unknown file format %d\n",
572 file, header->ver);
573 goto out_fw;
574 }
575 adsp_info(dsp, "Firmware version: %d\n", header->ver);
576
577 if (header->core != dsp->type) {
578 adsp_err(dsp, "%s: invalid core %d != %d\n",
579 file, header->core, dsp->type);
580 goto out_fw;
581 }
582
583 switch (dsp->type) {
584 case WMFW_ADSP1:
585 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
586 adsp1_sizes = (void *)&(header[1]);
587 footer = (void *)&(adsp1_sizes[1]);
588 sizes = sizeof(*adsp1_sizes);
589
590 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
591 file, le32_to_cpu(adsp1_sizes->dm),
592 le32_to_cpu(adsp1_sizes->pm),
593 le32_to_cpu(adsp1_sizes->zm));
594 break;
595
596 case WMFW_ADSP2:
597 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
598 adsp2_sizes = (void *)&(header[1]);
599 footer = (void *)&(adsp2_sizes[1]);
600 sizes = sizeof(*adsp2_sizes);
601
602 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
603 file, le32_to_cpu(adsp2_sizes->xm),
604 le32_to_cpu(adsp2_sizes->ym),
605 le32_to_cpu(adsp2_sizes->pm),
606 le32_to_cpu(adsp2_sizes->zm));
607 break;
608
609 default:
610 WARN(1, "Unknown DSP type");
611 goto out_fw;
612 }
613
614 if (le32_to_cpu(header->len) != sizeof(*header) +
615 sizes + sizeof(*footer)) {
616 adsp_err(dsp, "%s: unexpected header length %d\n",
617 file, le32_to_cpu(header->len));
618 goto out_fw;
619 }
620
621 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
622 le64_to_cpu(footer->timestamp));
623
624 while (pos < firmware->size &&
625 pos - firmware->size > sizeof(*region)) {
626 region = (void *)&(firmware->data[pos]);
627 region_name = "Unknown";
628 reg = 0;
629 text = NULL;
630 offset = le32_to_cpu(region->offset) & 0xffffff;
631 type = be32_to_cpu(region->type) & 0xff;
632 mem = wm_adsp_find_region(dsp, type);
633
634 switch (type) {
635 case WMFW_NAME_TEXT:
636 region_name = "Firmware name";
637 text = kzalloc(le32_to_cpu(region->len) + 1,
638 GFP_KERNEL);
639 break;
640 case WMFW_INFO_TEXT:
641 region_name = "Information";
642 text = kzalloc(le32_to_cpu(region->len) + 1,
643 GFP_KERNEL);
644 break;
645 case WMFW_ABSOLUTE:
646 region_name = "Absolute";
647 reg = offset;
648 break;
649 case WMFW_ADSP1_PM:
650 region_name = "PM";
651 reg = wm_adsp_region_to_reg(mem, offset);
652 break;
653 case WMFW_ADSP1_DM:
654 region_name = "DM";
655 reg = wm_adsp_region_to_reg(mem, offset);
656 break;
657 case WMFW_ADSP2_XM:
658 region_name = "XM";
659 reg = wm_adsp_region_to_reg(mem, offset);
660 break;
661 case WMFW_ADSP2_YM:
662 region_name = "YM";
663 reg = wm_adsp_region_to_reg(mem, offset);
664 break;
665 case WMFW_ADSP1_ZM:
666 region_name = "ZM";
667 reg = wm_adsp_region_to_reg(mem, offset);
668 break;
669 default:
670 adsp_warn(dsp,
671 "%s.%d: Unknown region type %x at %d(%x)\n",
672 file, regions, type, pos, pos);
673 break;
674 }
675
676 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
677 regions, le32_to_cpu(region->len), offset,
678 region_name);
679
680 if ((pos + le32_to_cpu(region->len) + sizeof(*region)) >
681 firmware->size) {
682 adsp_err(dsp,
683 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
684 file, regions, region_name,
685 le32_to_cpu(region->len), firmware->size);
686 ret = -EINVAL;
687 goto out_fw;
688 }
689
690 if (text) {
691 memcpy(text, region->data, le32_to_cpu(region->len));
692 adsp_info(dsp, "%s: %s\n", file, text);
693 kfree(text);
694 text = NULL;
695 }
696
697 if (reg) {
698 size_t to_write = PAGE_SIZE;
699 size_t remain = le32_to_cpu(region->len);
700 const u8 *data = region->data;
701
702 while (remain > 0) {
703 if (remain < PAGE_SIZE)
704 to_write = remain;
705
706 buf = wm_adsp_buf_alloc(data,
707 to_write,
708 &buf_list);
709 if (!buf) {
710 adsp_err(dsp, "Out of memory\n");
711 ret = -ENOMEM;
712 goto out_fw;
713 }
714
715 ret = regmap_raw_write_async(regmap, reg,
716 buf->buf,
717 to_write);
718 if (ret != 0) {
719 adsp_err(dsp,
720 "%s.%d: Failed to write %zd bytes at %d in %s: %d\n",
721 file, regions,
722 to_write, offset,
723 region_name, ret);
724 goto out_fw;
725 }
726
727 data += to_write;
728 reg += to_write / 2;
729 remain -= to_write;
730 }
731 }
732
733 pos += le32_to_cpu(region->len) + sizeof(*region);
734 regions++;
735 }
736
737 ret = regmap_async_complete(regmap);
738 if (ret != 0) {
739 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
740 goto out_fw;
741 }
742
743 if (pos > firmware->size)
744 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
745 file, regions, pos - firmware->size);
746
747 out_fw:
748 regmap_async_complete(regmap);
749 wm_adsp_buf_free(&buf_list);
750 release_firmware(firmware);
751 kfree(text);
752 out:
753 kfree(file);
754
755 return ret;
756 }
757
wm_coeff_init_control_caches(struct wm_adsp * adsp)758 static int wm_coeff_init_control_caches(struct wm_adsp *adsp)
759 {
760 struct wm_coeff_ctl *ctl;
761 int ret;
762
763 list_for_each_entry(ctl, &adsp->ctl_list, list) {
764 if (!ctl->enabled || ctl->set)
765 continue;
766 ret = wm_coeff_read_control(ctl->kcontrol,
767 ctl->cache,
768 ctl->len);
769 if (ret < 0)
770 return ret;
771 }
772
773 return 0;
774 }
775
wm_coeff_sync_controls(struct wm_adsp * adsp)776 static int wm_coeff_sync_controls(struct wm_adsp *adsp)
777 {
778 struct wm_coeff_ctl *ctl;
779 int ret;
780
781 list_for_each_entry(ctl, &adsp->ctl_list, list) {
782 if (!ctl->enabled)
783 continue;
784 if (ctl->set) {
785 ret = wm_coeff_write_control(ctl->kcontrol,
786 ctl->cache,
787 ctl->len);
788 if (ret < 0)
789 return ret;
790 }
791 }
792
793 return 0;
794 }
795
wm_adsp_ctl_work(struct work_struct * work)796 static void wm_adsp_ctl_work(struct work_struct *work)
797 {
798 struct wmfw_ctl_work *ctl_work = container_of(work,
799 struct wmfw_ctl_work,
800 work);
801
802 wmfw_add_ctl(ctl_work->adsp, ctl_work->ctl);
803 kfree(ctl_work);
804 }
805
wm_adsp_create_control(struct wm_adsp * dsp,const struct wm_adsp_alg_region * region)806 static int wm_adsp_create_control(struct wm_adsp *dsp,
807 const struct wm_adsp_alg_region *region)
808
809 {
810 struct wm_coeff_ctl *ctl;
811 struct wmfw_ctl_work *ctl_work;
812 char *name;
813 char *region_name;
814 int ret;
815
816 name = kmalloc(PAGE_SIZE, GFP_KERNEL);
817 if (!name)
818 return -ENOMEM;
819
820 switch (region->type) {
821 case WMFW_ADSP1_PM:
822 region_name = "PM";
823 break;
824 case WMFW_ADSP1_DM:
825 region_name = "DM";
826 break;
827 case WMFW_ADSP2_XM:
828 region_name = "XM";
829 break;
830 case WMFW_ADSP2_YM:
831 region_name = "YM";
832 break;
833 case WMFW_ADSP1_ZM:
834 region_name = "ZM";
835 break;
836 default:
837 ret = -EINVAL;
838 goto err_name;
839 }
840
841 snprintf(name, PAGE_SIZE, "DSP%d %s %x",
842 dsp->num, region_name, region->alg);
843
844 list_for_each_entry(ctl, &dsp->ctl_list,
845 list) {
846 if (!strcmp(ctl->name, name)) {
847 if (!ctl->enabled)
848 ctl->enabled = 1;
849 goto found;
850 }
851 }
852
853 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
854 if (!ctl) {
855 ret = -ENOMEM;
856 goto err_name;
857 }
858 ctl->region = *region;
859 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
860 if (!ctl->name) {
861 ret = -ENOMEM;
862 goto err_ctl;
863 }
864 ctl->enabled = 1;
865 ctl->set = 0;
866 ctl->ops.xget = wm_coeff_get;
867 ctl->ops.xput = wm_coeff_put;
868 ctl->adsp = dsp;
869
870 ctl->len = region->len;
871 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
872 if (!ctl->cache) {
873 ret = -ENOMEM;
874 goto err_ctl_name;
875 }
876
877 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
878 if (!ctl_work) {
879 ret = -ENOMEM;
880 goto err_ctl_cache;
881 }
882
883 ctl_work->adsp = dsp;
884 ctl_work->ctl = ctl;
885 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
886 schedule_work(&ctl_work->work);
887
888 found:
889 kfree(name);
890
891 return 0;
892
893 err_ctl_cache:
894 kfree(ctl->cache);
895 err_ctl_name:
896 kfree(ctl->name);
897 err_ctl:
898 kfree(ctl);
899 err_name:
900 kfree(name);
901 return ret;
902 }
903
wm_adsp_setup_algs(struct wm_adsp * dsp)904 static int wm_adsp_setup_algs(struct wm_adsp *dsp)
905 {
906 struct regmap *regmap = dsp->regmap;
907 struct wmfw_adsp1_id_hdr adsp1_id;
908 struct wmfw_adsp2_id_hdr adsp2_id;
909 struct wmfw_adsp1_alg_hdr *adsp1_alg;
910 struct wmfw_adsp2_alg_hdr *adsp2_alg;
911 void *alg, *buf;
912 struct wm_adsp_alg_region *region;
913 const struct wm_adsp_region *mem;
914 unsigned int pos, term;
915 size_t algs, buf_size;
916 __be32 val;
917 int i, ret;
918
919 switch (dsp->type) {
920 case WMFW_ADSP1:
921 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
922 break;
923 case WMFW_ADSP2:
924 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
925 break;
926 default:
927 mem = NULL;
928 break;
929 }
930
931 if (WARN_ON(!mem))
932 return -EINVAL;
933
934 switch (dsp->type) {
935 case WMFW_ADSP1:
936 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
937 sizeof(adsp1_id));
938 if (ret != 0) {
939 adsp_err(dsp, "Failed to read algorithm info: %d\n",
940 ret);
941 return ret;
942 }
943
944 buf = &adsp1_id;
945 buf_size = sizeof(adsp1_id);
946
947 algs = be32_to_cpu(adsp1_id.algs);
948 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
949 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
950 dsp->fw_id,
951 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
952 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
953 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
954 algs);
955
956 region = kzalloc(sizeof(*region), GFP_KERNEL);
957 if (!region)
958 return -ENOMEM;
959 region->type = WMFW_ADSP1_ZM;
960 region->alg = be32_to_cpu(adsp1_id.fw.id);
961 region->base = be32_to_cpu(adsp1_id.zm);
962 list_add_tail(®ion->list, &dsp->alg_regions);
963
964 region = kzalloc(sizeof(*region), GFP_KERNEL);
965 if (!region)
966 return -ENOMEM;
967 region->type = WMFW_ADSP1_DM;
968 region->alg = be32_to_cpu(adsp1_id.fw.id);
969 region->base = be32_to_cpu(adsp1_id.dm);
970 list_add_tail(®ion->list, &dsp->alg_regions);
971
972 pos = sizeof(adsp1_id) / 2;
973 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
974 break;
975
976 case WMFW_ADSP2:
977 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
978 sizeof(adsp2_id));
979 if (ret != 0) {
980 adsp_err(dsp, "Failed to read algorithm info: %d\n",
981 ret);
982 return ret;
983 }
984
985 buf = &adsp2_id;
986 buf_size = sizeof(adsp2_id);
987
988 algs = be32_to_cpu(adsp2_id.algs);
989 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
990 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
991 dsp->fw_id,
992 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
993 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
994 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
995 algs);
996
997 region = kzalloc(sizeof(*region), GFP_KERNEL);
998 if (!region)
999 return -ENOMEM;
1000 region->type = WMFW_ADSP2_XM;
1001 region->alg = be32_to_cpu(adsp2_id.fw.id);
1002 region->base = be32_to_cpu(adsp2_id.xm);
1003 list_add_tail(®ion->list, &dsp->alg_regions);
1004
1005 region = kzalloc(sizeof(*region), GFP_KERNEL);
1006 if (!region)
1007 return -ENOMEM;
1008 region->type = WMFW_ADSP2_YM;
1009 region->alg = be32_to_cpu(adsp2_id.fw.id);
1010 region->base = be32_to_cpu(adsp2_id.ym);
1011 list_add_tail(®ion->list, &dsp->alg_regions);
1012
1013 region = kzalloc(sizeof(*region), GFP_KERNEL);
1014 if (!region)
1015 return -ENOMEM;
1016 region->type = WMFW_ADSP2_ZM;
1017 region->alg = be32_to_cpu(adsp2_id.fw.id);
1018 region->base = be32_to_cpu(adsp2_id.zm);
1019 list_add_tail(®ion->list, &dsp->alg_regions);
1020
1021 pos = sizeof(adsp2_id) / 2;
1022 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
1023 break;
1024
1025 default:
1026 WARN(1, "Unknown DSP type");
1027 return -EINVAL;
1028 }
1029
1030 if (algs == 0) {
1031 adsp_err(dsp, "No algorithms\n");
1032 return -EINVAL;
1033 }
1034
1035 if (algs > 1024) {
1036 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
1037 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
1038 buf, buf_size);
1039 return -EINVAL;
1040 }
1041
1042 /* Read the terminator first to validate the length */
1043 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
1044 if (ret != 0) {
1045 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1046 ret);
1047 return ret;
1048 }
1049
1050 if (be32_to_cpu(val) != 0xbedead)
1051 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1052 term, be32_to_cpu(val));
1053
1054 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
1055 if (!alg)
1056 return -ENOMEM;
1057
1058 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
1059 if (ret != 0) {
1060 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1061 ret);
1062 goto out;
1063 }
1064
1065 adsp1_alg = alg;
1066 adsp2_alg = alg;
1067
1068 for (i = 0; i < algs; i++) {
1069 switch (dsp->type) {
1070 case WMFW_ADSP1:
1071 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1072 i, be32_to_cpu(adsp1_alg[i].alg.id),
1073 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1074 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1075 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1076 be32_to_cpu(adsp1_alg[i].dm),
1077 be32_to_cpu(adsp1_alg[i].zm));
1078
1079 region = kzalloc(sizeof(*region), GFP_KERNEL);
1080 if (!region)
1081 return -ENOMEM;
1082 region->type = WMFW_ADSP1_DM;
1083 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1084 region->base = be32_to_cpu(adsp1_alg[i].dm);
1085 region->len = 0;
1086 list_add_tail(®ion->list, &dsp->alg_regions);
1087 if (i + 1 < algs) {
1088 region->len = be32_to_cpu(adsp1_alg[i + 1].dm);
1089 region->len -= be32_to_cpu(adsp1_alg[i].dm);
1090 region->len *= 4;
1091 wm_adsp_create_control(dsp, region);
1092 } else {
1093 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1094 be32_to_cpu(adsp1_alg[i].alg.id));
1095 }
1096
1097 region = kzalloc(sizeof(*region), GFP_KERNEL);
1098 if (!region)
1099 return -ENOMEM;
1100 region->type = WMFW_ADSP1_ZM;
1101 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1102 region->base = be32_to_cpu(adsp1_alg[i].zm);
1103 region->len = 0;
1104 list_add_tail(®ion->list, &dsp->alg_regions);
1105 if (i + 1 < algs) {
1106 region->len = be32_to_cpu(adsp1_alg[i + 1].zm);
1107 region->len -= be32_to_cpu(adsp1_alg[i].zm);
1108 region->len *= 4;
1109 wm_adsp_create_control(dsp, region);
1110 } else {
1111 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1112 be32_to_cpu(adsp1_alg[i].alg.id));
1113 }
1114 break;
1115
1116 case WMFW_ADSP2:
1117 adsp_info(dsp,
1118 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1119 i, be32_to_cpu(adsp2_alg[i].alg.id),
1120 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1121 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1122 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1123 be32_to_cpu(adsp2_alg[i].xm),
1124 be32_to_cpu(adsp2_alg[i].ym),
1125 be32_to_cpu(adsp2_alg[i].zm));
1126
1127 region = kzalloc(sizeof(*region), GFP_KERNEL);
1128 if (!region)
1129 return -ENOMEM;
1130 region->type = WMFW_ADSP2_XM;
1131 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1132 region->base = be32_to_cpu(adsp2_alg[i].xm);
1133 region->len = 0;
1134 list_add_tail(®ion->list, &dsp->alg_regions);
1135 if (i + 1 < algs) {
1136 region->len = be32_to_cpu(adsp2_alg[i + 1].xm);
1137 region->len -= be32_to_cpu(adsp2_alg[i].xm);
1138 region->len *= 4;
1139 wm_adsp_create_control(dsp, region);
1140 } else {
1141 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1142 be32_to_cpu(adsp2_alg[i].alg.id));
1143 }
1144
1145 region = kzalloc(sizeof(*region), GFP_KERNEL);
1146 if (!region)
1147 return -ENOMEM;
1148 region->type = WMFW_ADSP2_YM;
1149 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1150 region->base = be32_to_cpu(adsp2_alg[i].ym);
1151 region->len = 0;
1152 list_add_tail(®ion->list, &dsp->alg_regions);
1153 if (i + 1 < algs) {
1154 region->len = be32_to_cpu(adsp2_alg[i + 1].ym);
1155 region->len -= be32_to_cpu(adsp2_alg[i].ym);
1156 region->len *= 4;
1157 wm_adsp_create_control(dsp, region);
1158 } else {
1159 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1160 be32_to_cpu(adsp2_alg[i].alg.id));
1161 }
1162
1163 region = kzalloc(sizeof(*region), GFP_KERNEL);
1164 if (!region)
1165 return -ENOMEM;
1166 region->type = WMFW_ADSP2_ZM;
1167 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1168 region->base = be32_to_cpu(adsp2_alg[i].zm);
1169 region->len = 0;
1170 list_add_tail(®ion->list, &dsp->alg_regions);
1171 if (i + 1 < algs) {
1172 region->len = be32_to_cpu(adsp2_alg[i + 1].zm);
1173 region->len -= be32_to_cpu(adsp2_alg[i].zm);
1174 region->len *= 4;
1175 wm_adsp_create_control(dsp, region);
1176 } else {
1177 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1178 be32_to_cpu(adsp2_alg[i].alg.id));
1179 }
1180 break;
1181 }
1182 }
1183
1184 out:
1185 kfree(alg);
1186 return ret;
1187 }
1188
wm_adsp_load_coeff(struct wm_adsp * dsp)1189 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1190 {
1191 LIST_HEAD(buf_list);
1192 struct regmap *regmap = dsp->regmap;
1193 struct wmfw_coeff_hdr *hdr;
1194 struct wmfw_coeff_item *blk;
1195 const struct firmware *firmware;
1196 const struct wm_adsp_region *mem;
1197 struct wm_adsp_alg_region *alg_region;
1198 const char *region_name;
1199 int ret, pos, blocks, type, offset, reg;
1200 char *file;
1201 struct wm_adsp_buf *buf;
1202 int tmp;
1203
1204 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1205 if (file == NULL)
1206 return -ENOMEM;
1207
1208 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1209 wm_adsp_fw[dsp->fw].file);
1210 file[PAGE_SIZE - 1] = '\0';
1211
1212 ret = request_firmware(&firmware, file, dsp->dev);
1213 if (ret != 0) {
1214 adsp_warn(dsp, "Failed to request '%s'\n", file);
1215 ret = 0;
1216 goto out;
1217 }
1218 ret = -EINVAL;
1219
1220 if (sizeof(*hdr) >= firmware->size) {
1221 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1222 file, firmware->size);
1223 goto out_fw;
1224 }
1225
1226 hdr = (void*)&firmware->data[0];
1227 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1228 adsp_err(dsp, "%s: invalid magic\n", file);
1229 goto out_fw;
1230 }
1231
1232 switch (be32_to_cpu(hdr->rev) & 0xff) {
1233 case 1:
1234 break;
1235 default:
1236 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1237 file, be32_to_cpu(hdr->rev) & 0xff);
1238 ret = -EINVAL;
1239 goto out_fw;
1240 }
1241
1242 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1243 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1244 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1245 le32_to_cpu(hdr->ver) & 0xff);
1246
1247 pos = le32_to_cpu(hdr->len);
1248
1249 blocks = 0;
1250 while (pos < firmware->size &&
1251 pos - firmware->size > sizeof(*blk)) {
1252 blk = (void*)(&firmware->data[pos]);
1253
1254 type = le16_to_cpu(blk->type);
1255 offset = le16_to_cpu(blk->offset);
1256
1257 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1258 file, blocks, le32_to_cpu(blk->id),
1259 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1260 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1261 le32_to_cpu(blk->ver) & 0xff);
1262 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1263 file, blocks, le32_to_cpu(blk->len), offset, type);
1264
1265 reg = 0;
1266 region_name = "Unknown";
1267 switch (type) {
1268 case (WMFW_NAME_TEXT << 8):
1269 case (WMFW_INFO_TEXT << 8):
1270 break;
1271 case (WMFW_ABSOLUTE << 8):
1272 /*
1273 * Old files may use this for global
1274 * coefficients.
1275 */
1276 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1277 offset == 0) {
1278 region_name = "global coefficients";
1279 mem = wm_adsp_find_region(dsp, type);
1280 if (!mem) {
1281 adsp_err(dsp, "No ZM\n");
1282 break;
1283 }
1284 reg = wm_adsp_region_to_reg(mem, 0);
1285
1286 } else {
1287 region_name = "register";
1288 reg = offset;
1289 }
1290 break;
1291
1292 case WMFW_ADSP1_DM:
1293 case WMFW_ADSP1_ZM:
1294 case WMFW_ADSP2_XM:
1295 case WMFW_ADSP2_YM:
1296 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1297 file, blocks, le32_to_cpu(blk->len),
1298 type, le32_to_cpu(blk->id));
1299
1300 mem = wm_adsp_find_region(dsp, type);
1301 if (!mem) {
1302 adsp_err(dsp, "No base for region %x\n", type);
1303 break;
1304 }
1305
1306 reg = 0;
1307 list_for_each_entry(alg_region,
1308 &dsp->alg_regions, list) {
1309 if (le32_to_cpu(blk->id) == alg_region->alg &&
1310 type == alg_region->type) {
1311 reg = alg_region->base;
1312 reg = wm_adsp_region_to_reg(mem,
1313 reg);
1314 reg += offset;
1315 break;
1316 }
1317 }
1318
1319 if (reg == 0)
1320 adsp_err(dsp, "No %x for algorithm %x\n",
1321 type, le32_to_cpu(blk->id));
1322 break;
1323
1324 default:
1325 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1326 file, blocks, type, pos);
1327 break;
1328 }
1329
1330 if (reg) {
1331 if ((pos + le32_to_cpu(blk->len) + sizeof(*blk)) >
1332 firmware->size) {
1333 adsp_err(dsp,
1334 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1335 file, blocks, region_name,
1336 le32_to_cpu(blk->len),
1337 firmware->size);
1338 ret = -EINVAL;
1339 goto out_fw;
1340 }
1341
1342 buf = wm_adsp_buf_alloc(blk->data,
1343 le32_to_cpu(blk->len),
1344 &buf_list);
1345 if (!buf) {
1346 adsp_err(dsp, "Out of memory\n");
1347 ret = -ENOMEM;
1348 goto out_fw;
1349 }
1350
1351 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1352 file, blocks, le32_to_cpu(blk->len),
1353 reg);
1354 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1355 le32_to_cpu(blk->len));
1356 if (ret != 0) {
1357 adsp_err(dsp,
1358 "%s.%d: Failed to write to %x in %s: %d\n",
1359 file, blocks, reg, region_name, ret);
1360 }
1361 }
1362
1363 tmp = le32_to_cpu(blk->len) % 4;
1364 if (tmp)
1365 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
1366 else
1367 pos += le32_to_cpu(blk->len) + sizeof(*blk);
1368
1369 blocks++;
1370 }
1371
1372 ret = regmap_async_complete(regmap);
1373 if (ret != 0)
1374 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1375
1376 if (pos > firmware->size)
1377 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1378 file, blocks, pos - firmware->size);
1379
1380 out_fw:
1381 regmap_async_complete(regmap);
1382 release_firmware(firmware);
1383 wm_adsp_buf_free(&buf_list);
1384 out:
1385 kfree(file);
1386 return ret;
1387 }
1388
wm_adsp1_init(struct wm_adsp * adsp)1389 int wm_adsp1_init(struct wm_adsp *adsp)
1390 {
1391 INIT_LIST_HEAD(&adsp->alg_regions);
1392
1393 return 0;
1394 }
1395 EXPORT_SYMBOL_GPL(wm_adsp1_init);
1396
wm_adsp1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1397 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1398 struct snd_kcontrol *kcontrol,
1399 int event)
1400 {
1401 struct snd_soc_codec *codec = w->codec;
1402 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1403 struct wm_adsp *dsp = &dsps[w->shift];
1404 struct wm_adsp_alg_region *alg_region;
1405 struct wm_coeff_ctl *ctl;
1406 int ret;
1407 int val;
1408
1409 dsp->card = codec->component.card;
1410
1411 switch (event) {
1412 case SND_SOC_DAPM_POST_PMU:
1413 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1414 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1415
1416 /*
1417 * For simplicity set the DSP clock rate to be the
1418 * SYSCLK rate rather than making it configurable.
1419 */
1420 if(dsp->sysclk_reg) {
1421 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1422 if (ret != 0) {
1423 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1424 ret);
1425 return ret;
1426 }
1427
1428 val = (val & dsp->sysclk_mask)
1429 >> dsp->sysclk_shift;
1430
1431 ret = regmap_update_bits(dsp->regmap,
1432 dsp->base + ADSP1_CONTROL_31,
1433 ADSP1_CLK_SEL_MASK, val);
1434 if (ret != 0) {
1435 adsp_err(dsp, "Failed to set clock rate: %d\n",
1436 ret);
1437 return ret;
1438 }
1439 }
1440
1441 ret = wm_adsp_load(dsp);
1442 if (ret != 0)
1443 goto err;
1444
1445 ret = wm_adsp_setup_algs(dsp);
1446 if (ret != 0)
1447 goto err;
1448
1449 ret = wm_adsp_load_coeff(dsp);
1450 if (ret != 0)
1451 goto err;
1452
1453 /* Initialize caches for enabled and unset controls */
1454 ret = wm_coeff_init_control_caches(dsp);
1455 if (ret != 0)
1456 goto err;
1457
1458 /* Sync set controls */
1459 ret = wm_coeff_sync_controls(dsp);
1460 if (ret != 0)
1461 goto err;
1462
1463 /* Start the core running */
1464 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1465 ADSP1_CORE_ENA | ADSP1_START,
1466 ADSP1_CORE_ENA | ADSP1_START);
1467 break;
1468
1469 case SND_SOC_DAPM_PRE_PMD:
1470 /* Halt the core */
1471 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1472 ADSP1_CORE_ENA | ADSP1_START, 0);
1473
1474 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1475 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1476
1477 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1478 ADSP1_SYS_ENA, 0);
1479
1480 list_for_each_entry(ctl, &dsp->ctl_list, list)
1481 ctl->enabled = 0;
1482
1483 while (!list_empty(&dsp->alg_regions)) {
1484 alg_region = list_first_entry(&dsp->alg_regions,
1485 struct wm_adsp_alg_region,
1486 list);
1487 list_del(&alg_region->list);
1488 kfree(alg_region);
1489 }
1490 break;
1491
1492 default:
1493 break;
1494 }
1495
1496 return 0;
1497
1498 err:
1499 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1500 ADSP1_SYS_ENA, 0);
1501 return ret;
1502 }
1503 EXPORT_SYMBOL_GPL(wm_adsp1_event);
1504
wm_adsp2_ena(struct wm_adsp * dsp)1505 static int wm_adsp2_ena(struct wm_adsp *dsp)
1506 {
1507 unsigned int val;
1508 int ret, count;
1509
1510 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1511 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1512 if (ret != 0)
1513 return ret;
1514
1515 /* Wait for the RAM to start, should be near instantaneous */
1516 for (count = 0; count < 10; ++count) {
1517 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1518 &val);
1519 if (ret != 0)
1520 return ret;
1521
1522 if (val & ADSP2_RAM_RDY)
1523 break;
1524
1525 msleep(1);
1526 }
1527
1528 if (!(val & ADSP2_RAM_RDY)) {
1529 adsp_err(dsp, "Failed to start DSP RAM\n");
1530 return -EBUSY;
1531 }
1532
1533 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1534
1535 return 0;
1536 }
1537
wm_adsp2_boot_work(struct work_struct * work)1538 static void wm_adsp2_boot_work(struct work_struct *work)
1539 {
1540 struct wm_adsp *dsp = container_of(work,
1541 struct wm_adsp,
1542 boot_work);
1543 int ret;
1544 unsigned int val;
1545
1546 /*
1547 * For simplicity set the DSP clock rate to be the
1548 * SYSCLK rate rather than making it configurable.
1549 */
1550 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1551 if (ret != 0) {
1552 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
1553 return;
1554 }
1555 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1556 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1557
1558 ret = regmap_update_bits_async(dsp->regmap,
1559 dsp->base + ADSP2_CLOCKING,
1560 ADSP2_CLK_SEL_MASK, val);
1561 if (ret != 0) {
1562 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
1563 return;
1564 }
1565
1566 if (dsp->dvfs) {
1567 ret = regmap_read(dsp->regmap,
1568 dsp->base + ADSP2_CLOCKING, &val);
1569 if (ret != 0) {
1570 adsp_err(dsp, "Failed to read clocking: %d\n", ret);
1571 return;
1572 }
1573
1574 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1575 ret = regulator_enable(dsp->dvfs);
1576 if (ret != 0) {
1577 adsp_err(dsp,
1578 "Failed to enable supply: %d\n",
1579 ret);
1580 return;
1581 }
1582
1583 ret = regulator_set_voltage(dsp->dvfs,
1584 1800000,
1585 1800000);
1586 if (ret != 0) {
1587 adsp_err(dsp,
1588 "Failed to raise supply: %d\n",
1589 ret);
1590 return;
1591 }
1592 }
1593 }
1594
1595 ret = wm_adsp2_ena(dsp);
1596 if (ret != 0)
1597 return;
1598
1599 ret = wm_adsp_load(dsp);
1600 if (ret != 0)
1601 goto err;
1602
1603 ret = wm_adsp_setup_algs(dsp);
1604 if (ret != 0)
1605 goto err;
1606
1607 ret = wm_adsp_load_coeff(dsp);
1608 if (ret != 0)
1609 goto err;
1610
1611 /* Initialize caches for enabled and unset controls */
1612 ret = wm_coeff_init_control_caches(dsp);
1613 if (ret != 0)
1614 goto err;
1615
1616 /* Sync set controls */
1617 ret = wm_coeff_sync_controls(dsp);
1618 if (ret != 0)
1619 goto err;
1620
1621 ret = regmap_update_bits_async(dsp->regmap,
1622 dsp->base + ADSP2_CONTROL,
1623 ADSP2_CORE_ENA,
1624 ADSP2_CORE_ENA);
1625 if (ret != 0)
1626 goto err;
1627
1628 dsp->running = true;
1629
1630 return;
1631
1632 err:
1633 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1634 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1635 }
1636
wm_adsp2_early_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1637 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
1638 struct snd_kcontrol *kcontrol, int event)
1639 {
1640 struct snd_soc_codec *codec = w->codec;
1641 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1642 struct wm_adsp *dsp = &dsps[w->shift];
1643
1644 dsp->card = codec->component.card;
1645
1646 switch (event) {
1647 case SND_SOC_DAPM_PRE_PMU:
1648 queue_work(system_unbound_wq, &dsp->boot_work);
1649 break;
1650 default:
1651 break;
1652 }
1653
1654 return 0;
1655 }
1656 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
1657
wm_adsp2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1658 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1659 struct snd_kcontrol *kcontrol, int event)
1660 {
1661 struct snd_soc_codec *codec = w->codec;
1662 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1663 struct wm_adsp *dsp = &dsps[w->shift];
1664 struct wm_adsp_alg_region *alg_region;
1665 struct wm_coeff_ctl *ctl;
1666 int ret;
1667
1668 switch (event) {
1669 case SND_SOC_DAPM_POST_PMU:
1670 flush_work(&dsp->boot_work);
1671
1672 if (!dsp->running)
1673 return -EIO;
1674
1675 ret = regmap_update_bits(dsp->regmap,
1676 dsp->base + ADSP2_CONTROL,
1677 ADSP2_START,
1678 ADSP2_START);
1679 if (ret != 0)
1680 goto err;
1681 break;
1682
1683 case SND_SOC_DAPM_PRE_PMD:
1684 dsp->running = false;
1685
1686 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1687 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1688 ADSP2_START, 0);
1689
1690 /* Make sure DMAs are quiesced */
1691 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1692 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1693 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1694
1695 if (dsp->dvfs) {
1696 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1697 1800000);
1698 if (ret != 0)
1699 adsp_warn(dsp,
1700 "Failed to lower supply: %d\n",
1701 ret);
1702
1703 ret = regulator_disable(dsp->dvfs);
1704 if (ret != 0)
1705 adsp_err(dsp,
1706 "Failed to enable supply: %d\n",
1707 ret);
1708 }
1709
1710 list_for_each_entry(ctl, &dsp->ctl_list, list)
1711 ctl->enabled = 0;
1712
1713 while (!list_empty(&dsp->alg_regions)) {
1714 alg_region = list_first_entry(&dsp->alg_regions,
1715 struct wm_adsp_alg_region,
1716 list);
1717 list_del(&alg_region->list);
1718 kfree(alg_region);
1719 }
1720
1721 adsp_dbg(dsp, "Shutdown complete\n");
1722 break;
1723
1724 default:
1725 break;
1726 }
1727
1728 return 0;
1729 err:
1730 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1731 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1732 return ret;
1733 }
1734 EXPORT_SYMBOL_GPL(wm_adsp2_event);
1735
wm_adsp2_init(struct wm_adsp * adsp,bool dvfs)1736 int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1737 {
1738 int ret;
1739
1740 /*
1741 * Disable the DSP memory by default when in reset for a small
1742 * power saving.
1743 */
1744 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1745 ADSP2_MEM_ENA, 0);
1746 if (ret != 0) {
1747 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1748 return ret;
1749 }
1750
1751 INIT_LIST_HEAD(&adsp->alg_regions);
1752 INIT_LIST_HEAD(&adsp->ctl_list);
1753 INIT_WORK(&adsp->boot_work, wm_adsp2_boot_work);
1754
1755 if (dvfs) {
1756 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1757 if (IS_ERR(adsp->dvfs)) {
1758 ret = PTR_ERR(adsp->dvfs);
1759 adsp_err(adsp, "Failed to get DCVDD: %d\n", ret);
1760 return ret;
1761 }
1762
1763 ret = regulator_enable(adsp->dvfs);
1764 if (ret != 0) {
1765 adsp_err(adsp, "Failed to enable DCVDD: %d\n", ret);
1766 return ret;
1767 }
1768
1769 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1770 if (ret != 0) {
1771 adsp_err(adsp, "Failed to initialise DVFS: %d\n", ret);
1772 return ret;
1773 }
1774
1775 ret = regulator_disable(adsp->dvfs);
1776 if (ret != 0) {
1777 adsp_err(adsp, "Failed to disable DCVDD: %d\n", ret);
1778 return ret;
1779 }
1780 }
1781
1782 return 0;
1783 }
1784 EXPORT_SYMBOL_GPL(wm_adsp2_init);
1785
1786 MODULE_LICENSE("GPL v2");
1787