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1/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2.  This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
16 */
17
18#include "armada-370-xp.dtsi"
19/include/ "skeleton.dtsi"
20
21/ {
22	model = "Marvell Armada 370 family SoC";
23	compatible = "marvell,armada370", "marvell,armada-370-xp";
24
25	aliases {
26		gpio0 = &gpio0;
27		gpio1 = &gpio1;
28		gpio2 = &gpio2;
29	};
30
31	soc {
32		compatible = "marvell,armada370-mbus", "simple-bus";
33
34		bootrom {
35			compatible = "marvell,bootrom";
36			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
37		};
38
39		pcie-controller {
40			compatible = "marvell,armada-370-pcie";
41			status = "disabled";
42			device_type = "pci";
43
44			#address-cells = <3>;
45			#size-cells = <2>;
46
47			msi-parent = <&mpic>;
48			bus-range = <0x00 0xff>;
49
50			ranges =
51			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
52				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
53				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
54				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
55				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
56				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
57
58			pcie@1,0 {
59				device_type = "pci";
60				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
61				reg = <0x0800 0 0 0 0>;
62				#address-cells = <3>;
63				#size-cells = <2>;
64				#interrupt-cells = <1>;
65                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
66                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
67				interrupt-map-mask = <0 0 0 0>;
68				interrupt-map = <0 0 0 0 &mpic 58>;
69				marvell,pcie-port = <0>;
70				marvell,pcie-lane = <0>;
71				clocks = <&gateclk 5>;
72				status = "disabled";
73			};
74
75			pcie@2,0 {
76				device_type = "pci";
77				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
78				reg = <0x1000 0 0 0 0>;
79				#address-cells = <3>;
80				#size-cells = <2>;
81				#interrupt-cells = <1>;
82                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
83                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
84				interrupt-map-mask = <0 0 0 0>;
85				interrupt-map = <0 0 0 0 &mpic 62>;
86				marvell,pcie-port = <1>;
87				marvell,pcie-lane = <0>;
88				clocks = <&gateclk 9>;
89				status = "disabled";
90			};
91		};
92
93		internal-regs {
94			L2: l2-cache {
95				compatible = "marvell,aurora-outer-cache";
96				reg = <0x08000 0x1000>;
97				cache-id-part = <0x100>;
98				wt-override;
99			};
100
101			i2c0: i2c@11000 {
102				reg = <0x11000 0x20>;
103			};
104
105			i2c1: i2c@11100 {
106				reg = <0x11100 0x20>;
107			};
108
109			pinctrl {
110				compatible = "marvell,mv88f6710-pinctrl";
111				reg = <0x18000 0x38>;
112
113				sdio_pins1: sdio-pins1 {
114					marvell,pins = "mpp9",  "mpp11", "mpp12",
115							"mpp13", "mpp14", "mpp15";
116					marvell,function = "sd0";
117				};
118
119				sdio_pins2: sdio-pins2 {
120					marvell,pins = "mpp47", "mpp48", "mpp49",
121							"mpp50", "mpp51", "mpp52";
122					marvell,function = "sd0";
123				};
124
125				sdio_pins3: sdio-pins3 {
126					marvell,pins = "mpp48", "mpp49", "mpp50",
127							"mpp51", "mpp52", "mpp53";
128					marvell,function = "sd0";
129				};
130
131				i2c0_pins: i2c0-pins {
132					marvell,pins = "mpp2", "mpp3";
133					marvell,function = "i2c0";
134				};
135
136				i2s_pins1: i2s-pins1 {
137					marvell,pins = "mpp5", "mpp6", "mpp7",
138						       "mpp8", "mpp9", "mpp10",
139						       "mpp12", "mpp13";
140					marvell,function = "audio";
141				};
142
143				i2s_pins2: i2s-pins2 {
144					marvell,pins = "mpp49", "mpp47", "mpp50",
145						       "mpp59", "mpp57", "mpp61",
146						       "mpp62", "mpp60", "mpp58";
147					marvell,function = "audio";
148				};
149
150				mdio_pins: mdio-pins {
151					marvell,pins = "mpp17", "mpp18";
152					marvell,function = "ge";
153				};
154
155				ge0_rgmii_pins: ge0-rgmii-pins {
156					marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
157						       "mpp9", "mpp10", "mpp11", "mpp12",
158						       "mpp13", "mpp14", "mpp15", "mpp16";
159					marvell,function = "ge0";
160				};
161
162				ge1_rgmii_pins: ge1-rgmii-pins {
163					marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
164						       "mpp23", "mpp24", "mpp25", "mpp26",
165						       "mpp27", "mpp28", "mpp29", "mpp30";
166					marvell,function = "ge1";
167				};
168			};
169
170			gpio0: gpio@18100 {
171				compatible = "marvell,orion-gpio";
172				reg = <0x18100 0x40>;
173				ngpios = <32>;
174				gpio-controller;
175				#gpio-cells = <2>;
176				interrupt-controller;
177				#interrupt-cells = <2>;
178				interrupts = <82>, <83>, <84>, <85>;
179			};
180
181			gpio1: gpio@18140 {
182				compatible = "marvell,orion-gpio";
183				reg = <0x18140 0x40>;
184				ngpios = <32>;
185				gpio-controller;
186				#gpio-cells = <2>;
187				interrupt-controller;
188				#interrupt-cells = <2>;
189				interrupts = <87>, <88>, <89>, <90>;
190			};
191
192			gpio2: gpio@18180 {
193				compatible = "marvell,orion-gpio";
194				reg = <0x18180 0x40>;
195				ngpios = <2>;
196				gpio-controller;
197				#gpio-cells = <2>;
198				interrupt-controller;
199				#interrupt-cells = <2>;
200				interrupts = <91>;
201			};
202
203			system-controller@18200 {
204				compatible = "marvell,armada-370-xp-system-controller";
205				reg = <0x18200 0x100>;
206			};
207
208			gateclk: clock-gating-control@18220 {
209				compatible = "marvell,armada-370-gating-clock";
210				reg = <0x18220 0x4>;
211				clocks = <&coreclk 0>;
212				#clock-cells = <1>;
213			};
214
215			coreclk: mvebu-sar@18230 {
216				compatible = "marvell,armada-370-core-clock";
217				reg = <0x18230 0x08>;
218				#clock-cells = <1>;
219			};
220
221			thermal@18300 {
222				compatible = "marvell,armada370-thermal";
223				reg = <0x18300 0x4
224					0x18304 0x4>;
225				status = "okay";
226			};
227
228			sscg@18330 {
229				reg = <0x18330 0x4>;
230			};
231
232			interrupt-controller@20000 {
233				reg = <0x20a00 0x1d0>, <0x21870 0x58>;
234			};
235
236			timer@20300 {
237				compatible = "marvell,armada-370-timer";
238				clocks = <&coreclk 2>;
239			};
240
241			watchdog@20300 {
242				compatible = "marvell,armada-370-wdt";
243				clocks = <&coreclk 2>;
244			};
245
246			cpurst@20800 {
247				compatible = "marvell,armada-370-cpu-reset";
248				reg = <0x20800 0x8>;
249			};
250
251			audio_controller: audio-controller@30000 {
252				compatible = "marvell,armada370-audio";
253				reg = <0x30000 0x4000>;
254				interrupts = <93>;
255				clocks = <&gateclk 0>;
256				clock-names = "internal";
257				status = "disabled";
258			};
259
260			usb@50000 {
261				clocks = <&coreclk 0>;
262			};
263
264			usb@51000 {
265				clocks = <&coreclk 0>;
266			};
267
268			xor@60800 {
269				compatible = "marvell,orion-xor";
270				reg = <0x60800 0x100
271				       0x60A00 0x100>;
272				status = "okay";
273
274				xor00 {
275					interrupts = <51>;
276					dmacap,memcpy;
277					dmacap,xor;
278				};
279				xor01 {
280					interrupts = <52>;
281					dmacap,memcpy;
282					dmacap,xor;
283					dmacap,memset;
284				};
285			};
286
287			xor@60900 {
288				compatible = "marvell,orion-xor";
289				reg = <0x60900 0x100
290				       0x60b00 0x100>;
291				status = "okay";
292
293				xor10 {
294					interrupts = <94>;
295					dmacap,memcpy;
296					dmacap,xor;
297				};
298				xor11 {
299					interrupts = <95>;
300					dmacap,memcpy;
301					dmacap,xor;
302					dmacap,memset;
303				};
304			};
305
306			ethernet@70000 {
307				compatible = "marvell,armada-370-neta";
308			};
309
310			ethernet@74000 {
311				compatible = "marvell,armada-370-neta";
312			};
313		};
314	};
315};
316