Searched refs:CRC (Results 1 – 25 of 42) sorted by relevance
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| /Documentation/ |
| D | crc32.txt | 1 A brief CRC tutorial.
3 A CRC is a long-division remainder. You add the CRC to the message,
4 and the whole thing (message+CRC) is a multiple of the given
5 CRC polynomial. To check the CRC, you can either check that the
6 CRC matches the recomputed value, *or* you can check that the
7 remainder computed on the message+CRC is 0. This latter approach
9 protocols put the end-of-frame flag after the CRC.
18 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
20 CRC is written in hex with the most significant bit omitted. (If you're
23 Note that a CRC is computed over a string of *bits*, so you have
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| /Documentation/arm/Samsung-S3C24XX/ |
| D | Suspend.txt | 114 `S3C2410 PM Suspend Memory CRC`
119 Note, the time to calculate the CRC is dependent on the CPU speed
126 `S3C2410 PM Suspend CRC Chunksize (KiB)`
128 Defines the size of memory each CRC chunk covers. A smaller value
129 will mean that the CRC data block will take more memory, but will
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| /Documentation/EDID/ |
| D | HOWTO.txt | 51 The CRC value in the last line
52 #define CRC 0x55
55 most probably complain about a wrong CRC. Fortunately, the utility also
56 displays the correct CRC which must then be inserted into the source
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| D | 1680x1050.S | 42 #define CRC 0x26 macro
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| D | 1600x1200.S | 42 #define CRC 0x9d macro
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| D | 1280x1024.S | 42 #define CRC 0xa0 macro
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| D | 1920x1080.S | 42 #define CRC 0x05 macro
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| D | 800x600.S | 39 #define CRC 0xc2 macro
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| D | 1024x768.S | 42 #define CRC 0x55 macro
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| D | edid.S | 272 checksum: .byte CRC /* Sum of all bytes must be 0 */
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| /Documentation/w1/slaves/ |
| D | w1_ds28e04 | 15 Support is provided through the sysfs files "eeprom" and "pio". CRC checking
26 to the EEPROM of the DS28E04. If CRC checking mode is enabled only
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| D | w1_ds2423 | 24 was successful and CRC matched.
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| /Documentation/networking/ |
| D | altera_tse.txt | 141 received. This count does not include any error packets such as CRC errors,
146 an integral number of bytes in length and do not pass the CRC test as the frame
151 integral number of bytes in length and do not pass the CRC test as the frame is
257 octets, and had either a bad CRC with an integral number of octets (CRC Error)
258 or a bad CRC with a non-integral number of octets (Alignment Error).
262 in length and had either a bad CRC with an integral number of octets (CRC
263 error) or a bad CRC with a non-integral number of octets (Alignment Error).
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| D | ixgb.txt | 342 Excessive CRC errors may be observed if the Intel(R) PRO/10GbE CX4
345 The CRC errors may be received either by the Intel(R) PRO/10GbE CX4
352 Excessive CRC errors may be observed if the Intel(R) PRO/10GbE CX4 Server
357 Excessive CRC errors may be observed using Fujitsu 24AWG cable assemblies that
358 Are 10 m or longer or where using a Leoni 15 m/24AWG cable assembly. The CRC
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| /Documentation/filesystems/ |
| D | xfs-self-describing-metadata.txt | 83 hence a 32 bit CRC is more than sufficient to detect multi-bit errors in
172 whether CRC validating is necessary. If it is, the CRC32c is calculated and
180 modification made to the object, After this, we calculate the CRC and insert it
192 __be32 crc; /* CRC, not logged */
236 The code ensures that the CRC is only checked if the filesystem has CRCs enabled
237 by checking the superblock of the feature bit, and then if the CRC verifies OK
323 update the LSN field (when it was last modified) and calculate the CRC on the
329 Inodes and dquots are special snowflakes. They have per-object CRC and
332 verification and CRC calculations. The per-buffer verifiers simply perform basic
334 there are magic numbers in all the expected spots. All further CRC and
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| /Documentation/hwmon/ |
| D | sht15 | 50 * If a CRC validation fails, a soft reset command is sent, which resets
58 set it to true to enable CRC validation of the readings (default to false).
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| D | htu21 | 45 Different resolutions, the on-chip heater, using the CRC checksum and reading
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| D | sht21 | 48 Different resolutions, the on-chip heater, using the CRC checksum and reading
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| D | lm90 | 250 Byte), the ADM1032 computes the CRC value over only the second half of
252 of the message belongs to a different transaction. As a result, the CRC
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| /Documentation/kbuild/ |
| D | modules.txt | 429 as a simple ABI consistency check. A CRC value of the full prototype
431 CRC values contained in the kernel are compared with similar values in
443 corresponding CRC value is also stored.
446 <CRC> <Symbol> <module>
450 For a kernel build without CONFIG_MODVERSIONS enabled, the CRC
455 2) It lists the CRC if CONFIG_MODVERSIONS is enabled.
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| /Documentation/block/ |
| D | data-integrity.txt | 56 Also, the 16-bit CRC checksum mandated by both the SCSI and SATA specs
62 The IP checksum received from the OS is converted to the 16-bit CRC
67 The IP checksum is weaker than the CRC in terms of detecting bit
268 E.g. T10-DIF-TYPE1-IP or T13-EPP-0-CRC.
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| /Documentation/w1/masters/ |
| D | omap-hdq | 35 be used to calculate the CRC and pass back an appropriate slave ID to the W1
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 26 bit 8 = set if SEC has the CRC EU (CRCU)
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| /Documentation/dvb/ |
| D | get_dvb_firmware | 805 my $CRC="\x0A\xCC";
813 print FW "$CRC"; # 16bit crc value of main part
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| /Documentation/scsi/ |
| D | cxgb3i.txt | 9 as CRC computation and verification, and direct DMA to the final host memory
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