Searched refs:ALT1 (Results 1 – 5 of 5) sorted by relevance
19 #define ALT1 0x1 macro29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x034 #define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x038 #define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x044 #define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x050 #define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x054 #define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x059 #define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x067 #define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x075 #define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0[all …]
121 tx = <&pio3 4 ALT1 OUT>;122 rx = <&pio3 5 ALT1 IN>;139 sda = <&pio4 6 ALT1 BIDIR>;140 scl = <&pio4 5 ALT1 BIDIR>;148 sda = <&pio5 1 ALT1 BIDIR>;149 scl = <&pio5 0 ALT1 BIDIR>;181 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;182 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;183 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;184 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;[all …]
144 sda = <&PIO4 6 ALT1 BIDIR>;145 scl = <&PIO4 5 ALT1 BIDIR>;162 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;163 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;164 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;165 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;166 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;167 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;168 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;169 col = <&PIO0 7 ALT1 IN BYPASS 1000>;[all …]
124 sda = <&PIO4 6 ALT1 BIDIR>;125 scl = <&PIO4 5 ALT1 BIDIR>;150 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;151 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;152 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;153 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;154 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;155 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;156 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;157 col = <&PIO0 7 ALT1 IN BYPASS 1000>;[all …]
5 #define ALT1 1 macro