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Searched refs:BRIDGE_VIRT_BASE (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-dove/include/mach/
Dbridge-regs.h16 #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
18 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
23 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
27 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
30 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
33 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
52 #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
54 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
Ddove.h78 #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) macro
/arch/arm/mach-mv78xx0/include/mach/
Dbridge-regs.h14 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
17 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
21 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
26 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
34 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
Dmv78xx0.h61 #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) macro
/arch/arm/mach-mv78xx0/
Dcommon.c349 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, in mv78xx0_timer_init()
/arch/arm/mach-dove/
Dcommon.c255 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, in dove_timer_init()