Searched refs:CKSEG1ADDR (Results 1 – 25 of 38) sorted by relevance
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/arch/mips/include/asm/ |
D | sni.h | 38 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) 44 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004) 45 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c) 46 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014) 47 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c) 48 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024) 49 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c) 50 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034) 51 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c) 52 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044) [all …]
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D | addrspace.h | 74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro 81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
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D | vga.h | 17 #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
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/arch/mips/boot/compressed/ |
D | uart-16550.c | 12 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) 17 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) 22 #define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset)) 27 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) 33 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
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/arch/mips/dec/prom/ |
D | identify.c | 73 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn01() 81 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn230() 90 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); in prom_init_kn02() 99 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn02xa() 100 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn02xa() 109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn03() 110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn03()
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/arch/mips/dec/ |
D | ecc-berr.c | 148 (void *)CKSEG1ADDR(address); in dec_ecc_be_backend() 231 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init() 233 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); in dec_kn02_be_init() 234 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); in dec_kn02_be_init() 249 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init() 250 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn03_be_init() 252 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); in dec_kn03_be_init() 253 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); in dec_kn03_be_init()
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D | kn02xa-berr.c | 33 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_ack() 34 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); in dec_kn02xa_be_ack() 44 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_backend() 45 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); in dec_kn02xa_be_backend() 130 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn02xa_be_init()
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D | kn02-irq.c | 34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() 43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() 66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs()
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D | kn01-berr.c | 53 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack() 66 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + in dec_kn01_be_backend() 154 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt() 181 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init()
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D | reset.c | 16 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); in back_to_prom()
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D | int-handler.S | 29 #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR) 30 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL) 31 #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
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/arch/mips/lib/ |
D | uncached.c | 46 usp = CKSEG1ADDR(sp); in run_uncached() 58 ufunc = CKSEG1ADDR(lfunc); in run_uncached()
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/arch/mips/netlogic/common/ |
D | smpboot.S | 63 li t0, CKSEG1ADDR(RESET_VEC_PHYS) 112 li t3, CKSEG1ADDR(RESET_DATA_PHYS) 129 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
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D | reset.S | 54 #define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 168 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 221 li t0, CKSEG1ADDR(RESET_DATA_PHYS) 251 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
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/arch/mips/cobalt/ |
D | setup.c | 83 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); in plat_mem_setup() 117 setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); in prom_init()
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D | reset.c | 20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
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D | pci.c | 38 .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
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/arch/mips/include/asm/mach-cobalt/ |
D | mach-gt64120.h | 25 #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
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/arch/mips/netlogic/xlp/ |
D | setup.c | 165 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); in prom_init() 176 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
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/arch/mips/fw/sni/ |
D | sniprom.c | 33 #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000) 85 return (void *)CKSEG1ADDR(hwconf); in prom_get_hwconf()
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/arch/mips/include/asm/netlogic/xlr/ |
D | iomap.h | 38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
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/arch/mips/jz4740/ |
D | prom.c | 57 #define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
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/arch/mips/sgi-ip22/ |
D | ip22-gio.c | 294 ptr32 = (void *)CKSEG1ADDR(addr); in ip22_gio_id() 304 ptr8 = (void *)CKSEG1ADDR(addr + 3); in ip22_gio_id() 315 ptr16 = (void *)CKSEG1ADDR(addr + 2); in ip22_gio_id() 336 ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); in ip22_is_gr2()
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/arch/mips/include/asm/netlogic/ |
D | common.h | 71 return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset); in nlm_get_boot_data()
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/arch/mips/bcm47xx/ |
D | prom.c | 113 setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); in prom_init()
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