Searched refs:CM_CLKSEL1 (Results 1 – 7 of 7) sorted by relevance
/arch/arm/mach-omap2/ |
D | cm2xxx.c | 372 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); in omap2xxx_cm_get_pll_config() 387 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & in omap2xxx_cm_set_mod_dividers() 389 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); in omap2xxx_cm_set_mod_dividers()
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D | cm2xxx_3xxx.h | 45 #define CM_CLKSEL1 CM_CLKSEL macro
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D | cm3xxx.c | 385 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); in omap3_cm_save_context() 399 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); in omap3_cm_save_context() 518 CM_CLKSEL1); in omap3_cm_restore_context() 532 CM_CLKSEL1); in omap3_cm_restore_context()
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D | cclock3xxx_data.c | 90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 135 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 603 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT, 667 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 698 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 856 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 924 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 1232 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 1240 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2514 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), [all …]
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D | sram34xx.S | 297 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
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D | sram243x.S | 324 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
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D | sram242x.S | 324 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
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