1 /************************************************************************ 2 * Include file for TRIZEPS4 SoM and ConXS eval-board 3 * Copyright (c) Jürgen Schindele 4 * 2006 5 ************************************************************************/ 6 7 /* 8 * Includes/Defines 9 */ 10 #ifndef _TRIPEPS4_H_ 11 #define _TRIPEPS4_H_ 12 13 #include "irqs.h" /* PXA_GPIO_TO_IRQ */ 14 15 /* physical memory regions */ 16 #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ 17 #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ 18 #define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ 19 #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ 20 #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ 21 22 /* Logic on ConXS-board CSFR register*/ 23 #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) 24 /* Logic on ConXS-board BOCR register*/ 25 #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) 26 /* Logic on ConXS-board IRCR register*/ 27 #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) 28 /* Logic on ConXS-board UPSR register*/ 29 #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) 30 /* Logic on ConXS-board DICR register*/ 31 #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) 32 33 /* virtual memory regions */ 34 #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ 35 36 #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ 37 #define TRIZEPS4_CFSR_VIRT 0xF0100000 38 #define TRIZEPS4_BOCR_VIRT 0xF0200000 39 #define TRIZEPS4_DICR_VIRT 0xF0300000 40 #define TRIZEPS4_IRCR_VIRT 0xF0400000 41 #define TRIZEPS4_UPSR_VIRT 0xF0500000 42 43 /* size of flash */ 44 #define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ 45 46 /* Ethernet Controller Davicom DM9000 */ 47 #define GPIO_DM9000 101 48 #define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) 49 50 /* UCB1400 audio / TS-controller */ 51 #define GPIO_UCB1400 1 52 #define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) 53 54 /* PCMCIA socket Compact Flash */ 55 #define GPIO_PCD 11 /* PCMCIA Card Detect */ 56 #define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) 57 #define GPIO_PRDY 13 /* READY / nINT */ 58 #define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) 59 60 /* MMC socket */ 61 #define GPIO_MMC_DET 12 62 #define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) 63 64 /* DOC NAND chip */ 65 #define GPIO_DOC_LOCK 94 66 #define GPIO_DOC_IRQ 93 67 #define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) 68 69 /* SPI interface */ 70 #define GPIO_SPI 53 71 #define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) 72 73 /* LEDS using tx2 / rx2 */ 74 #define GPIO_SYS_BUSY_LED 46 75 #define GPIO_HEARTBEAT_LED 47 76 77 /* Off-module PIC on ConXS board */ 78 #define GPIO_PIC 0 79 #define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) 80 81 #ifdef CONFIG_MACH_TRIZEPS_CONXS 82 /* for CONXS base board define these registers */ 83 #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) 84 #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) 85 86 #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) 87 #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) 88 89 #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) 90 #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) 91 92 #define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) 93 #define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) 94 95 #ifndef __ASSEMBLY__ CFSR_readw(void)96static inline unsigned short CFSR_readw(void) 97 { 98 /* [Compact Flash Status Register] is read only */ 99 return *((unsigned short *)CFSR_P2V(0x0C000000)); 100 } BCR_writew(unsigned short value)101static inline void BCR_writew(unsigned short value) 102 { 103 /* [Board Control Regsiter] is write only */ 104 *((unsigned short *)BCR_P2V(0x0E000000)) = value; 105 } DCR_writew(unsigned short value)106static inline void DCR_writew(unsigned short value) 107 { 108 /* [Display Control Register] is write only */ 109 *((unsigned short *)DCR_P2V(0x0E000000)) = value; 110 } IRCR_writew(unsigned short value)111static inline void IRCR_writew(unsigned short value) 112 { 113 /* [InfraRed data Control Register] is write only */ 114 *((unsigned short *)IRCR_P2V(0x0E000000)) = value; 115 } 116 #else 117 #define ConXS_CFSR CFSR_P2V(0x0C000000) 118 #define ConXS_BCR BCR_P2V(0x0E000000) 119 #define ConXS_DCR DCR_P2V(0x0F800000) 120 #define ConXS_IRCR IRCR_P2V(0x0F800000) 121 #endif 122 #else 123 /* for whatever baseboard define function registers */ CFSR_readw(void)124static inline unsigned short CFSR_readw(void) 125 { 126 return 0; 127 } BCR_writew(unsigned short value)128static inline void BCR_writew(unsigned short value) 129 { 130 ; 131 } DCR_writew(unsigned short value)132static inline void DCR_writew(unsigned short value) 133 { 134 ; 135 } IRCR_writew(unsigned short value)136static inline void IRCR_writew(unsigned short value) 137 { 138 ; 139 } 140 #endif /* CONFIG_MACH_TRIZEPS_CONXS */ 141 142 #define ConXS_CFSR_BVD_MASK 0x0003 143 #define ConXS_CFSR_BVD1 (1 << 0) 144 #define ConXS_CFSR_BVD2 (1 << 1) 145 #define ConXS_CFSR_VS_MASK 0x000C 146 #define ConXS_CFSR_VS1 (1 << 2) 147 #define ConXS_CFSR_VS2 (1 << 3) 148 #define ConXS_CFSR_VS_5V (0x3 << 2) 149 #define ConXS_CFSR_VS_3V3 0x0 150 151 #define ConXS_BCR_S0_POW_EN0 (1 << 0) 152 #define ConXS_BCR_S0_POW_EN1 (1 << 1) 153 #define ConXS_BCR_L_DISP (1 << 4) 154 #define ConXS_BCR_CF_BUF_EN (1 << 5) 155 #define ConXS_BCR_CF_RESET (1 << 7) 156 #define ConXS_BCR_S0_VCC_3V3 0x1 157 #define ConXS_BCR_S0_VCC_5V0 0x2 158 #define ConXS_BCR_S0_VPP_12V 0x4 159 #define ConXS_BCR_S0_VPP_3V3 0x8 160 161 #define ConXS_IRCR_MODE (1 << 0) 162 #define ConXS_IRCR_SD (1 << 1) 163 164 #endif /* _TRIPEPS4_H_ */ 165