Searched refs:DIV4_M1 (Results 1 – 5 of 5) sorted by relevance
| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7724.c | 160 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator
170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
284 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
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| /arch/arm/mach-shmobile/ |
| D | clock-sh7372.c | 315 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, enumerator
327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
430 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
486 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
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| D | clock-r8a7740.c | 316 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, enumerator
325 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
540 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
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| D | clock-r8a73a4.c | 385 DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, enumerator
393 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
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| D | clock-sh73a0.c | 223 enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, enumerator
239 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
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