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Searched refs:DMA8_IRQ_STATUS (Results 1 – 12 of 12) sorted by relevance

/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h342 #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ macro
DcdefBF522.h632 #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
633 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h342 #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ macro
DcdefBF512.h615 #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
616 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h318 #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register … macro
DcdefBF534.h594 #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
595 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h447 #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ macro
DcdefBF538.h716 #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
717 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h344 #define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */ macro
DcdefBF54x_base.h559 #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
560 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h1698 #define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */ macro
DcdefBF60x_base.h643 #define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
644 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)