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Searched refs:DMAC1_TC_PER (Results 1 – 7 of 7) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h309 #define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */ macro
DcdefBF561.h522 #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
523 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h432 #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ macro
DcdefBF538.h694 #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
695 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h692 #define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods … macro
DcdefBF54x_base.h1156 #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
1157 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
/arch/blackfin/kernel/
Ddebug-mmrs.c814 D16(DMAC1_TC_PER); in bfin_debug_mmrs_init()