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Searched refs:EBIU_DDRBWC4 (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h186 #define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */ macro
DcdefBF54x_base.h273 #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
274 #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
/arch/blackfin/kernel/
Ddebug-mmrs.c919 D32(EBIU_DDRBWC4); in bfin_debug_mmrs_init()