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Searched refs:EBIU_DDRBWC7 (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h189 #define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */ macro
DcdefBF54x_base.h279 #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
280 #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
/arch/blackfin/kernel/
Ddebug-mmrs.c922 D32(EBIU_DDRBWC7); in bfin_debug_mmrs_init()