| /arch/sh/include/cpu-sh4/cpu/ |
| D | freq.h | 17 #define FRQCR 0xa4150000 macro
26 #define FRQCR 0xffc80000 macro
31 #define FRQCR 0xffc80000 macro
39 #define FRQCR FRQCRA macro
68 #define FRQCR 0xffc00000 macro
|
| /arch/sh/kernel/cpu/sh3/ |
| D | clock-sh7710.c | 29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
38 int idx = (__raw_readw(FRQCR) & 0x0007); in module_clk_recalc()
48 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8; in bus_clk_recalc()
58 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4; in cpu_clk_recalc()
|
| D | clock-sh7705.c | 35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; in master_clk_init()
44 int idx = __raw_readw(FRQCR) & 0x0003; in module_clk_recalc()
54 int idx = (__raw_readw(FRQCR) & 0x0300) >> 8; in bus_clk_recalc()
64 int idx = (__raw_readw(FRQCR) & 0x0030) >> 4; in cpu_clk_recalc()
|
| D | clock-sh3.c | 31 int frqcr = __raw_readw(FRQCR); in master_clk_init()
43 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
55 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
67 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
|
| D | clock-sh7709.c | 27 int frqcr = __raw_readw(FRQCR); in master_clk_init()
39 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
51 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
64 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
|
| D | clock-sh7706.c | 27 int frqcr = __raw_readw(FRQCR); in master_clk_init()
39 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
51 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
63 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
|
| D | clock-sh7712.c | 26 int frqcr = __raw_readw(FRQCR); in master_clk_init()
38 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
50 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
|
| /arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4.c | 31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
40 int idx = (__raw_readw(FRQCR) & 0x0007); in module_clk_recalc()
50 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007; in bus_clk_recalc()
60 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007; in cpu_clk_recalc()
|
| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7770.c | 24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); in module_clk_recalc()
43 int idx = (__raw_readl(FRQCR) & 0x000f); in bus_clk_recalc()
53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); in cpu_clk_recalc()
|
| D | clock-sh7780.c | 27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
36 int idx = (__raw_readl(FRQCR) & 0x0003); in module_clk_recalc()
46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); in bus_clk_recalc()
56 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); in cpu_clk_recalc()
79 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); in shyway_clk_recalc()
|
| D | clock-sh7763.c | 27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; in master_clk_init()
36 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); in module_clk_recalc()
46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); in bus_clk_recalc()
73 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); in shyway_clk_recalc()
|
| D | clock-sh7722.c | 30 #define FRQCR 0xa4150000 macro
83 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
126 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
127 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
|
| D | clock-sh7366.c | 28 #define FRQCR 0xa4150000 macro
80 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
|
| D | clock-sh7723.c | 31 #define FRQCR 0xa4150000 macro
84 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
127 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
129 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
130 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
|
| D | clock-sh7343.c | 28 #define FRQCR 0xa4150000 macro
79 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
|
| D | clock-sh7757.c | 66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
|
| /arch/sh/boards/mach-hp6xx/ |
| D | pm.c | 57 frqcr = __raw_readw(FRQCR); in pm_enter()
59 __raw_writew(frqcr, FRQCR); in pm_enter()
87 frqcr = __raw_readw(FRQCR); in pm_enter()
89 __raw_writew(frqcr, FRQCR); in pm_enter()
92 __raw_writew(frqcr, FRQCR); in pm_enter()
|
| /arch/sh/include/cpu-sh3/cpu/ |
| D | freq.h | 14 #define FRQCR 0xA415FF80 macro
16 #define FRQCR 0xffffff80 macro
|
| /arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7264.c | 19 #define FRQCR 0xfffe0010 macro
47 return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1]; in pll_recalc()
85 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
87 [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
|
| D | clock-sh7269.c | 19 #define FRQCR 0xfffe0010 macro
113 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
115 [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
|
| /arch/arm/mach-shmobile/include/mach/ |
| D | head-mackerel.txt | 17 LIST "FRQCR"
|