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Searched refs:GEMINI_TIMER_BASE (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-gemini/
Dtime.c45 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
50 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
57 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
75 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
78 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
88 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
91 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
161 writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_init()
Dmm.c32 .virtual = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
33 .pfn = __phys_to_pfn(GEMINI_TIMER_BASE),
/arch/arm/mach-gemini/include/mach/
Dhardware.h29 #define GEMINI_TIMER_BASE 0x43000000 macro
60 #define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE
61 #define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
62 #define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)