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Searched refs:GxICR_LEVEL_0 (Results 1 – 4 of 4) sorted by relevance

/arch/mn10300/include/asm/
Dsmp.h45 #define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0
46 #define SMP_BOOT_GxICR_LV GxICR_LEVEL_0
Dintctl-regs.h49 #define GxICR_LEVEL_0 0x0000 /* - level 0 */ macro
/arch/mn10300/kernel/
Dprofile.c28 set_intr_level(TM11IRQ, GxICR_LEVEL_0); in profile_init()
Dhead.S59 or GxICR_ENABLE|GxICR_LEVEL_0,d3