Searched refs:IRQ (Results 1 – 25 of 78) sorted by relevance
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/arch/sh/boards/mach-microdev/ |
D | irq.c | 44 # error Inconsistancy in defining the IRQ# for Keyboard! 48 # error Inconsistancy in defining the IRQ# for Ethernet! 52 # error Inconsistancy in defining the IRQ# for USB! 56 # error Inconsistancy in defining the IRQ# for PS/2 Mouse! 60 # error Inconsistancy in defining the IRQ# for secondary IDE! 64 # error Inconsistancy in defining the IRQ# for primary IDE!
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/arch/mn10300/include/asm/ |
D | irq.h | 38 #define irq_canonicalize(IRQ) (IRQ) argument
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/arch/blackfin/mach-bf548/ |
D | Kconfig | 189 int "IRQ MXVR Data" 294 int "IRQ Handshake DMA Status" 297 int "IRQ PIXC IN0" 300 int "IRQ PIXC IN1" 303 int "IRQ PIXC OUT" 306 int "IRQ SDH" 309 int "IRQ CNT" 312 int "IRQ KEY" 315 int "IRQ CAN1 RX" 327 int "IRQ USB INT0" [all …]
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/arch/arm/mach-ixp4xx/include/mach/ |
D | entry-macro.S | 19 beq 1001f @ upper IRQ? 23 b 1002f @ lower IRQ being
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/arch/avr32/mach-at32ap/ |
D | at32ap700x.c | 48 #define IRQ(num) \ macro 615 IRQ(2), 629 IRQ(20), 638 IRQ(21), 655 IRQ(19), 764 IRQ(22), 776 IRQ(23), 792 IRQ(13), 799 IRQ(14), 806 IRQ(15), [all …]
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/arch/arc/kernel/ |
D | entry.S | 150 ;##################### Scratch Mem for IRQ stack switching ############# 200 ; if L2 IRQ interrupted a L1 ISR, disable preemption 204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal 568 ; interim IRQ). 590 ; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs 642 ; preempt_schedule_irq() always returns with IRQ disabled 649 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 650 ; IRQ shd definitely not happen between now and rtie 660 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None 687 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier [all …]
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/arch/sh/cchips/ |
D | Kconfig | 29 int "HD64461 IRQ" 33 The default setting of the HD64461 IRQ is 36.
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/arch/powerpc/boot/dts/ |
D | p1023rdb.dts | 159 /* IRQ[0:3] are pulled up on board, set to active-low */ 184 * IRQ[4:6] only for PCIe, set to active-high, 185 * IRQ[7] is pulled up on board, set to active-low 211 * IRQ[8:10] are pulled up on board, set to active-low 212 * IRQ[11] only for PCIe, set to active-high,
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D | media5200.dts | 135 interrupts = <0 0 3 // IRQ bank 0 136 1 1 3>; // IRQ bank 1
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/arch/m68k/q40/ |
D | README | 12 It seems IRQ unmasking can't be safely done on a Q40. IRQ probing 69 Make sure to configure the parallel port as SPP and remove IRQ/DMA jumpers 88 The main interrupt register IIRQ_REG will indicate whether an IRQ was internal 116 that there is no way to find out which IRQ caused a request, [EI]IRQ_REG 117 displays current state of the various IRQ lines.
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/arch/cris/include/arch-v32/arch/ |
D | irq.h | 56 #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
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/arch/arm/boot/dts/ |
D | omap-zoom-common.dtsi | 13 * they probably share the same GPIO IRQ
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D | twl6030_omap4.dtsi | 11 * On most OMAP4 platforms, the twl6030 IRQ line is connected
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D | twl4030_omap3.dtsi | 16 * On most OMAP3 platforms, the twl4030 IRQ line is connected
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D | ste-hrefv60plus.dtsi | 117 /* NFC ENA and RESET to low, pulldown IRQ line */ 186 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
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D | imx53-qsb.dts | 26 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
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D | imx51-digi-connectcore-som.dtsi | 307 MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ 313 MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
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D | omap4-var-som-om44.dtsi | 186 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ 198 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
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/arch/arm/kernel/ |
D | entry-v7m.S | 41 @ Invoke the IRQ handler
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/arch/frv/kernel/ |
D | irq.c | 152 #error dont know external IRQ trigger levels for this setup in init_IRQ()
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/arch/arm/include/asm/hardware/ |
D | entry-macro-iomd.S | 37 2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
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/arch/metag/ |
D | Kconfig.debug | 17 will also use IRQ stacks to compensate for the reduced stackspace.
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/arch/cris/include/arch-v10/arch/ |
D | irq.h | 108 #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
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/arch/arm/mach-w90x900/ |
D | cpu.c | 46 IODESC_ENT(IRQ),
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/arch/arm64/boot/dts/ |
D | apm-storm.dtsi | 88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ 94 <1 13 0xff01>, /* Non-secure Phys IRQ */ 95 <1 14 0xff01>, /* Virt IRQ */ 96 <1 15 0xff01>; /* Hyp IRQ */
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