1 /* 2 * bfin_sport.h - interface to Blackfin SPORTs 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9 #ifndef _UAPI__BFIN_SPORT_H__ 10 #define _UAPI__BFIN_SPORT_H__ 11 12 /* Sport mode: it can be set to TDM, i2s or others */ 13 #define NORM_MODE 0x0 14 #define TDM_MODE 0x1 15 #define I2S_MODE 0x2 16 #define NDSO_MODE 0x3 17 18 /* Data format, normal, a-law or u-law */ 19 #define NORM_FORMAT 0x0 20 #define ALAW_FORMAT 0x2 21 #define ULAW_FORMAT 0x3 22 23 /* Function driver which use sport must initialize the structure */ 24 struct sport_config { 25 /* TDM (multichannels), I2S or other mode */ 26 unsigned int mode:3; 27 unsigned int polled; /* use poll instead of irq when set */ 28 29 /* if TDM mode is selected, channels must be set */ 30 int channels; /* Must be in 8 units */ 31 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ 32 33 /* I2S mode */ 34 unsigned int right_first:1; /* Right stereo channel first */ 35 36 /* In mormal mode, the following item need to be set */ 37 unsigned int lsb_first:1; /* order of transmit or receive data */ 38 unsigned int fsync:1; /* Frame sync required */ 39 unsigned int data_indep:1; /* data independent frame sync generated */ 40 unsigned int act_low:1; /* Active low TFS */ 41 unsigned int late_fsync:1; /* Late frame sync */ 42 unsigned int tckfe:1; 43 unsigned int sec_en:1; /* Secondary side enabled */ 44 45 /* Choose clock source */ 46 unsigned int int_clk:1; /* Internal or external clock */ 47 48 /* If external clock is used, the following fields are ignored */ 49 int serial_clk; 50 int fsync_clk; 51 52 unsigned int data_format:2; /* Normal, u-law or a-law */ 53 54 int word_len; /* How length of the word in bits, 3-32 bits */ 55 int dma_enabled; 56 }; 57 58 /* Userspace interface */ 59 #define SPORT_IOC_MAGIC 'P' 60 #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) 61 #define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long) 62 #define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long) 63 64 65 /* SPORT_TCR1 Masks */ 66 #define TSPEN 0x0001 /* TX enable */ 67 #define ITCLK 0x0002 /* Internal TX Clock Select */ 68 #define TDTYPE 0x000C /* TX Data Formatting Select */ 69 #define DTYPE_NORM 0x0000 /* Data Format Normal */ 70 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 71 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 72 #define TLSBIT 0x0010 /* TX Bit Order */ 73 #define ITFS 0x0200 /* Internal TX Frame Sync Select */ 74 #define TFSR 0x0400 /* TX Frame Sync Required Select */ 75 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ 76 #define LTFS 0x1000 /* Low TX Frame Sync Select */ 77 #define LATFS 0x2000 /* Late TX Frame Sync Select */ 78 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ 79 80 /* SPORT_TCR2 Masks */ 81 #define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */ 82 #define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x) 83 #define EX_SLEN(x) BFIN_EXTRACT(SLEN, x) 84 #define TXSE 0x0100 /* TX Secondary Enable */ 85 #define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ 86 #define TRFST 0x0400 /* TX Right-First Data Order */ 87 88 /* SPORT_RCR1 Masks */ 89 #define RSPEN 0x0001 /* RX enable */ 90 #define IRCLK 0x0002 /* Internal RX Clock Select */ 91 #define RDTYPE 0x000C /* RX Data Formatting Select */ 92 /* DTYPE_* defined above */ 93 #define RLSBIT 0x0010 /* RX Bit Order */ 94 #define IRFS 0x0200 /* Internal RX Frame Sync Select */ 95 #define RFSR 0x0400 /* RX Frame Sync Required Select */ 96 #define LRFS 0x1000 /* Low RX Frame Sync Select */ 97 #define LARFS 0x2000 /* Late RX Frame Sync Select */ 98 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ 99 100 /* SPORT_RCR2 Masks */ 101 /* SLEN defined above */ 102 #define RXSE 0x0100 /* RX Secondary Enable */ 103 #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ 104 #define RRFST 0x0400 /* Right-First Data Order */ 105 106 /* SPORT_STAT Masks */ 107 #define RXNE 0x0001 /* RX FIFO Not Empty Status */ 108 #define RUVF 0x0002 /* RX Underflow Status */ 109 #define ROVF 0x0004 /* RX Overflow Status */ 110 #define TXF 0x0008 /* TX FIFO Full Status */ 111 #define TUVF 0x0010 /* TX Underflow Status */ 112 #define TOVF 0x0020 /* TX Overflow Status */ 113 #define TXHRE 0x0040 /* TX Hold Register Empty */ 114 115 /* SPORT_MCMC1 Masks */ 116 #define SP_WOFF 0x03FF /* Multichannel Window Offset Field */ 117 #define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x) 118 #define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x) 119 #define SP_WSIZE 0xF000 /* Multichannel Window Size Field */ 120 #define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x) 121 #define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x) 122 123 /* SPORT_MCMC2 Masks */ 124 #define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ 125 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ 126 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ 127 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ 128 #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ 129 #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ 130 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ 131 #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ 132 #define MFD 0xF000 /* Multichannel Frame Delay */ 133 #define DP_MFD(x) BFIN_DEPOSIT(MFD, x) 134 #define EX_MFD(x) BFIN_EXTRACT(MFD, x) 135 136 #endif /* _UAPI__BFIN_SPORT_H__ */ 137