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Searched refs:MIPS_CPU_IRQ_BASE (Results 1 – 25 of 65) sorted by relevance

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/arch/mips/include/asm/mach-cobalt/
Dirq.h40 #define MIPS_CPU_IRQ_BASE 16 macro
42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
/arch/mips/include/asm/mach-paravirt/
Dirq.h12 #define MIPS_CPU_IRQ_BASE 1 macro
14 #define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)
16 #define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)
17 #define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)
/arch/mips/include/asm/mach-generic/
Dirq.h23 #ifndef MIPS_CPU_IRQ_BASE
25 #define MIPS_CPU_IRQ_BASE 16 macro
27 #define MIPS_CPU_IRQ_BASE 0 macro
33 #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
/arch/mips/cobalt/
Dirq.c37 do_IRQ(MIPS_CPU_IRQ_BASE + 3); in plat_irq_dispatch()
39 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in plat_irq_dispatch()
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in plat_irq_dispatch()
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in plat_irq_dispatch()
/arch/mips/include/asm/mach-loongson/
Dirq.h9 #define MIPS_CPU_IRQ_BASE 56 macro
11 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
12 #define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
13 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
/arch/mips/kernel/
Dirq_cpu.c43 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); in unmask_mips_irq()
49 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); in mask_mips_irq()
72 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); in mips_mt_cpu_irq_startup()
85 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); in mips_mt_cpu_irq_ack()
115 do_IRQ(MIPS_CPU_IRQ_BASE + irq); in plat_irq_dispatch()
153 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, in __mips_cpu_irq_init()
/arch/mips/loongson/fuloong-2e/
Dirq.c31 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in mach_irq_dispatch()
66 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); in mach_init_irq()
68 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); in mach_init_irq()
/arch/mips/sni/
Dpcit.c214 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in sni_pcit_hwint()
216 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in sni_pcit_hwint()
218 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in sni_pcit_hwint()
228 do_IRQ(MIPS_CPU_IRQ_BASE + 3); in sni_pcit_hwint_cplus()
230 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in sni_pcit_hwint_cplus()
232 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in sni_pcit_hwint_cplus()
234 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in sni_pcit_hwint_cplus()
260 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); in sni_pcit_cplus_irq_init()
/arch/mips/loongson/lemote-2f/
Dirq.c21 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22 #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
23 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
24 #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
/arch/mips/include/asm/mach-db1x00/
Dirq.h16 #ifndef MIPS_CPU_IRQ_BASE
17 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/ralink/
Dirq.c33 #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
34 #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
35 #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
36 #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
37 #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
/arch/mips/include/asm/mach-pnx833x/
Dirq.h48 #define MIPS_CPU_IRQ_BASE 0 macro
49 #define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
/arch/mips/txx9/rbtx4939/
Dirq.c58 return MIPS_CPU_IRQ_BASE + 7; in rbtx4939_irq_dispatch()
68 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4939_irq_dispatch()
70 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4939_irq_dispatch()
/arch/mips/include/asm/mach-loongson1/
Dirq.h19 #define MIPS_CPU_IRQ_BASE 0 macro
20 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
31 #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
/arch/mips/txx9/rbtx4938/
Dirq.c115 irq = MIPS_CPU_IRQ_BASE + 7; in rbtx4938_irq_dispatch()
121 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4938_irq_dispatch()
123 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4938_irq_dispatch()
/arch/mips/txx9/rbtx4927/
Dirq.c177 irq = MIPS_CPU_IRQ_BASE + 7; in rbtx4927_irq_dispatch()
183 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4927_irq_dispatch()
185 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4927_irq_dispatch()
/arch/mips/mti-sead3/
Dsead3-serial.c23 UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */
24 UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */
Dsead3-platform.c23 UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */
24 UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */
Dsead3-time.c89 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; in plat_perf_setup()
97 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; in get_c0_compare_int()
/arch/mips/include/asm/mach-ath79/
Dirq.h12 #define MIPS_CPU_IRQ_BASE 0 macro
15 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
/arch/mips/mti-malta/
Dmalta-int.c294 do_IRQ(MIPS_CPU_IRQ_BASE + irq); in plat_irq_dispatch()
307 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); in ipi_resched_dispatch()
312 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); in ipi_call_dispatch()
518 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); in arch_init_irq()
519 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, in arch_init_irq()
522 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); in arch_init_irq()
523 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, in arch_init_irq()
582 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + in arch_init_irq()
584 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + in arch_init_irq()
/arch/mips/include/asm/mach-bcm63xx/
Dirq.h5 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/include/asm/mips-boards/
Dsead3int.h17 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0)
/arch/mips/include/asm/mach-netlogic/
Dirq.h15 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/include/asm/
Dsni.h144 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
152 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
177 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)

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