Home
last modified time | relevance | path

Searched refs:MOV (Results 1 – 25 of 30) sorted by relevance

12

/arch/metag/tbx/
Dtbidspram.S32 MOV A0.3, D0Ar2
39 DL MOV D0AR.0, #0
44 DL MOV D0Re0, [D0AR.0++]
45 DL MOV D0Ar6, [D0AR.0++]
46 DL MOV D0Ar4, [D0AR.0++]
47 DL MOV D0.5, [D0AR.0++]
53 MOV PC, D1RtP
66 MOV A0.3, D0Ar2
73 DL MOV D0BR.0, #0
78 DL MOV D0Re0, [D0BR.0++]
[all …]
Dtbipcx.S68 MOV D0FrT,A0FrP /* Boing entry sequence */
71 MOV D0Re0,PCX /* Check for repeat call */
77 MOV A0.2,A0StP /* else push context here */
80 MOV D1Re0,D1Ar1 /* and set result to arg */
94 MOV D0Ar6,#0
95 MOV D1Ar5,#0
99 MOV A0FrP,A0.2 /* Restore me! */
110 MOV PCX,A0.2 /* Setup PCX for interrupts */
111 MOV PC,D1Re0 /* Jump to handler */
118 MOV TXSTATUS,D0Re0 /* Restore flags */
[all …]
Dtbisoft.S74 MOV D0FrT,A0FrP /* Boing entry sequence */
88 MOV D0Re0,#0 /* Setup 0:0 result for ASync */
89 MOV D1Re0,#0 /* resume of the thread */
100 MOV D0Re0,D0Ar2 /* Result from args */
101 MOV D1Re0,D1Ar1
110 MOV A0FrP,D0FrT /* Last memory read completes */
111 MOV PC,D1RtP /* Return to caller */
129 MOV D0Re0,D0Ar2 /* Result from args */
130 MOV D1Re0,D1Ar1
152 MOV A0StP,D0Ar6 /* Stack = Frame */
[all …]
Dtbictx.S40 MOV D0Ar6,TXMASKI /* BGNDHALT currently enabled? */
48 MOV D0Re0,D0Ar2 /* Update State argument */
49 MOV D1Re0,D1Ar1 /* with less Ints in TrigMask */
59 MOV D0FrT,A0FrP /* Full entry sequence so we */
63 MOV D0.5,D0Ar2 /* Save State in DX.5 */ define
64 MOV D1.5,D1Ar1 define
68 MOV TXMASKI,D0.6 /* Allow Ints */
69 MOV D0Re0,D0.5 /* Return State */
70 MOV D1Re0,D1.5
73 MOV A0FrP,D0FrT
[all …]
Dtbidefr.S49 MOV D1.5, TXDEFR define
51 MOV D1Ar3, D1.5
70 MOV D1RtP, #TXSTAT_FPE_INVALID_S
74 MOV D1RtP, #1
98 MOV TXDEFR, D1.5
105 MOV PC,D1RtP
119 MOV D1Ar3, D0Ar4
140 MOV D0Re0, #TXSTAT_FPE_INVALID_S
155 MOV D0Re0, TXDEFR
169 MOV PC,D0Re0
Dtbitimer.S65 MOV D1Ar5,#TIMER_SET_BIT /* Timer SET request */
71 MOV PC,D1RtP /* Return */
90 MOV D1Ar5,#0 /* Timer GET request */
96 MOV PC,D1RtP /* Return */
114 MOV D1Ar5,#TIMER_ADD_BIT /* Timer ADD request */
124 MOV PC,D1RtP /* Return */
146 MOV D1Ar5,#TIMER_SET_BIT /* Timer SET request */
149 MOV D0Re0,D0Ar6 /* Old value read = result */
156 MOV PC,D1RtP /* Return */
181 MOV A1.3,A1LbP /* Get ___TBITimes address */
[all …]
Dtbictxfpu.S52 MOV D0Ar6, TXENABLE
62 MOV D0Ar6, TXDEFR
69 MOV D0Ar6, TXMODE
102 MOV D0Re0, D1Ar3 /* Return end of save area */
103 MOV PC, D1RtP
143 MOV D0Ar6, D1Ar5
149 MOV D1Ar5, TXDEFR
153 MOV TXDEFR, D1Re0
156 MOV D1Ar5, TXMODE
160 MOV TXMODE, D0Ar6
[all …]
Dtbicore.S42 MOV PC,D1RtP
60 MOV D0Re0,TXSTATUS /* What priv level are we at? */
74 MOV PC,D1RtP /* Return */
94 MOV D1RtP,PC /* Setup return address to form loop */
98 MOV PC,D1RtP /* Return */
114 MOV D1Re0,#0 /* Prepare to disable ints */
128 MOV TXMASKI,D1Re0 /* Allow ints */
131 MOV PC,D1RtP /* Return (NZ indicates failure) */
Dtbilogf.S26 MOV D0Re0,#0
28 MOV PC,D1RtP
39 MOV D0Ar6,#1
43 MOV PC,D1RtP /* Return */
Dtbiroot.S51 MOV PC,D1RtP
68 MOV D1Re0,TXSTATUS /* Are we privileged or int? */
69 MOV D0Re0,TXENABLE /* Which thread are we? */
80 MOV PC,D1RtP /* Return */
/arch/metag/lib/
Dmemmove.S12 MOV D0Re0, D1Ar1
15 MOV D1Ar5, D0Ar2
23 MOV D1Re0, D0Ar2
28 MOV A1.2, D0Ar2
29 MOV A0.2, D1Ar1
33 MOV D0Ar4, D0Ar2
34 MOV D1Ar5, D1Ar1
59 MOV D0Re0, A0.2
65 MOV PC, D1RtP
78 MOV D0Ar4, A1.2
[all …]
Dmodsi3.S14 MOV D0FrT,D1RtP ! Save original return address
16 MOV D1RtP,D0FrT ! Recover return address
17 MOV D0Re0,D1Ar1 ! Return remainder
18 MOV PC,D1RtP
28 MOV D0FrT,D1RtP ! Save original return address
29 MOV A0.2,D1Ar1 ! Save A in A0.2
31 MOV D1RtP,D0FrT ! Recover return address
32 MOV D1Re0,A0.2 ! Recover A
33 MOV D0Re0,D1Ar1 ! Return remainder
37 MOV PC, D1RtP
Ddiv64.S15 MOV D0Re0,D0Ar2
16 MOV D1Re0,D1Ar1
17 MOV PC,D1RtP
21 MOV D0Re0,#1
22 MOV D1Re0,#0
32 MOV D0Ar4,D0Ar6
33 MOV D1Ar3,D1Ar5
42 MOV D0Ar6,#0
43 MOV D1Ar5,D0Ar6
69 MOV D0Re0,D0Ar6
[all …]
Dmemcpy.S12 MOV A1.2, D0Ar2 ! source pointer
13 MOV A0.2, D1Ar1 ! destination pointer
14 MOV A0.3, D1Ar1 ! for return value
29 MOV D0Re0, A0.3
30 MOV PC, D1RtP
52 MOV D0Ar4, A1.2
84 MOV D0Ar4, A1.2
85 MOV D0Ar6, A1.2
87 MOV A1.2, D0Ar4
90 MOV D0Ar4, D0Ar6
[all …]
Dlshrdi3.S11 MOV D0Re0,D0Ar2
12 MOV D1Re0,D1Ar1
16 MOV D0Ar4,D1Ar3
27 MOV PC,D1RtP
31 MOV D1Re0,#0 ! HI = 0
32 MOV PC,D1RtP
Dclear_page.S10 MOV TXRPT,#((PAGE_SIZE / 8) - 1)
11 MOV D0Re0,#0
12 MOV D1Re0,#0
16 MOV PC,D1RtP
Dashldi3.S11 MOV D0Re0,D0Ar2
12 MOV D1Re0,D1Ar1
26 MOV PC,D1RtP
31 MOV D0Re0,#0 ! LO = 0
32 MOV PC,D1RtP
Dashrdi3.S11 MOV D0Re0,D0Ar2
12 MOV D1Re0,D1Ar1
16 MOV D0Ar4,D1Ar3
27 MOV PC,D1RtP
32 MOV PC,D1RtP
Dcmpdi2.S15 MOV D0Re0,#1
25 MOV PC,D1RtP
31 MOV PC,D1RtP
Ddivsi3.S15 MOV D1Re0,D0Ar2 ! Au already in A1Ar1, Bu -> D1Re0
16 MOV D0Re0,#0 ! Result is 0
17 MOV D0Ar4,#0 ! Return positive result
31 MOV D1Re0,D0Ar2 ! A already in A1Ar1, B -> D1Re0
32 MOV D0Re0,#0 ! Result is 0
56 MOV PC,D1RtP
68 MOV D0Ar6,#1 ! Set curbit to 1
80 MOV D0Ar2,D1Ar3 ! copy into bank 0
99 MOV PC,D1RtP
Dmemset.S16 MOV D0Re0,D1Ar1 ! Return dst
21 MOV D0Ar2,#8 ! Need 8 - N in D1Ar5 ...
33 MOV A1.2,A0.2
50 MOV D1Ar5,D1Ar3
70 MOV A1.2,D1Ar5
84 MOV PC,D1RtP
Dcopy_page.S11 MOV D0FrT,#PAGE_SIZE
19 MOV PC,D1RtP
/arch/metag/kernel/
Dftrace_stub.S14 MOV PC,D0.4
20 MOV D1Ar1, D0.4
21 MOV D0Ar2, D1RtP
32 MOV PC, D0.4
39 MOV D1Ar1, D0.4
40 MOV D0Ar2, D1RtP
48 MOV D1RtP,D1Ar3
56 MOV PC, D0.4
62 MOV PC,D1RtP
Dhead.S24 MOV A0FrP,#0
25 MOV D0Re0,#0
26 MOV D1Re0,#0
27 MOV D1Ar3,#0
28 MOV D1Ar1,D0Ar4 !Store kernel boot params
29 MOV D1Ar5,#0
30 MOV D0Ar6,#0
32 MOV D0.8,#0 define
56 MOV D1Re0,#0
Duser_gateway.S41 MOV D1Ar3,TXENABLE
46 MOV PC,D1RtP
81 1: MOV D0Re0,#1
83 MOV PC,D1RtP
89 MOV D0Re0,#1
91 MOV PC,D1RtP

12