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Searched refs:MSTPCR1 (Results 1 – 15 of 15) sorted by relevance

/arch/sh/kernel/cpu/sh4a/
Dclock-sh7757.c79 #define MSTPCR1 0xffc80034 macro
92 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
93 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
94 [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
95 [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
96 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
97 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
98 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
99 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
Dclock-sh7786.c83 #define MSTPCR1 0xffc40034 macro
118 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
119 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
120 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
121 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
122 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
123 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
124 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
Dclock-sh7734.c85 #define MSTPCR1 0xFFC80034 macro
149 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
150 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
151 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
152 [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
153 [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
154 [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
155 [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
156 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
157 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
Dclock-sh7785.c84 #define MSTPCR1 0xffc80034 macro
112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
Dclock-shx3.c77 #define MSTPCR1 0xffc00034 macro
98 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
99 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
Dclock-sh7724.c39 #define MSTPCR1 0xa4150034 macro
241 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
242 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
243 [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
244 [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
Dclock-sh7722.c37 #define MSTPCR1 0xa4150034 macro
164 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
165 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
Dclock-sh7723.c38 #define MSTPCR1 0xa4150034 macro
182 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
183 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
Dclock-sh7343.c34 #define MSTPCR1 0xa4150034 macro
175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
Dclock-sh7366.c34 #define MSTPCR1 0xa4150034 macro
176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
/arch/arm/mach-shmobile/
Dclock-r8a7779.c54 #define MSTPCR1 IOMEM(0xffc80034) macro
123 [MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
124 [MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
125 [MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
126 [MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
127 [MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
128 [MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */
129 [MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */
130 [MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */
131 [MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */
[all …]
Dclock-r8a7778.c46 #define MSTPCR1 IOMEM(0xffc80034) macro
152 [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
153 [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
154 [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */
155 [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */
/arch/sh/include/cpu-sh4/cpu/
Dfreq.h23 #define MSTPCR1 0xa4150034 macro
47 #define MSTPCR1 0xa4150034 macro
/arch/sh/include/mach-common/mach/
Dsh7763rdp.h18 #define MSTPCR1 0xFFC80038 macro
/arch/sh/boards/mach-sh7763rdp/
Dsetup.c208 __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1); in sh7763rdp_setup()