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Searched refs:PLL_MOD (Results 1 – 9 of 9) sorted by relevance

/arch/arm/mach-omap2/
Dcm2xxx.c85 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_dpll_autoidle()
88 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_dpll_autoidle()
109 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_apll_autoidle()
112 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_apll_autoidle()
146 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in _omap2xxx_apll_enable()
151 omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); in _omap2xxx_apll_enable()
153 omap2xxx_cm_wait_module_ready(PLL_MOD, 1, status_bit); in _omap2xxx_apll_enable()
167 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in _omap2xxx_apll_disable()
169 omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); in _omap2xxx_apll_disable()
359 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); in omap2xxx_cm_get_core_clk_src()
[all …]
Dcm3xxx.c410 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); in omap3_cm_save_context()
412 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); in omap3_cm_save_context()
414 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); in omap3_cm_save_context()
416 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); in omap3_cm_save_context()
418 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); in omap3_cm_save_context()
540 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, in omap3_cm_restore_context()
542 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, in omap3_cm_restore_context()
544 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, in omap3_cm_restore_context()
546 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, in omap3_cm_restore_context()
548 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, in omap3_cm_restore_context()
[all …]
Dcclock3xxx_data.c90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
135 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
316 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
322 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
328 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
330 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
338 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
[all …]
Dpowerdomains3xxx_data.c323 .prcm_offs = PLL_MOD,
329 .prcm_offs = PLL_MOD,
335 .prcm_offs = PLL_MOD,
Dsram243x.S131 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
226 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
320 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
322 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
324 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dsram242x.S131 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
226 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
320 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
322 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
324 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dprcm-common.h30 #define PLL_MOD 0x500 macro
42 #define OMAP3430_CCR_MOD PLL_MOD
Dsram34xx.S297 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dsleep34xx.S47 #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)