Searched refs:REG_OFFSET (Results 1 – 18 of 18) sorted by relevance
| /arch/arm64/kvm/ |
| D | regmap.c | 28 #define REG_OFFSET(_reg) \ macro
31 #define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
41 REG_OFFSET(pc)
49 REG_OFFSET(compat_r8_fiq), /* r8 */
50 REG_OFFSET(compat_r9_fiq), /* r9 */
51 REG_OFFSET(compat_r10_fiq), /* r10 */
52 REG_OFFSET(compat_r11_fiq), /* r11 */
53 REG_OFFSET(compat_r12_fiq), /* r12 */
54 REG_OFFSET(compat_sp_fiq), /* r13 */
55 REG_OFFSET(compat_lr_fiq), /* r14 */
[all …]
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| /arch/arm/kvm/ |
| D | emulate.c | 35 #define REG_OFFSET(_reg) \ macro
38 #define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
55 REG_OFFSET(fiq_regs[0]), /* r8 */
56 REG_OFFSET(fiq_regs[1]), /* r9 */
57 REG_OFFSET(fiq_regs[2]), /* r10 */
58 REG_OFFSET(fiq_regs[3]), /* r11 */
59 REG_OFFSET(fiq_regs[4]), /* r12 */
60 REG_OFFSET(fiq_regs[5]), /* r13 */
61 REG_OFFSET(fiq_regs[6]), /* r14 */
71 REG_OFFSET(irq_regs[0]), /* r13 */
[all …]
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| /arch/mips/ar7/ |
| D | irq.c | 32 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) macro
35 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
37 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
39 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
43 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
44 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
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| /arch/arm/mach-ixp4xx/ |
| D | gtwx5715-setup.c | 83 #define REG_OFFSET 3 macro
85 #define REG_OFFSET 0 macro
110 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | coyote-setup.c | 64 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
101 (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET); in coyote_init()
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| D | avila-setup.c | 81 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
90 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | dsmg600-setup.c | 130 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
139 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | vulcan-setup.c | 80 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
89 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | nas100d-setup.c | 132 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
141 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | nslu2-setup.c | 144 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
153 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | omixp-setup.c | 128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
136 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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| D | fsg-setup.c | 92 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
101 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | wg302v2-setup.c | 59 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | gateway7001-setup.c | 58 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | ixdp425-setup.c | 154 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
163 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | goramo_mlr.c | 251 REG_OFFSET,
261 REG_OFFSET,
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| /arch/arm/mach-ixp4xx/include/mach/ |
| D | platform.h | 21 #define REG_OFFSET 0 macro
23 #define REG_OFFSET 3 macro
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| /arch/ia64/hp/sim/boot/ |
| D | fw-emu.c | 106 #define REG_OFFSET(addr) (0x00000000000000FF & (addr)) macro
202 r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3))); in sal_emulator()
204 r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2))); in sal_emulator()
216 outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3))); in sal_emulator()
218 outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2))); in sal_emulator()
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