/arch/mips/mm/ |
D | uasm-micromips.c | 44 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, 45 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 46 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, 47 { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 48 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 50 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, 52 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, 54 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, 55 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, 58 { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS }, [all …]
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D | uasm-mips.c | 52 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 53 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 54 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 55 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, 56 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 57 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 58 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 59 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 60 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, 61 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, [all …]
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D | uasm.c | 17 RS = 0x001, enumerator
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/arch/powerpc/xmon/ |
D | ppc-opc.c | 422 #define RS RBS + 1 macro 423 #define RT RS 429 #define RSQ RS + 1 2073 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, 2074 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, 2075 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, 2076 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, 2077 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, 2078 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, 2079 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, [all …]
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/arch/powerpc/platforms/powermac/ |
D | time.c | 53 #define RS 0x200 /* skip between registers */ macro 54 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ 55 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ 56 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ 57 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ 58 #define ACR (11*RS) /* Auxiliary control register */ 59 #define IFR (13*RS) /* Interrupt flag register */
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/arch/powerpc/include/asm/ |
D | asm-compat.h | 32 #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS) argument
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D | ppc_asm.h | 410 #define MTOCRF(FXM, RS) \ argument 412 mtcrf (FXM), RS; \ 414 mtocrf (FXM), RS; \
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/arch/m68k/fpsp040/ |
D | stan.S | 236 fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3)) 241 faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3)) 274 fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3)) 279 faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
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/arch/cris/arch-v10/drivers/ |
D | Kconfig | 381 bool "RS-485 support" 384 Enables support for RS-485 serial communication. For a primer on 385 RS-485, see <http://en.wikipedia.org/wiki/Rs485> 388 bool "RS-485 mode on PA" 396 int "RS-485 mode on PA bit"
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/arch/cris/arch-v32/drivers/ |
D | Kconfig | 31 bool "RS-485 support" 34 Enables support for RS-485 serial communication.
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/arch/powerpc/ |
D | Kconfig | 706 have an IBM RS/6000 or pSeries machine, say Y. If you have an 778 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
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/arch/m68k/ifpsp060/src/ |
D | fplsp.S | 5822 fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3)) 5826 fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3)) 5859 fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3)) 5863 fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3))
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