1 /* 2 * SCC (Super Companion Chip) definitions 3 * 4 * (C) Copyright 2004-2006 TOSHIBA CORPORATION 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef _CELLEB_SCC_H 22 #define _CELLEB_SCC_H 23 24 #define PCI_VENDOR_ID_TOSHIBA_2 0x102f 25 #define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0 26 #define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1 27 #define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2 28 #define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3 29 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 30 #define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5 31 #define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6 32 #define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7 33 34 #define SCC_EPCI_REG 0x0000d000 35 36 /* EPCI registers */ 37 #define SCC_EPCI_CNF10_REG 0x010 38 #define SCC_EPCI_CNF14_REG 0x014 39 #define SCC_EPCI_CNF18_REG 0x018 40 #define SCC_EPCI_PVBAT 0x100 41 #define SCC_EPCI_VPMBAT 0x104 42 #define SCC_EPCI_VPIBAT 0x108 43 #define SCC_EPCI_VCSR 0x110 44 #define SCC_EPCI_VIENAB 0x114 45 #define SCC_EPCI_VISTAT 0x118 46 #define SCC_EPCI_VRDCOUNT 0x124 47 #define SCC_EPCI_BAM0 0x12c 48 #define SCC_EPCI_BAM1 0x134 49 #define SCC_EPCI_BAM2 0x13c 50 #define SCC_EPCI_IADR 0x164 51 #define SCC_EPCI_CLKRST 0x800 52 #define SCC_EPCI_INTSET 0x804 53 #define SCC_EPCI_STATUS 0x808 54 #define SCC_EPCI_ABTSET 0x80c 55 #define SCC_EPCI_WATRP 0x810 56 #define SCC_EPCI_DUMYRADR 0x814 57 #define SCC_EPCI_SWRESP 0x818 58 #define SCC_EPCI_CNTOPT 0x81c 59 #define SCC_EPCI_ECMODE 0xf00 60 #define SCC_EPCI_IOM_AC_NUM 5 61 #define SCC_EPCI_IOM_ACTE(n) (0xf10 + (n) * 4) 62 #define SCC_EPCI_IOT_AC_NUM 4 63 #define SCC_EPCI_IOT_ACTE(n) (0xf30 + (n) * 4) 64 #define SCC_EPCI_MAEA 0xf50 65 #define SCC_EPCI_MAEC 0xf54 66 #define SCC_EPCI_CKCTRL 0xff0 67 68 /* bits for SCC_EPCI_VCSR */ 69 #define SCC_EPCI_VCSR_FRE 0x00020000 70 #define SCC_EPCI_VCSR_FWE 0x00010000 71 #define SCC_EPCI_VCSR_DR 0x00000400 72 #define SCC_EPCI_VCSR_SR 0x00000008 73 #define SCC_EPCI_VCSR_AT 0x00000004 74 75 /* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */ 76 #define SCC_EPCI_VISTAT_PMPE 0x00000008 77 #define SCC_EPCI_VISTAT_PMFE 0x00000004 78 #define SCC_EPCI_VISTAT_PRA 0x00000002 79 #define SCC_EPCI_VISTAT_PRD 0x00000001 80 #define SCC_EPCI_VISTAT_ALL 0x0000000f 81 82 #define SCC_EPCI_VIENAB_PMPEE 0x00000008 83 #define SCC_EPCI_VIENAB_PMFEE 0x00000004 84 #define SCC_EPCI_VIENAB_PRA 0x00000002 85 #define SCC_EPCI_VIENAB_PRD 0x00000001 86 #define SCC_EPCI_VIENAB_ALL 0x0000000f 87 88 /* bits for SCC_EPCI_CLKRST */ 89 #define SCC_EPCI_CLKRST_CKS_MASK 0x00030000 90 #define SCC_EPCI_CLKRST_CKS_2 0x00000000 91 #define SCC_EPCI_CLKRST_CKS_4 0x00010000 92 #define SCC_EPCI_CLKRST_CKS_8 0x00020000 93 #define SCC_EPCI_CLKRST_PCICRST 0x00000400 94 #define SCC_EPCI_CLKRST_BC 0x00000200 95 #define SCC_EPCI_CLKRST_PCIRST 0x00000100 96 #define SCC_EPCI_CLKRST_PCKEN 0x00000001 97 98 /* bits for SCC_EPCI_INTSET/SCC_EPCI_STATUS */ 99 #define SCC_EPCI_INT_2M 0x01000000 100 #define SCC_EPCI_INT_RERR 0x00200000 101 #define SCC_EPCI_INT_SERR 0x00100000 102 #define SCC_EPCI_INT_PRTER 0x00080000 103 #define SCC_EPCI_INT_SER 0x00040000 104 #define SCC_EPCI_INT_PER 0x00020000 105 #define SCC_EPCI_INT_PAI 0x00010000 106 #define SCC_EPCI_INT_1M 0x00000100 107 #define SCC_EPCI_INT_PME 0x00000010 108 #define SCC_EPCI_INT_INTD 0x00000008 109 #define SCC_EPCI_INT_INTC 0x00000004 110 #define SCC_EPCI_INT_INTB 0x00000002 111 #define SCC_EPCI_INT_INTA 0x00000001 112 #define SCC_EPCI_INT_DEVINT 0x0000000f 113 #define SCC_EPCI_INT_ALL 0x003f001f 114 #define SCC_EPCI_INT_ALLERR 0x003f0000 115 116 /* bits for SCC_EPCI_CKCTRL */ 117 #define SCC_EPCI_CKCTRL_CRST0 0x00010000 118 #define SCC_EPCI_CKCTRL_CRST1 0x00020000 119 #define SCC_EPCI_CKCTRL_OCLKEN 0x00000100 120 #define SCC_EPCI_CKCTRL_LCLKEN 0x00000001 121 122 #define SCC_EPCI_IDSEL_AD_TO_SLOT(ad) ((ad) - 10) 123 #define SCC_EPCI_MAX_DEVNU SCC_EPCI_IDSEL_AD_TO_SLOT(32) 124 125 /* bits for SCC_EPCI_CNTOPT */ 126 #define SCC_EPCI_CNTOPT_O2PMB 0x00000002 127 128 /* SCC PCIEXC SMMIO registers */ 129 #define PEXCADRS 0x000 130 #define PEXCWDATA 0x004 131 #define PEXCRDATA 0x008 132 #define PEXDADRS 0x010 133 #define PEXDCMND 0x014 134 #define PEXDWDATA 0x018 135 #define PEXDRDATA 0x01c 136 #define PEXREQID 0x020 137 #define PEXTIDMAP 0x024 138 #define PEXINTMASK 0x028 139 #define PEXINTSTS 0x02c 140 #define PEXAERRMASK 0x030 141 #define PEXAERRSTS 0x034 142 #define PEXPRERRMASK 0x040 143 #define PEXPRERRSTS 0x044 144 #define PEXPRERRID01 0x048 145 #define PEXPRERRID23 0x04c 146 #define PEXVDMASK 0x050 147 #define PEXVDSTS 0x054 148 #define PEXRCVCPLIDA 0x060 149 #define PEXLENERRIDA 0x068 150 #define PEXPHYPLLST 0x070 151 #define PEXDMRDEN0 0x100 152 #define PEXDMRDADR0 0x104 153 #define PEXDMRDENX 0x110 154 #define PEXDMRDADRX 0x114 155 #define PEXECMODE 0xf00 156 #define PEXMAEA(n) (0xf50 + (8 * n)) 157 #define PEXMAEC(n) (0xf54 + (8 * n)) 158 #define PEXCCRCTRL 0xff0 159 160 /* SCC PCIEXC bits and shifts for PEXCADRS */ 161 #define PEXCADRS_BYTE_EN_SHIFT 20 162 #define PEXCADRS_CMD_SHIFT 16 163 #define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT) 164 #define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT) 165 166 /* SCC PCIEXC shifts for PEXDADRS */ 167 #define PEXDADRS_BUSNO_SHIFT 20 168 #define PEXDADRS_DEVNO_SHIFT 15 169 #define PEXDADRS_FUNCNO_SHIFT 12 170 171 /* SCC PCIEXC bits and shifts for PEXDCMND */ 172 #define PEXDCMND_BYTE_EN_SHIFT 4 173 #define PEXDCMND_IO_READ 0x2 174 #define PEXDCMND_IO_WRITE 0x3 175 #define PEXDCMND_CONFIG_READ 0xa 176 #define PEXDCMND_CONFIG_WRITE 0xb 177 178 /* SCC PCIEXC bits for PEXPHYPLLST */ 179 #define PEXPHYPLLST_PEXPHYAPLLST 0x00000001 180 181 /* SCC PCIEXC bits for PEXECMODE */ 182 #define PEXECMODE_ALL_THROUGH 0x00000000 183 #define PEXECMODE_ALL_8BIT 0x00550155 184 #define PEXECMODE_ALL_16BIT 0x00aa02aa 185 186 /* SCC PCIEXC bits for PEXCCRCTRL */ 187 #define PEXCCRCTRL_PEXIPCOREEN 0x00040000 188 #define PEXCCRCTRL_PEXIPCONTEN 0x00020000 189 #define PEXCCRCTRL_PEXPHYPLLEN 0x00010000 190 #define PEXCCRCTRL_PCIEXCAOCKEN 0x00000100 191 192 /* SCC PCIEXC port configuration registers */ 193 #define PEXTCERRCHK 0x21c 194 #define PEXTAMAPB0 0x220 195 #define PEXTAMAPL0 0x224 196 #define PEXTAMAPB(n) (PEXTAMAPB0 + 8 * (n)) 197 #define PEXTAMAPL(n) (PEXTAMAPL0 + 8 * (n)) 198 #define PEXCHVC0P 0x500 199 #define PEXCHVC0NP 0x504 200 #define PEXCHVC0C 0x508 201 #define PEXCDVC0P 0x50c 202 #define PEXCDVC0NP 0x510 203 #define PEXCDVC0C 0x514 204 #define PEXCHVCXP 0x518 205 #define PEXCHVCXNP 0x51c 206 #define PEXCHVCXC 0x520 207 #define PEXCDVCXP 0x524 208 #define PEXCDVCXNP 0x528 209 #define PEXCDVCXC 0x52c 210 #define PEXCTTRG 0x530 211 #define PEXTSCTRL 0x700 212 #define PEXTSSTS 0x704 213 #define PEXSKPCTRL 0x708 214 215 /* UHC registers */ 216 #define SCC_UHC_CKRCTRL 0xff0 217 #define SCC_UHC_ECMODE 0xf00 218 219 /* bits for SCC_UHC_CKRCTRL */ 220 #define SCC_UHC_F48MCKLEN 0x00000001 221 #define SCC_UHC_P_SUSPEND 0x00000002 222 #define SCC_UHC_PHY_SUSPEND_SEL 0x00000004 223 #define SCC_UHC_HCLKEN 0x00000100 224 #define SCC_UHC_USBEN 0x00010000 225 #define SCC_UHC_USBCEN 0x00020000 226 #define SCC_UHC_PHYEN 0x00040000 227 228 /* bits for SCC_UHC_ECMODE */ 229 #define SCC_UHC_ECMODE_BY_BYTE 0x00000555 230 #define SCC_UHC_ECMODE_BY_WORD 0x00000aaa 231 232 #endif /* _CELLEB_SCC_H */ 233