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Searched refs:SET (Results 1 – 13 of 13) sorted by relevance

/arch/arm/mach-imx/
Dclk-pfd.c38 #define SET 0x4 macro
55 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); in clk_pfd_disable()
107 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); in clk_pfd_set_rate()
/arch/mips/mm/
Duasm-mips.c75 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
76 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
111 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
112 { insn_mfhc0, M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
115 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
116 { insn_mthc0, M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
219 if (ip->fields & SET) in build_insn()
Duasm-micromips.c194 if (ip->fields & SET) in build_insn()
Duasm.c26 SET = 0x200, enumerator
/arch/arm/boot/compressed/
Dhead-sharpsl.S130 bic r3, r3, #0x11 @ SET NCE
131 orr r3, r3, #0x0a @ SET CLR + FLWP
136 orr r3, r3, #4 @ SET ALE
/arch/metag/tbx/
Dtbicore.S118 SET [A0.3+#UON],D1RtP /* Stop shared memory access too */
126 SET [A0.3+#UOFF],D1RtP /* Allow shared memory access */
/arch/c6x/kernel/
Dentry.S38 SET .S2 reg,0,0,reg
249 SET .S2 B1,0,0,B1
/arch/m68k/fpsp040/
Dssin.S170 |--SET ADJN TO 0
176 |--SET ADJN TO 1
533 |--SET ADJN TO 4
Dsatan.S282 oril #0x04000000,XFRAC(%a6) | ...SET 6-TH BIT TO 1
/arch/metag/
DKconfig141 to be accessed by normal GET/SET instructions too.
/arch/blackfin/kernel/
Ddebug-mmrs.c364 __PORT(SET, data_set); in bfin_debug_mmrs_port()
373 __PORT(SET, data_set); in bfin_debug_mmrs_port()
/arch/m68k/ifpsp060/src/
Dfplsp.S5016 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0
5022 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1
6275 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE
Dfpsp.S5342 #--SET ADJN TO 4
6388 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1