Searched refs:SET (Results 1 – 13 of 13) sorted by relevance
/arch/arm/mach-imx/ |
D | clk-pfd.c | 38 #define SET 0x4 macro 55 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); in clk_pfd_disable() 107 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); in clk_pfd_set_rate()
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/arch/mips/mm/ |
D | uasm-mips.c | 75 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 76 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 111 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 112 { insn_mfhc0, M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, 115 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 116 { insn_mthc0, M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET}, 219 if (ip->fields & SET) in build_insn()
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D | uasm-micromips.c | 194 if (ip->fields & SET) in build_insn()
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D | uasm.c | 26 SET = 0x200, enumerator
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/arch/arm/boot/compressed/ |
D | head-sharpsl.S | 130 bic r3, r3, #0x11 @ SET NCE 131 orr r3, r3, #0x0a @ SET CLR + FLWP 136 orr r3, r3, #4 @ SET ALE
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/arch/metag/tbx/ |
D | tbicore.S | 118 SET [A0.3+#UON],D1RtP /* Stop shared memory access too */ 126 SET [A0.3+#UOFF],D1RtP /* Allow shared memory access */
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/arch/c6x/kernel/ |
D | entry.S | 38 SET .S2 reg,0,0,reg 249 SET .S2 B1,0,0,B1
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/arch/m68k/fpsp040/ |
D | ssin.S | 170 |--SET ADJN TO 0 176 |--SET ADJN TO 1 533 |--SET ADJN TO 4
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D | satan.S | 282 oril #0x04000000,XFRAC(%a6) | ...SET 6-TH BIT TO 1
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/arch/metag/ |
D | Kconfig | 141 to be accessed by normal GET/SET instructions too.
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/arch/blackfin/kernel/ |
D | debug-mmrs.c | 364 __PORT(SET, data_set); in bfin_debug_mmrs_port() 373 __PORT(SET, data_set); in bfin_debug_mmrs_port()
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/arch/m68k/ifpsp060/src/ |
D | fplsp.S | 5016 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 5022 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 6275 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE
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D | fpsp.S | 5342 #--SET ADJN TO 4 6388 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1
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