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Searched refs:SIC_ISR0 (Results 1 – 12 of 12) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
Dblackfin.h36 #define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
37 #define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
DdefBF561.h43 #define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ macro
DcdefBF561.h52 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
53 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
/arch/blackfin/mach-bf518/include/mach/
DcdefBF512.h45 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
46 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
47 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
48 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
DdefBF512.h32 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/arch/blackfin/mach-bf527/include/mach/
DcdefBF522.h45 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
46 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
47 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
48 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
DdefBF522.h35 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/arch/blackfin/mach-bf538/include/mach/
DcdefBF538.h34 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
35 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
38 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
39 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
DdefBF538.h32 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h42 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ macro
DcdefBF54x_base.h50 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
51 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
56 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
57 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1491 D32(SIC_ISR0); in bfin_debug_mmrs_init()