Searched refs:SIC_IWR0 (Results 1 – 17 of 17) sorted by relevance
| /arch/blackfin/mach-bf561/include/mach/ |
| D | pll.h | 26 bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0); in bfin_iwr_restore()
37 *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF); in bfin_iwr_save()
|
| D | defBF561.h | 45 #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ macro
|
| D | cdefBF561.h | 56 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
57 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
|
| /arch/blackfin/mach-common/ |
| D | clocks-init.c | 67 #ifdef SIC_IWR0 in init_clocks()
|
| D | dpmc_modes.S | 258 #ifdef SIC_IWR0
261 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
|
| D | pm.c | 49 #ifdef SIC_IWR0 in bfin_pm_suspend_standby_enter()
|
| D | ints-priority.c | 1104 #ifdef SIC_IWR0 in init_arch_irq()
|
| /arch/blackfin/include/asm/ |
| D | dpmc.h | 219 #ifdef SIC_IWR0
220 PM_SYS_PUSH(1, SIC_IWR0)
319 #ifdef SIC_IWR0
320 PM_SYS_POP(1, SIC_IWR0)
|
| /arch/blackfin/mach-bf518/include/mach/ |
| D | cdefBF512.h | 50 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
|
| D | defBF512.h | 33 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
|
| /arch/blackfin/mach-bf527/include/mach/ |
| D | cdefBF522.h | 50 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
|
| D | defBF522.h | 36 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
|
| /arch/blackfin/mach-bf538/include/mach/ |
| D | cdefBF538.h | 40 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
41 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
44 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
45 #define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
|
| D | defBF538.h | 33 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
|
| /arch/blackfin/mach-bf548/include/mach/ |
| D | defBF54x_base.h | 45 #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ macro
|
| D | cdefBF54x_base.h | 59 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
60 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
|
| /arch/blackfin/kernel/ |
| D | debug-mmrs.c | 1493 D32(SIC_IWR0); in bfin_debug_mmrs_init()
|