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Searched refs:SIMM (Results 1 – 4 of 4) sorted by relevance

/arch/mips/mm/
Duasm-mips.c52 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
66 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
70 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
97 { insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
98 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
100 { insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
108 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
109 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
[all …]
Duasm-micromips.c45 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
55 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
76 { insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
78 { insn_lh, M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
79 { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
81 { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
82 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
90 { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
92 { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
98 { insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
[all …]
Duasm.c21 SIMM = 0x010, enumerator
/arch/powerpc/xmon/
Dppc-opc.c534 #define SIMM VD + 1 macro
538 #define UIMM SIMM + 1
2224 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2225 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2226 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2295 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2296 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },