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Searched refs:SPI1_CTL (Results 1 – 7 of 7) sorted by relevance

/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h718 #define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ macro
725 #define SPI1_REGBASE SPI1_CTL
DcdefBF538.h158 #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
159 #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h87 #define SPI1_CTL 0xFFC03400 /* SPI Control Register */ macro
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h965 #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ macro
DcdefBF54x_base.h1650 #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
1651 #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h1313 #define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */ macro
DcdefBF60x_base.h160 #define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
161 #define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)