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Searched refs:SPRN_MMCR0 (Results 1 – 10 of 10) sorted by relevance

/arch/powerpc/kernel/
Dpmc.c34 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO)); in dummy_perf()
36 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE); in dummy_perf()
Dcpu_setup_power.S179 mtspr SPRN_MMCR0,r5
Dsysfs.c467 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
/arch/powerpc/oprofile/
Dop_model_power4.c182 mtspr(SPRN_MMCR0, mmcr0); in power4_cpu_setup()
186 mtspr(SPRN_MMCR0, mmcr0); in power4_cpu_setup()
195 mfspr(SPRN_MMCR0)); in power4_cpu_setup()
220 mmcr0 = mfspr(SPRN_MMCR0); in power4_start()
234 mtspr(SPRN_MMCR0, mmcr0); in power4_start()
247 mmcr0 = mfspr(SPRN_MMCR0); in power4_stop()
249 mtspr(SPRN_MMCR0, mmcr0); in power4_stop()
412 mmcr0 = mfspr(SPRN_MMCR0); in power4_handle_interrupt()
433 mtspr(SPRN_MMCR0, mmcr0); in power4_handle_interrupt()
Dop_model_7450.c61 u32 mmcr0 = mfspr(SPRN_MMCR0); in pmc_start_ctrs()
66 mtspr(SPRN_MMCR0, mmcr0); in pmc_start_ctrs()
72 u32 mmcr0 = mfspr(SPRN_MMCR0); in pmc_stop_ctrs()
77 mtspr(SPRN_MMCR0, mmcr0); in pmc_stop_ctrs()
87 mtspr(SPRN_MMCR0, mmcr0_val); in fsl7450_cpu_setup()
/arch/powerpc/kvm/
Dbook3s_hv_interrupts.S84 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
85 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
Dbook3s_emulate.c497 case SPRN_MMCR0: in kvmppc_core_emulate_mtspr_pr()
639 case SPRN_MMCR0: in kvmppc_core_emulate_mfspr_pr()
Dbook3s_hv_rmhandlers.S132 mtspr SPRN_MMCR0, r3
659 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
708 mtspr SPRN_MMCR0, r3
1306 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1307 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2608 mtspr SPRN_MMCR0, r3
/arch/powerpc/perf/
Dcore-book3s.c676 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); in pmao_restore_workaround()
679 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); in pmao_restore_workaround()
799 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); in perf_event_print_debug()
1118 mtspr(SPRN_MMCR0, mmcr0); in write_mmcr0()
1132 "i" (SPRN_MMCR0), in write_mmcr0()
1145 mtspr(SPRN_MMCR0, mmcr0); in write_mmcr0()
1174 val = mmcr0 = mfspr(SPRN_MMCR0); in power_pmu_disable()
1292 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) in power_pmu_enable()
/arch/powerpc/include/asm/
Dreg.h677 #define SPRN_MMCR0 795 macro
851 #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ macro