1 /* 2 * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes 3 * 4 * Copyright (c) 2005-2008 Analog Devices Inc. 5 * Copyright (C) 2005 John DeHority 6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) 7 * 8 * Licensed under the GPL-2. 9 */ 10 11 #ifndef _BLACKFIN_TIMERS_H_ 12 #define _BLACKFIN_TIMERS_H_ 13 14 #include <linux/types.h> 15 #include <asm/blackfin.h> 16 17 /* 18 * BF51x/BF52x/BF537: 8 timers: 19 */ 20 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY) 21 # define MAX_BLACKFIN_GPTIMERS 8 22 # define TIMER0_GROUP_REG TIMER_ENABLE 23 #endif 24 /* 25 * BF54x: 11 timers (BF542: 8 timers): 26 */ 27 #if defined(CONFIG_BF54x) 28 # ifdef CONFIG_BF542 29 # define MAX_BLACKFIN_GPTIMERS 8 30 # else 31 # define MAX_BLACKFIN_GPTIMERS 11 32 # define TIMER8_GROUP_REG TIMER_ENABLE1 33 # define TIMER_GROUP2 1 34 # endif 35 # define TIMER0_GROUP_REG TIMER_ENABLE0 36 #endif 37 /* 38 * BF561: 12 timers: 39 */ 40 #if defined(CONFIG_BF561) 41 # define MAX_BLACKFIN_GPTIMERS 12 42 # define TIMER0_GROUP_REG TMRS8_ENABLE 43 # define TIMER8_GROUP_REG TMRS4_ENABLE 44 # define TIMER_GROUP2 1 45 #endif 46 /* 47 * BF609: 8 timers: 48 */ 49 #if defined(CONFIG_BF60x) 50 # define MAX_BLACKFIN_GPTIMERS 8 51 # define TIMER0_GROUP_REG TIMER_RUN 52 #endif 53 /* 54 * All others: 3 timers: 55 */ 56 #define TIMER_GROUP1 0 57 #if !defined(MAX_BLACKFIN_GPTIMERS) 58 # define MAX_BLACKFIN_GPTIMERS 3 59 # define TIMER0_GROUP_REG TIMER_ENABLE 60 #endif 61 62 #define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1) 63 #define BFIN_TIMER_OCTET(x) ((x) >> 3) 64 65 /* used in masks for timer_enable() and timer_disable() */ 66 #define TIMER0bit 0x0001 /* 0001b */ 67 #define TIMER1bit 0x0002 /* 0010b */ 68 #define TIMER2bit 0x0004 /* 0100b */ 69 #define TIMER3bit 0x0008 70 #define TIMER4bit 0x0010 71 #define TIMER5bit 0x0020 72 #define TIMER6bit 0x0040 73 #define TIMER7bit 0x0080 74 #define TIMER8bit 0x0100 75 #define TIMER9bit 0x0200 76 #define TIMER10bit 0x0400 77 #define TIMER11bit 0x0800 78 79 #define TIMER0_id 0 80 #define TIMER1_id 1 81 #define TIMER2_id 2 82 #define TIMER3_id 3 83 #define TIMER4_id 4 84 #define TIMER5_id 5 85 #define TIMER6_id 6 86 #define TIMER7_id 7 87 #define TIMER8_id 8 88 #define TIMER9_id 9 89 #define TIMER10_id 10 90 #define TIMER11_id 11 91 92 /* associated timers for ppi framesync: */ 93 94 #if defined(CONFIG_BF561) 95 # define FS0_1_TIMER_ID TIMER8_id 96 # define FS0_2_TIMER_ID TIMER9_id 97 # define FS1_1_TIMER_ID TIMER10_id 98 # define FS1_2_TIMER_ID TIMER11_id 99 # define FS0_1_TIMER_BIT TIMER8bit 100 # define FS0_2_TIMER_BIT TIMER9bit 101 # define FS1_1_TIMER_BIT TIMER10bit 102 # define FS1_2_TIMER_BIT TIMER11bit 103 # undef FS1_TIMER_ID 104 # undef FS2_TIMER_ID 105 # undef FS1_TIMER_BIT 106 # undef FS2_TIMER_BIT 107 #else 108 # define FS1_TIMER_ID TIMER0_id 109 # define FS2_TIMER_ID TIMER1_id 110 # define FS1_TIMER_BIT TIMER0bit 111 # define FS2_TIMER_BIT TIMER1bit 112 #endif 113 114 #ifdef CONFIG_BF60x 115 /* 116 * Timer Configuration Register Bits 117 */ 118 #define TIMER_EMU_RUN 0x8000 119 #define TIMER_BPER_EN 0x4000 120 #define TIMER_BWID_EN 0x2000 121 #define TIMER_BDLY_EN 0x1000 122 #define TIMER_OUT_DIS 0x0800 123 #define TIMER_TIN_SEL 0x0400 124 #define TIMER_CLK_SEL 0x0300 125 #define TIMER_CLK_SCLK 0x0000 126 #define TIMER_CLK_ALT_CLK0 0x0100 127 #define TIMER_CLK_ALT_CLK1 0x0300 128 #define TIMER_PULSE_HI 0x0080 129 #define TIMER_SLAVE_TRIG 0x0040 130 #define TIMER_IRQ_MODE 0x0030 131 #define TIMER_IRQ_ACT_EDGE 0x0000 132 #define TIMER_IRQ_DLY 0x0010 133 #define TIMER_IRQ_WID_DLY 0x0020 134 #define TIMER_IRQ_PER 0x0030 135 #define TIMER_MODE 0x000f 136 #define TIMER_MODE_WDOG_P 0x0008 137 #define TIMER_MODE_WDOG_W 0x0009 138 #define TIMER_MODE_PWM_CONT 0x000c 139 #define TIMER_MODE_PWM 0x000d 140 #define TIMER_MODE_WDTH 0x000a 141 #define TIMER_MODE_WDTH_D 0x000b 142 #define TIMER_MODE_EXT_CLK 0x000e 143 #define TIMER_MODE_PININT 0x000f 144 145 /* 146 * Timer Status Register Bits 147 */ 148 #define TIMER_STATUS_TIMIL0 0x0001 149 #define TIMER_STATUS_TIMIL1 0x0002 150 #define TIMER_STATUS_TIMIL2 0x0004 151 #define TIMER_STATUS_TIMIL3 0x0008 152 #define TIMER_STATUS_TIMIL4 0x0010 153 #define TIMER_STATUS_TIMIL5 0x0020 154 #define TIMER_STATUS_TIMIL6 0x0040 155 #define TIMER_STATUS_TIMIL7 0x0080 156 157 #define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */ 158 #define TIMER_STATUS_TOVF1 0x0002 159 #define TIMER_STATUS_TOVF2 0x0004 160 #define TIMER_STATUS_TOVF3 0x0008 161 #define TIMER_STATUS_TOVF4 0x0010 162 #define TIMER_STATUS_TOVF5 0x0020 163 #define TIMER_STATUS_TOVF6 0x0040 164 #define TIMER_STATUS_TOVF7 0x0080 165 166 /* 167 * Timer Slave Enable Status : write 1 to clear 168 */ 169 #define TIMER_STATUS_TRUN0 0x0001 170 #define TIMER_STATUS_TRUN1 0x0002 171 #define TIMER_STATUS_TRUN2 0x0004 172 #define TIMER_STATUS_TRUN3 0x0008 173 #define TIMER_STATUS_TRUN4 0x0010 174 #define TIMER_STATUS_TRUN5 0x0020 175 #define TIMER_STATUS_TRUN6 0x0040 176 #define TIMER_STATUS_TRUN7 0x0080 177 178 #else 179 180 /* 181 * Timer Configuration Register Bits 182 */ 183 #define TIMER_ERR 0xC000 184 #define TIMER_ERR_OVFL 0x4000 185 #define TIMER_ERR_PROG_PER 0x8000 186 #define TIMER_ERR_PROG_PW 0xC000 187 #define TIMER_EMU_RUN 0x0200 188 #define TIMER_TOGGLE_HI 0x0100 189 #define TIMER_CLK_SEL 0x0080 190 #define TIMER_OUT_DIS 0x0040 191 #define TIMER_TIN_SEL 0x0020 192 #define TIMER_IRQ_ENA 0x0010 193 #define TIMER_PERIOD_CNT 0x0008 194 #define TIMER_PULSE_HI 0x0004 195 #define TIMER_MODE 0x0003 196 #define TIMER_MODE_PWM 0x0001 197 #define TIMER_MODE_WDTH 0x0002 198 #define TIMER_MODE_EXT_CLK 0x0003 199 200 /* 201 * Timer Status Register Bits 202 */ 203 #define TIMER_STATUS_TIMIL0 0x0001 204 #define TIMER_STATUS_TIMIL1 0x0002 205 #define TIMER_STATUS_TIMIL2 0x0004 206 #define TIMER_STATUS_TIMIL3 0x00000008 207 #define TIMER_STATUS_TIMIL4 0x00010000 208 #define TIMER_STATUS_TIMIL5 0x00020000 209 #define TIMER_STATUS_TIMIL6 0x00040000 210 #define TIMER_STATUS_TIMIL7 0x00080000 211 #define TIMER_STATUS_TIMIL8 0x0001 212 #define TIMER_STATUS_TIMIL9 0x0002 213 #define TIMER_STATUS_TIMIL10 0x0004 214 #define TIMER_STATUS_TIMIL11 0x0008 215 216 #define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ 217 #define TIMER_STATUS_TOVF1 0x0020 218 #define TIMER_STATUS_TOVF2 0x0040 219 #define TIMER_STATUS_TOVF3 0x00000080 220 #define TIMER_STATUS_TOVF4 0x00100000 221 #define TIMER_STATUS_TOVF5 0x00200000 222 #define TIMER_STATUS_TOVF6 0x00400000 223 #define TIMER_STATUS_TOVF7 0x00800000 224 #define TIMER_STATUS_TOVF8 0x0010 225 #define TIMER_STATUS_TOVF9 0x0020 226 #define TIMER_STATUS_TOVF10 0x0040 227 #define TIMER_STATUS_TOVF11 0x0080 228 229 /* 230 * Timer Slave Enable Status : write 1 to clear 231 */ 232 #define TIMER_STATUS_TRUN0 0x1000 233 #define TIMER_STATUS_TRUN1 0x2000 234 #define TIMER_STATUS_TRUN2 0x4000 235 #define TIMER_STATUS_TRUN3 0x00008000 236 #define TIMER_STATUS_TRUN4 0x10000000 237 #define TIMER_STATUS_TRUN5 0x20000000 238 #define TIMER_STATUS_TRUN6 0x40000000 239 #define TIMER_STATUS_TRUN7 0x80000000 240 #define TIMER_STATUS_TRUN 0xF000F000 241 #define TIMER_STATUS_TRUN8 0x1000 242 #define TIMER_STATUS_TRUN9 0x2000 243 #define TIMER_STATUS_TRUN10 0x4000 244 #define TIMER_STATUS_TRUN11 0x8000 245 246 #endif 247 248 /* The actual gptimer API */ 249 250 void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); 251 uint32_t get_gptimer_pwidth(unsigned int timer_id); 252 void set_gptimer_period(unsigned int timer_id, uint32_t period); 253 uint32_t get_gptimer_period(unsigned int timer_id); 254 #ifdef CONFIG_BF60x 255 void set_gptimer_delay(unsigned int timer_id, uint32_t delay); 256 uint32_t get_gptimer_delay(unsigned int timer_id); 257 #endif 258 uint32_t get_gptimer_count(unsigned int timer_id); 259 int get_gptimer_intr(unsigned int timer_id); 260 void clear_gptimer_intr(unsigned int timer_id); 261 int get_gptimer_over(unsigned int timer_id); 262 void clear_gptimer_over(unsigned int timer_id); 263 void set_gptimer_config(unsigned int timer_id, uint16_t config); 264 uint16_t get_gptimer_config(unsigned int timer_id); 265 int get_gptimer_run(unsigned int timer_id); 266 void set_gptimer_pulse_hi(unsigned int timer_id); 267 void clear_gptimer_pulse_hi(unsigned int timer_id); 268 void enable_gptimers(uint16_t mask); 269 void disable_gptimers(uint16_t mask); 270 void disable_gptimers_sync(uint16_t mask); 271 uint16_t get_enabled_gptimers(void); 272 uint32_t get_gptimer_status(unsigned int group); 273 void set_gptimer_status(unsigned int group, uint32_t value); 274 enable_gptimer(unsigned int timer_id)275static inline void enable_gptimer(unsigned int timer_id) 276 { 277 enable_gptimers(1 << timer_id); 278 } 279 disable_gptimer(unsigned int timer_id)280static inline void disable_gptimer(unsigned int timer_id) 281 { 282 disable_gptimers(1 << timer_id); 283 } 284 285 /* 286 * All Blackfin system MMRs are padded to 32bits even if the register 287 * itself is only 16bits. So use a helper macro to streamline this. 288 */ 289 #define __BFP(m) u16 m; u16 __pad_##m 290 291 /* 292 * bfin timer registers layout 293 */ 294 struct bfin_gptimer_regs { 295 __BFP(config); 296 u32 counter; 297 u32 period; 298 u32 width; 299 #ifdef CONFIG_BF60x 300 u32 delay; 301 #endif 302 }; 303 304 /* 305 * bfin group timer registers layout 306 */ 307 #ifndef CONFIG_BF60x 308 struct bfin_gptimer_group_regs { 309 __BFP(enable); 310 __BFP(disable); 311 u32 status; 312 }; 313 #else 314 struct bfin_gptimer_group_regs { 315 __BFP(run); 316 __BFP(enable); 317 __BFP(disable); 318 __BFP(stop_cfg); 319 __BFP(stop_cfg_set); 320 __BFP(stop_cfg_clr); 321 __BFP(data_imsk); 322 __BFP(stat_imsk); 323 __BFP(tr_msk); 324 __BFP(tr_ie); 325 __BFP(data_ilat); 326 __BFP(stat_ilat); 327 __BFP(err_status); 328 __BFP(bcast_per); 329 __BFP(bcast_wid); 330 __BFP(bcast_dly); 331 332 }; 333 #endif 334 335 #undef __BFP 336 337 #endif 338