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Searched refs:TREG_ZERO (Results 1 – 7 of 7) sorted by relevance

/arch/tile/kernel/
Dtile-desc_64.c27 #define TREG_ZERO 63 macro
34 { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
37 { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
40 { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
43 { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
46 { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
49 { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
52 { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
55 { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
58 { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
[all …]
Dtile-desc_32.c27 #define TREG_ZERO 63 macro
34 { "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
37 { "info", TILEPRO_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
40 { "infol", TILEPRO_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
43 { "j", TILEPRO_OPC_J, 0x2, 1, TREG_ZERO, 1,
49 { "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
55 { "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
61 { "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
70 { "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
73 { "raise", TILEPRO_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
[all …]
Dsingle_step.c74 create_SrcB_X1(TREG_ZERO) | in move_X1()
83 return move_X1(n, TREG_ZERO, TREG_ZERO); in nop_X1()
147 (val_reg != TREG_ZERO || in rewrite_load_store_unaligned()
198 val = (val_reg == TREG_ZERO) ? 0 : regs->regs[val_reg]; in rewrite_load_store_unaligned()
253 bundle |= (create_SrcBDest_Y2(TREG_ZERO) | in rewrite_load_store_unaligned()
391 BUG_ON(get_SrcA_X1(__single_step_addli_insn) != TREG_ZERO); in single_step_once()
Dtraps.c149 if (get_Dest_X0(bundle) != TREG_ZERO) in special_ill()
151 if (get_SrcA_X0(bundle) != TREG_ZERO) in special_ill()
Dunaligned.c319 if ((ra >= 56) && (ra != TREG_ZERO)) in check_regs()
326 if ((rd >= 56) && (rd != TREG_ZERO)) in check_regs()
329 if ((rb >= 56) && (rb != TREG_ZERO)) in check_regs()
836 && (get_SrcA_Y1(bundle) == TREG_ZERO) && in jit_bundle_gen()
842 (get_SrcA_Y0(bundle) == TREG_ZERO) && in jit_bundle_gen()
859 (get_SrcA_X0(bundle) == TREG_ZERO) && in jit_bundle_gen()
1185 jit_x0_addi(clob2, TREG_ZERO, 7) | in jit_bundle_gen()
1198 jit_x0_addi(clob2, TREG_ZERO, 3) | in jit_bundle_gen()
Dftrace.c82 create_SrcB_X0(TREG_ZERO) | in ftrace_gen_branch()
/arch/tile/include/uapi/arch/
Dabi.h113 #define TREG_ZERO 63 /**< "Zero" register; always reads as "0". */ macro